ATE504037T1 - APPARATUS AND METHOD FOR CONFIGURABLE PROCESSING - Google Patents

APPARATUS AND METHOD FOR CONFIGURABLE PROCESSING

Info

Publication number
ATE504037T1
ATE504037T1 AT06727002T AT06727002T ATE504037T1 AT E504037 T1 ATE504037 T1 AT E504037T1 AT 06727002 T AT06727002 T AT 06727002T AT 06727002 T AT06727002 T AT 06727002T AT E504037 T1 ATE504037 T1 AT E504037T1
Authority
AT
Austria
Prior art keywords
instruction
configurable
operator
unit comprises
configuration information
Prior art date
Application number
AT06727002T
Other languages
German (de)
Inventor
Simon Knowles
Original Assignee
Icera Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icera Inc filed Critical Icera Inc
Application granted granted Critical
Publication of ATE504037T1 publication Critical patent/ATE504037T1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path

Abstract

A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more dynamically configurable operator modules, each module being connectable to receive input operands indicated in an instruction, and a programmable lookup table connectable to receive dynamic configuration information determined from an opcode portion of the instruction and capable of generating operator configuration settings defining an aspect of the function or behavior of a configurable operator module, responsive to said dynamic configuration information in the instruction.
AT06727002T 2005-05-05 2006-05-04 APPARATUS AND METHOD FOR CONFIGURABLE PROCESSING ATE504037T1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/122,385 US8966223B2 (en) 2005-05-05 2005-05-05 Apparatus and method for configurable processing
PCT/GB2006/001629 WO2006117562A1 (en) 2005-05-05 2006-05-04 Apparatus and method for configurable processing

Publications (1)

Publication Number Publication Date
ATE504037T1 true ATE504037T1 (en) 2011-04-15

Family

ID=36659717

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06727002T ATE504037T1 (en) 2005-05-05 2006-05-04 APPARATUS AND METHOD FOR CONFIGURABLE PROCESSING

Country Status (10)

Country Link
US (2) US8966223B2 (en)
EP (1) EP1877896B1 (en)
JP (1) JP4806009B2 (en)
KR (1) KR20080015836A (en)
CN (1) CN101218560B (en)
AT (1) ATE504037T1 (en)
CA (1) CA2606558A1 (en)
DE (1) DE602006021000D1 (en)
TW (1) TWI439928B (en)
WO (1) WO2006117562A1 (en)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007193435A (en) * 2006-01-17 2007-08-02 Matsushita Electric Ind Co Ltd Information processing terminal and program
US8099583B2 (en) * 2006-08-23 2012-01-17 Axis Semiconductor, Inc. Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing
US8276120B2 (en) * 2007-10-30 2012-09-25 Coreworks, S.A. Reconfigurable coprocessor architecture template for nested loops and programming tool
GB0721429D0 (en) 2007-10-31 2007-12-12 Icera Inc Processing signals in a wireless communications environment
GB0721427D0 (en) 2007-10-31 2007-12-12 Icera Inc Processing signals in a wireless newtwork
GB2454914B (en) 2007-11-22 2012-07-25 Icera Inc Clock control
GB2459733B (en) 2008-04-30 2012-12-19 Icera Inc Clock configuration
GB2459939B (en) 2008-05-16 2012-02-15 Icera Inc Fetching descriptors in a multiple context DMA engine
US8181003B2 (en) * 2008-05-29 2012-05-15 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cores and the like
US8078833B2 (en) * 2008-05-29 2011-12-13 Axis Semiconductor, Inc. Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
CN101630305B (en) * 2008-07-16 2011-05-11 中国人民解放军信息工程大学 Flexible management method for reconfigurable components in high-efficiency computer
GB0818918D0 (en) 2008-10-15 2008-11-19 Icera Inc Boot algorithm
US9170816B2 (en) * 2009-01-15 2015-10-27 Altair Semiconductor Ltd. Enhancing processing efficiency in large instruction width processors
GB2466982B (en) 2009-01-16 2013-07-17 Nvidia Technology Uk Ltd DMA Engine
GB2467760B (en) 2009-02-12 2013-05-22 Icera Inc Method for generating transmitter power amplifier ramp profiles from a single reference ramp pattern
GB0910850D0 (en) 2009-06-23 2009-08-05 Icera Inc Processing signals in a wireless network
JP5785357B2 (en) * 2009-06-25 2015-09-30 スパンション エルエルシー Computer system provided with reconfiguration arithmetic device and reconfiguration arithmetic device
CN102043755B (en) * 2009-10-22 2012-12-05 财团法人工业技术研究院 Reconfigurable processing device and system
GB2483225B (en) 2010-08-27 2018-07-11 Nvidia Tech Uk Limited Improved processor architecture
KR20120134549A (en) 2011-06-02 2012-12-12 삼성전자주식회사 Apparatus and method for processing parallel computation using simd architecture
US10255228B2 (en) * 2011-12-06 2019-04-09 Nvidia Corporation System and method for performing shaped memory access operations
US9558006B2 (en) * 2012-12-20 2017-01-31 Intel Corporation Continuous automatic tuning of code regions
US10001993B2 (en) 2013-08-08 2018-06-19 Linear Algebra Technologies Limited Variable-length instruction buffer management
US11768689B2 (en) 2013-08-08 2023-09-26 Movidius Limited Apparatus, systems, and methods for low power computational imaging
US10019260B2 (en) * 2013-09-20 2018-07-10 Via Alliance Semiconductor Co., Ltd Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match
CN106796504B (en) * 2014-07-30 2019-08-13 线性代数技术有限公司 Method and apparatus for managing variable length instruction
EP3125109B1 (en) 2015-07-31 2019-02-20 ARM Limited Vector length querying instruction
US10860322B2 (en) * 2015-10-30 2020-12-08 Arm Limited Modifying behavior of a data processing unit using rewritable behavior mappings of instructions
US9977677B2 (en) * 2016-04-07 2018-05-22 International Business Machines Corporation Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port
US9734126B1 (en) 2016-10-10 2017-08-15 International Business Machines Corporation Post-silicon configurable instruction behavior based on input operands
US10963265B2 (en) * 2017-04-21 2021-03-30 Micron Technology, Inc. Apparatus and method to switch configurable logic units
US10409615B2 (en) * 2017-06-19 2019-09-10 The Regents Of The University Of Michigan Configurable arithmetic unit
JP7032647B2 (en) * 2018-04-17 2022-03-09 富士通株式会社 Arithmetic processing unit and control method of arithmetic processing unit
US10565036B1 (en) 2019-02-14 2020-02-18 Axis Semiconductor, Inc. Method of synchronizing host and coprocessor operations via FIFO communication
US11500644B2 (en) * 2020-05-15 2022-11-15 Alibaba Group Holding Limited Custom instruction implemented finite state machine engines for extensible processors
CN112783614A (en) * 2021-01-20 2021-05-11 北京百度网讯科技有限公司 Object processing method, device, equipment, storage medium and program product
EP4080354A1 (en) * 2021-04-23 2022-10-26 Nxp B.V. Processor and instruction set

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US6052773A (en) * 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5784636A (en) * 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
JPH118547A (en) 1997-06-17 1999-01-12 Fuji Xerox Co Ltd Reconfigurable arithmetic unit
US6339819B1 (en) * 1997-12-17 2002-01-15 Src Computers, Inc. Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer
US6226735B1 (en) * 1998-05-08 2001-05-01 Broadcom Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements
US6092174A (en) * 1998-06-01 2000-07-18 Context, Inc. Dynamically reconfigurable distributed integrated circuit processor and method
US6961084B1 (en) * 1999-10-07 2005-11-01 Ess Technology, Inc. Programmable image transform processor
US6255849B1 (en) * 2000-02-04 2001-07-03 Xilinx, Inc. On-chip self-modification for PLDs
KR100457040B1 (en) * 2000-06-21 2004-11-10 패러데이 테크놀로지 코퍼레이션 Apparatus and method for data processing using multiply-accumulate instructions
US6959378B2 (en) * 2000-11-06 2005-10-25 Broadcom Corporation Reconfigurable processing system and method
US20070067380A2 (en) * 2001-12-06 2007-03-22 The University Of Georgia Research Foundation Floating Point Intensive Reconfigurable Computing System for Iterative Applications
WO2003081454A2 (en) * 2002-03-21 2003-10-02 Pact Xpp Technologies Ag Method and device for data processing
US7200735B2 (en) * 2002-04-10 2007-04-03 Tensilica, Inc. High-performance hybrid processor with configurable execution units
WO2004010320A2 (en) * 2002-07-23 2004-01-29 Gatechance Technologies, Inc. Pipelined reconfigurable dynamic instruciton set processor
WO2004010286A2 (en) 2002-07-23 2004-01-29 Gatechange Technologies, Inc. Self-configuring processing element
AU2003286131A1 (en) * 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US20040122887A1 (en) * 2002-12-20 2004-06-24 Macy William W. Efficient multiplication of small matrices using SIMD registers
US7149996B1 (en) * 2003-07-11 2006-12-12 Xilinx, Inc. Reconfigurable multi-stage crossbar
JP2006065788A (en) * 2004-08-30 2006-03-09 Sanyo Electric Co Ltd Processor with reconfigurable circuit

Also Published As

Publication number Publication date
JP2008541216A (en) 2008-11-20
WO2006117562A1 (en) 2006-11-09
US20060253689A1 (en) 2006-11-09
US8671268B2 (en) 2014-03-11
JP4806009B2 (en) 2011-11-02
US20110161640A1 (en) 2011-06-30
TW200707280A (en) 2007-02-16
TWI439928B (en) 2014-06-01
KR20080015836A (en) 2008-02-20
US8966223B2 (en) 2015-02-24
EP1877896A1 (en) 2008-01-16
CA2606558A1 (en) 2006-11-09
CN101218560B (en) 2012-06-06
EP1877896B1 (en) 2011-03-30
DE602006021000D1 (en) 2011-05-12
CN101218560A (en) 2008-07-09

Similar Documents

Publication Publication Date Title
ATE504037T1 (en) APPARATUS AND METHOD FOR CONFIGURABLE PROCESSING
DE602006014415D1 (en) Synchronization and parallel execution of control flow and data flow on task level
ATE443886T1 (en) CRYPTOGRAPHIC PROCESSING OF DATA BASED ON THE CASSELS-TATE PAIRING
ATE493703T1 (en) PROGRAMMABLE DATA PROCESSING CIRCUIT THAT SUPPORTS SIMD INSTRUCTIONS
DE602006012567D1 (en) Method and apparatus for direct input and output in a virtual machine environment
GB2429554A (en) Method and apparatus to vectorize multiple input instructions
GB2456775B (en) Apparatus and method for performing permutation operations on data
ATE476066T1 (en) METHOD AND DEVICE FOR RECONFIGURING A COMMON CHANNEL
SG144700A1 (en) A method, apparatus, and instruction for performing a sign operation that multiplies
TR201907717T4 (en) Sieve machine and sieving method.
DE502006009123D1 (en) HAND MACHINE TOOL
WO2008002730A3 (en) Method and system for rapidly developing and deploying sens0r-enabled software applications
IN2014CN02111A (en)
WO2007078913A3 (en) Cross-architecture execution optimization
DE502006005141D1 (en) DEVICE, SERIES OF EQUIPMENT, DEVICE WITH HOUSING USING A LIQUID CHILLER
TW200704563A (en) Signal generating apparatus for a bicycle control device
WO2007095397A3 (en) Programmable processing unit
TW200738059A (en) Ambience control
ATE484790T1 (en) METHOD AND DEVICE FOR GENERATING RANDOM DATA
ATE530340T1 (en) PLATE CUTTING
TW200713032A (en) Methods and apparatus for dynamically switching processor mode
ATE478376T1 (en) ARITHMETIC LOGIC AND SWITCHING DEVICE FOR USE IN A PROCESSOR
DE502006008834D1 (en) FIELD DEVICE
ATE519145T1 (en) METHOD FOR PARAMETIZING EQUIPMENT
DE602006016443D1 (en) Arrangement, method and computer program for advanced forecasts

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties