ATE495652T1 - Verfahren zur herstellung von elektrischen bondkontaktstellen auf einem wafer - Google Patents

Verfahren zur herstellung von elektrischen bondkontaktstellen auf einem wafer

Info

Publication number
ATE495652T1
ATE495652T1 AT08774406T AT08774406T ATE495652T1 AT E495652 T1 ATE495652 T1 AT E495652T1 AT 08774406 T AT08774406 T AT 08774406T AT 08774406 T AT08774406 T AT 08774406T AT E495652 T1 ATE495652 T1 AT E495652T1
Authority
AT
Austria
Prior art keywords
wafer
blocks
producing electrical
electrical bond
bond contacts
Prior art date
Application number
AT08774406T
Other languages
English (en)
Inventor
Romain Coffy
Jacky Seiller
Gil Provent
Original Assignee
St Microelectronics Grenoble
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Grenoble filed Critical St Microelectronics Grenoble
Application granted granted Critical
Publication of ATE495652T1 publication Critical patent/ATE495652T1/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0574—Stacked resist layers used for different processes
    • H10W72/012—
    • H10W72/01255—
    • H10W72/01257—
    • H10W72/019—
    • H10W72/0198—
    • H10W72/07251—
    • H10W72/20—
    • H10W72/227—
    • H10W72/252—
    • H10W72/29—
    • H10W72/90—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
AT08774406T 2007-08-29 2008-06-27 Verfahren zur herstellung von elektrischen bondkontaktstellen auf einem wafer ATE495652T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0757254A FR2920634A1 (fr) 2007-08-29 2007-08-29 Procede de fabrication de plots de connexion electrique d'une plaque.
PCT/EP2008/058239 WO2009027132A1 (en) 2007-08-29 2008-06-27 Method for fabricating electrical bonding pads on a wafer

Publications (1)

Publication Number Publication Date
ATE495652T1 true ATE495652T1 (de) 2011-01-15

Family

ID=39264520

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08774406T ATE495652T1 (de) 2007-08-29 2008-06-27 Verfahren zur herstellung von elektrischen bondkontaktstellen auf einem wafer

Country Status (7)

Country Link
US (1) US8148258B2 (de)
EP (1) EP2181569B1 (de)
CN (1) CN101803479B (de)
AT (1) ATE495652T1 (de)
DE (1) DE602008004552D1 (de)
FR (1) FR2920634A1 (de)
WO (1) WO2009027132A1 (de)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723387A1 (de) * 1995-01-19 1996-07-24 Digital Equipment Corporation Absperrung von Oberflächenmontage-Kontaktflächen einer Leiterplatte durch eine Lötstopmaske
ATE240586T1 (de) 1995-04-05 2003-05-15 Unitive Int Ltd Eine löthöckerstruktur für ein mikroelektronisches substrat
US6042953A (en) * 1996-03-21 2000-03-28 Matsushita Electric Industrial Co., Ltd. Substrate on which bumps are formed and method of forming the same
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
TW483136B (en) * 2001-03-22 2002-04-11 Apack Technologies Inc Bump process
US6555296B2 (en) * 2001-04-04 2003-04-29 Siliconware Precision Industries Co., Ltd. Fine pitch wafer bumping process
TW536767B (en) * 2002-03-01 2003-06-11 Advanced Semiconductor Eng Solder ball attaching process
US6784089B2 (en) * 2003-01-13 2004-08-31 Aptos Corporation Flat-top bumping structure and preparation method
TWI227557B (en) * 2003-07-25 2005-02-01 Advanced Semiconductor Eng Bumping process
TWI322491B (en) * 2003-08-21 2010-03-21 Advanced Semiconductor Eng Bumping process
TWI259572B (en) * 2004-09-07 2006-08-01 Siliconware Precision Industries Co Ltd Bump structure of semiconductor package and fabrication method thereof
US7459386B2 (en) * 2004-11-16 2008-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming solder bumps of increased height

Also Published As

Publication number Publication date
WO2009027132A1 (en) 2009-03-05
FR2920634A1 (fr) 2009-03-06
EP2181569B1 (de) 2011-01-12
CN101803479B (zh) 2012-04-04
CN101803479A (zh) 2010-08-11
US8148258B2 (en) 2012-04-03
EP2181569A1 (de) 2010-05-05
US20110151657A1 (en) 2011-06-23
DE602008004552D1 (de) 2011-02-24

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties