ATE481675T1 - Arithmetische schaltung mit ausgeglichenen logikpegeln für betrieb mit niedriger stromaufnahme - Google Patents

Arithmetische schaltung mit ausgeglichenen logikpegeln für betrieb mit niedriger stromaufnahme

Info

Publication number
ATE481675T1
ATE481675T1 AT05724542T AT05724542T ATE481675T1 AT E481675 T1 ATE481675 T1 AT E481675T1 AT 05724542 T AT05724542 T AT 05724542T AT 05724542 T AT05724542 T AT 05724542T AT E481675 T1 ATE481675 T1 AT E481675T1
Authority
AT
Austria
Prior art keywords
adder
arithmetic circuit
current operation
low current
carry out
Prior art date
Application number
AT05724542T
Other languages
English (en)
Inventor
Kai Chirca
C Glossner
Original Assignee
Sandbridge Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandbridge Technologies Inc filed Critical Sandbridge Technologies Inc
Priority claimed from PCT/US2005/007021 external-priority patent/WO2005086675A2/en
Application granted granted Critical
Publication of ATE481675T1 publication Critical patent/ATE481675T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
AT05724542T 2004-03-05 2005-03-04 Arithmetische schaltung mit ausgeglichenen logikpegeln für betrieb mit niedriger stromaufnahme ATE481675T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US55091604P 2004-03-05 2004-03-05
PCT/US2005/007021 WO2005086675A2 (en) 2004-03-05 2005-03-04 Arithmetic circuit with balanced logic levels for low-power operation

Publications (1)

Publication Number Publication Date
ATE481675T1 true ATE481675T1 (de) 2010-10-15

Family

ID=37801598

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05724542T ATE481675T1 (de) 2004-03-05 2005-03-04 Arithmetische schaltung mit ausgeglichenen logikpegeln für betrieb mit niedriger stromaufnahme

Country Status (4)

Country Link
EP (1) EP1769335B1 (de)
CN (1) CN101065724A (de)
AT (1) ATE481675T1 (de)
DE (1) DE602005023614D1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10223071B2 (en) * 2017-04-14 2019-03-05 Qualcomm Incorporated Energy-efficient variable power adder and methods of use thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7325025B2 (en) * 2001-12-18 2008-01-29 Intel Corporation Look-ahead carry adder circuit

Also Published As

Publication number Publication date
DE602005023614D1 (de) 2010-10-28
EP1769335A4 (de) 2009-07-08
EP1769335B1 (de) 2010-09-15
CN101065724A (zh) 2007-10-31
EP1769335A2 (de) 2007-04-04

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Legal Events

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