ATE430427T1 - Verteilter automat - Google Patents

Verteilter automat

Info

Publication number
ATE430427T1
ATE430427T1 AT05702837T AT05702837T ATE430427T1 AT E430427 T1 ATE430427 T1 AT E430427T1 AT 05702837 T AT05702837 T AT 05702837T AT 05702837 T AT05702837 T AT 05702837T AT E430427 T1 ATE430427 T1 AT E430427T1
Authority
AT
Austria
Prior art keywords
module
state machine
memory
finite state
local information
Prior art date
Application number
AT05702837T
Other languages
English (en)
Inventor
Sylvain Monette
Mathieu Giguere
Martin Julien
Benoit Tremblay
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Application granted granted Critical
Publication of ATE430427T1 publication Critical patent/ATE430427T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/76—Routing in software-defined topologies, e.g. routing between virtual machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
AT05702837T 2004-02-02 2005-01-28 Verteilter automat ATE430427T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US54035104P 2004-02-02 2004-02-02
US11/038,205 US7411953B2 (en) 2004-02-02 2005-01-21 Distributed finite state machine
PCT/IB2005/050388 WO2005074203A1 (en) 2004-02-02 2005-01-28 Distributed finite state machine

Publications (1)

Publication Number Publication Date
ATE430427T1 true ATE430427T1 (de) 2009-05-15

Family

ID=34810518

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05702837T ATE430427T1 (de) 2004-02-02 2005-01-28 Verteilter automat

Country Status (5)

Country Link
US (1) US7411953B2 (de)
EP (1) EP1719305B1 (de)
AT (1) ATE430427T1 (de)
DE (1) DE602005014203D1 (de)
WO (1) WO2005074203A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7716610B2 (en) * 2007-01-05 2010-05-11 International Business Machines Corporation Distributable and serializable finite state machine
WO2008097710A2 (en) * 2007-02-02 2008-08-14 Tarari, Inc. Systems and methods for processing access control lists (acls) in network switches using regular expression matching logic
US8526435B2 (en) * 2010-03-19 2013-09-03 Telefonaktiebolaget L M Ericsson (Publ) Packet node for applying service path routing at the MAC layer
US20130016725A1 (en) * 2010-12-24 2013-01-17 Telefonaktiebolaget L M Ericsson (Publ) Method and system for intra-node header compression
US20140280850A1 (en) * 2013-03-15 2014-09-18 Lantronix, Inc. Collaborative State Machine Management

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592685A (en) * 1992-10-07 1997-01-07 Digital Equipment Corporation Synchronous/asynchronous partitioning of an asynchronous bus interface
JPH06131244A (ja) * 1992-10-20 1994-05-13 Fujitsu Ltd 共有メモリの非同期アクセス方式
US5649176A (en) * 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US6006340A (en) * 1998-03-27 1999-12-21 Phoenix Technologies Ltd. Communication interface between two finite state machines operating at different clock domains
WO2001086434A2 (en) 2000-05-08 2001-11-15 Transilica, Inc. Software modem architecture

Also Published As

Publication number Publication date
EP1719305A1 (de) 2006-11-08
US7411953B2 (en) 2008-08-12
DE602005014203D1 (de) 2009-06-10
US20050169286A1 (en) 2005-08-04
EP1719305B1 (de) 2009-04-29
WO2005074203A1 (en) 2005-08-11

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties