ATE413648T1 - Verfahren und vorrichtungen zur steuerung eines cache-speichers - Google Patents

Verfahren und vorrichtungen zur steuerung eines cache-speichers

Info

Publication number
ATE413648T1
ATE413648T1 AT02807417T AT02807417T ATE413648T1 AT E413648 T1 ATE413648 T1 AT E413648T1 AT 02807417 T AT02807417 T AT 02807417T AT 02807417 T AT02807417 T AT 02807417T AT E413648 T1 ATE413648 T1 AT E413648T1
Authority
AT
Austria
Prior art keywords
cache memory
controlling
cache
data
cache line
Prior art date
Application number
AT02807417T
Other languages
English (en)
Inventor
H Magoshi
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of ATE413648T1 publication Critical patent/ATE413648T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G06F12/127—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
AT02807417T 2002-05-06 2002-09-16 Verfahren und vorrichtungen zur steuerung eines cache-speichers ATE413648T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37819902P 2002-05-06 2002-05-06
US10/187,150 US6751707B2 (en) 2002-05-06 2002-07-01 Methods and apparatus for controlling a cache memory

Publications (1)

Publication Number Publication Date
ATE413648T1 true ATE413648T1 (de) 2008-11-15

Family

ID=29272738

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02807417T ATE413648T1 (de) 2002-05-06 2002-09-16 Verfahren und vorrichtungen zur steuerung eines cache-speichers

Country Status (8)

Country Link
US (1) US6751707B2 (de)
EP (1) EP1502191B1 (de)
JP (1) JP3974131B2 (de)
AT (1) ATE413648T1 (de)
AU (1) AU2002333656A1 (de)
DE (1) DE60229790D1 (de)
ES (1) ES2316653T3 (de)
WO (1) WO2003096194A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7774759B2 (en) * 2003-04-28 2010-08-10 Intel Corporation Methods and apparatus to detect a macroscopic transaction boundary in a program
US7647585B2 (en) * 2003-04-28 2010-01-12 Intel Corporation Methods and apparatus to detect patterns in programs
US8316048B2 (en) * 2004-08-17 2012-11-20 Hewlett-Packard Development Company, L.P. Method and apparatus for managing a data structure for multi-processor access
WO2006076405A1 (en) * 2005-01-11 2006-07-20 Avox Systems, Inc. Regulator with belleville springs
US7739662B2 (en) 2005-12-30 2010-06-15 Intel Corporation Methods and apparatus to analyze processor systems
JP6089890B2 (ja) * 2013-03-29 2017-03-08 富士通株式会社 ストレージ制御装置、ストレージ制御装置の制御方法およびストレージ制御装置の制御プログラム

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4942518A (en) * 1984-06-20 1990-07-17 Convex Computer Corporation Cache store bypass for computer
FR2664719A1 (fr) * 1990-07-10 1992-01-17 Philips Electronique Lab Dispositif de controle pour une memoire tampon a partitionnement reconfigurable.
US5353426A (en) 1992-04-29 1994-10-04 Sun Microsystems, Inc. Cache miss buffer adapted to satisfy read requests to portions of a cache fill in progress without waiting for the cache fill to complete
US5510934A (en) 1993-12-15 1996-04-23 Silicon Graphics, Inc. Memory system including local and global caches for storing floating point and integer data
US6877089B2 (en) * 2000-12-27 2005-04-05 International Business Machines Corporation Branch prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program
US6804799B2 (en) * 2001-06-26 2004-10-12 Advanced Micro Devices, Inc. Using type bits to track storage of ECC and predecode bits in a level two cache

Also Published As

Publication number Publication date
EP1502191B1 (de) 2008-11-05
AU2002333656A1 (en) 2003-11-11
US6751707B2 (en) 2004-06-15
WO2003096194A1 (en) 2003-11-20
US20030208661A1 (en) 2003-11-06
JP2005524905A (ja) 2005-08-18
DE60229790D1 (de) 2008-12-18
EP1502191A4 (de) 2007-04-04
EP1502191A1 (de) 2005-02-02
JP3974131B2 (ja) 2007-09-12
ES2316653T3 (es) 2009-04-16

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