ATE344494T1 - Hochgeschwindigkeits-interchip- schnittstellenprotokoll - Google Patents

Hochgeschwindigkeits-interchip- schnittstellenprotokoll

Info

Publication number
ATE344494T1
ATE344494T1 AT02781542T AT02781542T ATE344494T1 AT E344494 T1 ATE344494 T1 AT E344494T1 AT 02781542 T AT02781542 T AT 02781542T AT 02781542 T AT02781542 T AT 02781542T AT E344494 T1 ATE344494 T1 AT E344494T1
Authority
AT
Austria
Prior art keywords
data
pending
read
origination
write
Prior art date
Application number
AT02781542T
Other languages
English (en)
Inventor
Robert L Payne
David R Evoy
Timothy A Pontius
George Spatz
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE344494T1 publication Critical patent/ATE344494T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
AT02781542T 2001-11-29 2002-11-14 Hochgeschwindigkeits-interchip- schnittstellenprotokoll ATE344494T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/997,609 US6996106B2 (en) 2001-11-29 2001-11-29 High-speed interchip interface protocol

Publications (1)

Publication Number Publication Date
ATE344494T1 true ATE344494T1 (de) 2006-11-15

Family

ID=25544207

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02781542T ATE344494T1 (de) 2001-11-29 2002-11-14 Hochgeschwindigkeits-interchip- schnittstellenprotokoll

Country Status (7)

Country Link
US (1) US6996106B2 (de)
EP (1) EP1451698B1 (de)
JP (1) JP2005510798A (de)
AT (1) ATE344494T1 (de)
AU (1) AU2002348922A1 (de)
DE (1) DE60215853T2 (de)
WO (1) WO2003046731A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7058090B1 (en) * 2001-12-18 2006-06-06 Applied Micro Circuits Corporation System and method for paralleling digital wrapper data streams
US7602729B2 (en) * 2004-07-19 2009-10-13 Alcatel-Lucent Usa Inc. Slow-fast programming of distributed base stations in a wireless network
WO2006043320A1 (ja) * 2004-10-20 2006-04-27 Fujitsu Limited アプリケーション管理プログラム、アプリケーション管理方法、およびアプリケーション管理装置
US8429356B2 (en) * 2005-11-02 2013-04-23 Ati Technologies Ulc Write data mask method and system
WO2007097006A1 (ja) * 2006-02-24 2007-08-30 Fujitsu Limited パケット送出制御装置および方法
US9341676B2 (en) 2011-10-07 2016-05-17 Alcatel Lucent Packet-based propagation of testing information
US10203897B1 (en) 2016-12-02 2019-02-12 Nutanix, Inc. Dynamic data compression
CN111522588B (zh) * 2020-04-16 2023-05-05 珠海泰芯半导体有限公司 一种基于swd协议的芯片运行交互方法及通信系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644593A (en) * 1994-09-02 1997-07-01 Microcom Systems, Inc. High performance communications interface
US6263385B1 (en) * 1997-10-20 2001-07-17 Advanced Micro Devices, Inc. PC parallel port structure partitioned between two integrated circuits interconnected by a serial bus
US6009488A (en) * 1997-11-07 1999-12-28 Microlinc, Llc Computer having packet-based interconnect channel
US6611891B1 (en) * 1998-11-23 2003-08-26 Advanced Micro Devices, Inc. Computer resource configuration mechanism across a multi-pipe communication link
US6748442B1 (en) * 1998-12-21 2004-06-08 Advanced Micro Devices, Inc. Method and apparatus for using a control signal on a packet based communication link
US7003585B2 (en) * 2001-09-05 2006-02-21 Xerox Corporation High speed serial interface

Also Published As

Publication number Publication date
US20030099238A1 (en) 2003-05-29
DE60215853T2 (de) 2007-09-06
JP2005510798A (ja) 2005-04-21
WO2003046731A3 (en) 2004-06-10
US6996106B2 (en) 2006-02-07
EP1451698B1 (de) 2006-11-02
AU2002348922A8 (en) 2003-06-10
AU2002348922A1 (en) 2003-06-10
DE60215853D1 (de) 2006-12-14
WO2003046731A2 (en) 2003-06-05
EP1451698A2 (de) 2004-09-01

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Legal Events

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