ATE336764T1 - Verfahren und system zur kachelweisen bildwiedergabe - Google Patents

Verfahren und system zur kachelweisen bildwiedergabe

Info

Publication number
ATE336764T1
ATE336764T1 AT01932742T AT01932742T ATE336764T1 AT E336764 T1 ATE336764 T1 AT E336764T1 AT 01932742 T AT01932742 T AT 01932742T AT 01932742 T AT01932742 T AT 01932742T AT E336764 T1 ATE336764 T1 AT E336764T1
Authority
AT
Austria
Prior art keywords
tile
variable
image reproduction
primitives
wise image
Prior art date
Application number
AT01932742T
Other languages
English (en)
Inventor
Michael C Lewis
Glenn Nissen
Vadim Kochubievski
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE336764T1 publication Critical patent/ATE336764T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/10—Geometric effects
AT01932742T 2000-05-01 2001-04-30 Verfahren und system zur kachelweisen bildwiedergabe ATE336764T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20103400P 2000-05-01 2000-05-01
US09/782,467 US6741243B2 (en) 2000-05-01 2001-02-08 Method and system for reducing overflows in a computer graphics system

Publications (1)

Publication Number Publication Date
ATE336764T1 true ATE336764T1 (de) 2006-09-15

Family

ID=26896320

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01932742T ATE336764T1 (de) 2000-05-01 2001-04-30 Verfahren und system zur kachelweisen bildwiedergabe

Country Status (6)

Country Link
US (2) US6741243B2 (de)
EP (1) EP1295256B1 (de)
AT (1) ATE336764T1 (de)
AU (1) AU2001259246A1 (de)
DE (1) DE60122333T2 (de)
WO (1) WO2001084502A1 (de)

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US6738069B2 (en) * 2001-12-31 2004-05-18 Intel Corporation Efficient graphics state management for zone rendering
JP3747859B2 (ja) * 2002-02-06 2006-02-22 ソニー株式会社 画像処理装置およびその方法
US20040179007A1 (en) * 2003-03-14 2004-09-16 Bower K. Scott Method, node, and network for transmitting viewable and non-viewable data in a compositing system
WO2008004135A2 (en) * 2006-01-18 2008-01-10 Lucid Information Technology, Ltd. Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US20080079737A1 (en) * 2003-11-19 2008-04-03 Reuven Bakalash Multi-mode parallel graphics rendering and display system supporting real-time detection of mode control commands (MCCS) programmed within pre-profiled scenes of the graphics-based application
US8085273B2 (en) 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US7808499B2 (en) * 2003-11-19 2010-10-05 Lucid Information Technology, Ltd. PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router
US8497865B2 (en) * 2006-12-31 2013-07-30 Lucid Information Technology, Ltd. Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
US7961194B2 (en) * 2003-11-19 2011-06-14 Lucid Information Technology, Ltd. Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
WO2006117683A2 (en) * 2005-01-25 2006-11-09 Lucid Information Technology, Ltd. Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US20090027383A1 (en) 2003-11-19 2009-01-29 Lucid Information Technology, Ltd. Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition
US8223157B1 (en) * 2003-12-31 2012-07-17 Ziilabs Inc., Ltd. Stochastic super sampling or automatic accumulation buffering
US20090096798A1 (en) * 2005-01-25 2009-04-16 Reuven Bakalash Graphics Processing and Display System Employing Multiple Graphics Cores on a Silicon Chip of Monolithic Construction
ITMI20070038A1 (it) * 2007-01-12 2008-07-13 St Microelectronics Srl Dispositivo di renderizzazione per grafica a tre dimensioni con architettura di tipo sort-middle.
ITMI20082342A1 (it) * 2008-12-30 2010-06-30 St Microelectronics Srl Modulo di renderizzazione per grafica a due dimensioni, preferibilmente basato su primitive di tipo bordo attivo
KR102089471B1 (ko) 2012-11-30 2020-03-17 삼성전자주식회사 타일 기반 렌더링 방법 및 장치
US10169906B2 (en) 2013-03-29 2019-01-01 Advanced Micro Devices, Inc. Hybrid render with deferred primitive batch binning
US10957094B2 (en) 2013-03-29 2021-03-23 Advanced Micro Devices, Inc. Hybrid render with preferred primitive batch binning and sorting

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
US5594467A (en) * 1989-12-06 1997-01-14 Video Logic Ltd. Computer based display system allowing mixing and windowing of graphics and video
US5377320A (en) 1992-09-30 1994-12-27 Sun Microsystems, Inc. Method and apparatus for the rendering of trimmed nurb surfaces
US5621869A (en) * 1994-06-29 1997-04-15 Drews; Michael D. Multiple level computer graphics system with display level blending
US6005582A (en) 1995-08-04 1999-12-21 Microsoft Corporation Method and system for texture mapping images with anisotropic filtering
JP3742167B2 (ja) * 1996-12-18 2006-02-01 株式会社東芝 画像表示制御装置
US6219058B1 (en) * 1997-09-08 2001-04-17 Intel Corporation Bin-per-span based representation and communication of graphical data
US6191800B1 (en) * 1998-08-11 2001-02-20 International Business Machines Corporation Dynamic balancing of graphics workloads using a tiling strategy
US6288730B1 (en) 1998-08-20 2001-09-11 Apple Computer, Inc. Method and apparatus for generating texture
US6344852B1 (en) * 1999-03-17 2002-02-05 Nvidia Corporation Optimized system and method for binning of graphics data
US6396473B1 (en) * 1999-04-22 2002-05-28 Webtv Networks, Inc. Overlay graphics memory management method and apparatus
US6424345B1 (en) * 1999-10-14 2002-07-23 Ati International Srl Binsorter triangle insertion optimization
US6819321B1 (en) * 2000-03-31 2004-11-16 Intel Corporation Method and apparatus for processing 2D operations in a tiled graphics architecture

Also Published As

Publication number Publication date
US20040196283A1 (en) 2004-10-07
EP1295256A1 (de) 2003-03-26
DE60122333D1 (de) 2006-09-28
US20010055012A1 (en) 2001-12-27
DE60122333T2 (de) 2007-09-13
WO2001084502A1 (en) 2001-11-08
US6741243B2 (en) 2004-05-25
AU2001259246A1 (en) 2001-11-12
EP1295256B1 (de) 2006-08-16

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