ATE256886T1 - METHOD AND DEVICE FOR BRANCH CONTROL IN A PIPELINE PROCESSOR - Google Patents

METHOD AND DEVICE FOR BRANCH CONTROL IN A PIPELINE PROCESSOR

Info

Publication number
ATE256886T1
ATE256886T1 AT00928970T AT00928970T ATE256886T1 AT E256886 T1 ATE256886 T1 AT E256886T1 AT 00928970 T AT00928970 T AT 00928970T AT 00928970 T AT00928970 T AT 00928970T AT E256886 T1 ATE256886 T1 AT E256886T1
Authority
AT
Austria
Prior art keywords
instruction
flags
branch
jump
affect
Prior art date
Application number
AT00928970T
Other languages
German (de)
Inventor
James Robert Howar Hakewill
Jon Sanders
Original Assignee
Arc Internat U S Holdings Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/418,663 external-priority patent/US6862563B1/en
Priority claimed from US09/523,871 external-priority patent/US6560754B1/en
Application filed by Arc Internat U S Holdings Inc filed Critical Arc Internat U S Holdings Inc
Application granted granted Critical
Publication of ATE256886T1 publication Critical patent/ATE256886T1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines

Abstract

An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of permitting programmer control of jump instruction interlocks is disclosed. In one embodiment, a minimum of one cycle is required between an instruction that sets flags and a branch taken as a result of those flags; an interlock is used to detect a branch preceded by an instruction setting the flags to ensure that the instruction immediately preceding the branch can not affect the branch outcome. In a second embodiment, a jump instruction following a flag setting instruction whose flags may affect the outcome of the jump is stalled until all flags are set. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned interlocks is disclosed. Exemplary gate logic synthesized using the aforementioned methods, and a computer system capable of implementing these methods, are also described.
AT00928970T 1999-05-13 2000-05-12 METHOD AND DEVICE FOR BRANCH CONTROL IN A PIPELINE PROCESSOR ATE256886T1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13425399P 1999-05-13 1999-05-13
US09/418,663 US6862563B1 (en) 1998-10-14 1999-10-14 Method and apparatus for managing the configuration and functionality of a semiconductor design
US09/523,871 US6560754B1 (en) 1999-05-13 2000-03-13 Method and apparatus for jump control in a pipelined processor
PCT/US2000/013030 WO2000070444A2 (en) 1999-05-13 2000-05-12 Method and apparatus for jump control in a pipelined processor

Publications (1)

Publication Number Publication Date
ATE256886T1 true ATE256886T1 (en) 2004-01-15

Family

ID=27384544

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00928970T ATE256886T1 (en) 1999-05-13 2000-05-12 METHOD AND DEVICE FOR BRANCH CONTROL IN A PIPELINE PROCESSOR

Country Status (7)

Country Link
EP (1) EP1190303B1 (en)
CN (1) CN1167005C (en)
AT (1) ATE256886T1 (en)
AU (1) AU4712300A (en)
DE (1) DE60007312T2 (en)
TW (1) TW527563B (en)
WO (1) WO2000070444A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4204522B2 (en) * 2004-07-07 2009-01-07 株式会社東芝 Microprocessor
GB2563587B (en) 2017-06-16 2021-01-06 Imagination Tech Ltd Scheduling tasks
GB2563589B (en) * 2017-06-16 2019-06-12 Imagination Tech Ltd Scheduling tasks
CN111026442B (en) * 2019-12-17 2022-08-02 天津国芯科技有限公司 Method and device for eliminating program unconditional jump overhead in CPU

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0365188B1 (en) * 1988-10-18 1996-09-18 Hewlett-Packard Company Central processor condition code method and apparatus

Also Published As

Publication number Publication date
EP1190303B1 (en) 2003-12-17
DE60007312D1 (en) 2004-01-29
TW527563B (en) 2003-04-11
CN1357122A (en) 2002-07-03
WO2000070444A3 (en) 2001-08-09
CN1167005C (en) 2004-09-15
AU4712300A (en) 2000-12-05
DE60007312T2 (en) 2004-10-14
EP1190303A2 (en) 2002-03-27
WO2000070444A2 (en) 2000-11-23

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Legal Events

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