ATE214194T1 - SINGLE ELECTRON MEMORY CELL ARRANGEMENT - Google Patents

SINGLE ELECTRON MEMORY CELL ARRANGEMENT

Info

Publication number
ATE214194T1
ATE214194T1 AT97107314T AT97107314T ATE214194T1 AT E214194 T1 ATE214194 T1 AT E214194T1 AT 97107314 T AT97107314 T AT 97107314T AT 97107314 T AT97107314 T AT 97107314T AT E214194 T1 ATE214194 T1 AT E214194T1
Authority
AT
Austria
Prior art keywords
memory cell
cell arrangement
single electron
electron memory
electron transistor
Prior art date
Application number
AT97107314T
Other languages
German (de)
Inventor
Lothar Risch
Wolfgang Roesner
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of ATE214194T1 publication Critical patent/ATE214194T1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/08—Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/937—Single electron transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

Each memory cell of an array has a single-electron transistor and a single-electron memory element. The single-electron transistor is driven by a charge stored in the memory element. When a read voltage is applied, a current flows through the single-electron transistor which is dependent on the stored charge, but the stored charge in not changed. When a write voltage is applied, the magnitude of which is greater than the read voltage, then the stored charge is changed. The memory cells of the array are each connected between first lines and transverse second lines of a memory cell configuration.
AT97107314T 1996-05-31 1997-05-02 SINGLE ELECTRON MEMORY CELL ARRANGEMENT ATE214194T1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19621994A DE19621994C1 (en) 1996-05-31 1996-05-31 Single electron memory cell arrangement

Publications (1)

Publication Number Publication Date
ATE214194T1 true ATE214194T1 (en) 2002-03-15

Family

ID=7795864

Family Applications (1)

Application Number Title Priority Date Filing Date
AT97107314T ATE214194T1 (en) 1996-05-31 1997-05-02 SINGLE ELECTRON MEMORY CELL ARRANGEMENT

Country Status (7)

Country Link
US (1) US5844834A (en)
EP (1) EP0810609B1 (en)
JP (1) JP4057675B2 (en)
KR (1) KR100435924B1 (en)
AT (1) ATE214194T1 (en)
DE (2) DE19621994C1 (en)
TW (1) TW382707B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0881691B1 (en) 1997-05-30 2004-09-01 Matsushita Electric Industrial Co., Ltd. Quantum dot device
DE19820050C1 (en) * 1998-05-05 1999-03-25 Siemens Ag Circuit arrangement with single electron components in CMOS logic circuit application
KR100325689B1 (en) 1999-12-01 2002-02-25 오길록 Single - electron memory device using the electron - hole coupling
US6483125B1 (en) 2001-07-13 2002-11-19 North Carolina State University Single electron transistors in which the thickness of an insulating layer defines spacing between electrodes
US6653653B2 (en) 2001-07-13 2003-11-25 Quantum Logic Devices, Inc. Single-electron transistors and fabrication methods in which a projecting feature defines spacing between electrodes
US6673717B1 (en) 2002-06-26 2004-01-06 Quantum Logic Devices, Inc. Methods for fabricating nanopores for single-electron devices
US7135697B2 (en) * 2004-02-25 2006-11-14 Wisconsin Alumni Research Foundation Spin readout and initialization in semiconductor quantum dots
EP1748501B1 (en) * 2005-07-26 2007-10-17 Universität Duisburg-Essen Microelectronic component
US7602069B2 (en) * 2004-03-31 2009-10-13 Universität Duisburg-Essen Micro electronic component with electrically accessible metallic clusters
KR100673408B1 (en) * 2005-02-07 2007-01-24 최중범 Momory cell and memory device employing single electron transistor
US20090066853A1 (en) * 2007-09-10 2009-03-12 Sony Corporation Sony Electronics Inc. Remote control with recessed keypad
US20120235968A1 (en) * 2011-03-15 2012-09-20 Qualcomm Mems Technologies, Inc. Method and apparatus for line time reduction
US9558820B2 (en) 2013-10-29 2017-01-31 Hewlett Packard Enterprise Development Lp Resistive crosspoint memory array sensing
US11047877B2 (en) * 2017-09-28 2021-06-29 Quantum Silicon Inc. Initiating and monitoring the evolution of single electrons within atom-defined structures

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357460A (en) * 1991-05-28 1994-10-18 Sharp Kabushiki Kaisha Semiconductor memory device having two transistors and at least one ferroelectric film capacitor
DE4212220C3 (en) * 1992-04-09 2000-05-04 Guenter Schmid Use of an arrangement of cluster molecules as a microelectronic component

Also Published As

Publication number Publication date
KR100435924B1 (en) 2004-07-16
DE59706533D1 (en) 2002-04-11
TW382707B (en) 2000-02-21
US5844834A (en) 1998-12-01
EP0810609A3 (en) 1999-08-11
JP4057675B2 (en) 2008-03-05
KR970076815A (en) 1997-12-12
DE19621994C1 (en) 1997-06-12
EP0810609A2 (en) 1997-12-03
JPH1098160A (en) 1998-04-14
EP0810609B1 (en) 2002-03-06

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Legal Events

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