ATE100224T1 - PRIORITY TECHNIQUE FOR A SPLIT TRANSACTION BUS IN A MULTIPROCESSOR COMPUTER SYSTEM. - Google Patents

PRIORITY TECHNIQUE FOR A SPLIT TRANSACTION BUS IN A MULTIPROCESSOR COMPUTER SYSTEM.

Info

Publication number
ATE100224T1
ATE100224T1 AT87906623T AT87906623T ATE100224T1 AT E100224 T1 ATE100224 T1 AT E100224T1 AT 87906623 T AT87906623 T AT 87906623T AT 87906623 T AT87906623 T AT 87906623T AT E100224 T1 ATE100224 T1 AT E100224T1
Authority
AT
Austria
Prior art keywords
computer system
multiprocessor computer
split transaction
transaction bus
priority technique
Prior art date
Application number
AT87906623T
Other languages
German (de)
Inventor
Michael A Fischer
Original Assignee
Datapoint Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/909,773 external-priority patent/US4785394A/en
Application filed by Datapoint Corp filed Critical Datapoint Corp
Application granted granted Critical
Publication of ATE100224T1 publication Critical patent/ATE100224T1/en

Links

AT87906623T 1986-09-19 1987-09-18 PRIORITY TECHNIQUE FOR A SPLIT TRANSACTION BUS IN A MULTIPROCESSOR COMPUTER SYSTEM. ATE100224T1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US06/909,773 US4785394A (en) 1986-09-19 1986-09-19 Fair arbitration technique for a split transaction bus in a multiprocessor computer system
EP87906623A EP0329664B1 (en) 1986-09-19 1987-09-18 Arbitration technique for a split transaction bus in a multprocessor computer system
PCT/US1987/002391 WO1988002150A1 (en) 1986-09-19 1987-09-18 Arbitration technique for a split transaction bus in a multprocessor computer system

Publications (1)

Publication Number Publication Date
ATE100224T1 true ATE100224T1 (en) 1994-01-15

Family

ID=27231060

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87906623T ATE100224T1 (en) 1986-09-19 1987-09-18 PRIORITY TECHNIQUE FOR A SPLIT TRANSACTION BUS IN A MULTIPROCESSOR COMPUTER SYSTEM.

Country Status (1)

Country Link
AT (1) ATE100224T1 (en)

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties