ATA836473A - METHOD OF MANUFACTURING A MULTI-LAYER PCB - Google Patents

METHOD OF MANUFACTURING A MULTI-LAYER PCB

Info

Publication number
ATA836473A
ATA836473A AT836473A AT836473A ATA836473A AT A836473 A ATA836473 A AT A836473A AT 836473 A AT836473 A AT 836473A AT 836473 A AT836473 A AT 836473A AT A836473 A ATA836473 A AT A836473A
Authority
AT
Austria
Prior art keywords
manufacturing
layer pcb
pcb
layer
Prior art date
Application number
AT836473A
Other languages
German (de)
Other versions
AT334452B (en
Inventor
Georgy Avenirovich Kitaev
Vadim Alexandrovich Ploskikh
Viktor Alexeevich Minkov
Viktor Georgievich Kurbakov
Evangelina Mikhail Chernysheva
Tatyana Nikolaevn Zlatkovskaya
Viktor Timofeevich Brunov
Original Assignee
Uralsky Politekhn Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Uralsky Politekhn Inst filed Critical Uralsky Politekhn Inst
Priority to AT836473A priority Critical patent/AT334452B/en
Application granted granted Critical
Publication of AT334452B publication Critical patent/AT334452B/en
Publication of ATA836473A publication Critical patent/ATA836473A/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0344—Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
AT836473A 1973-09-28 1973-09-28 METHOD OF MANUFACTURING A MULTI-LAYER PCB AT334452B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT836473A AT334452B (en) 1973-09-28 1973-09-28 METHOD OF MANUFACTURING A MULTI-LAYER PCB

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AT836473A AT334452B (en) 1973-09-28 1973-09-28 METHOD OF MANUFACTURING A MULTI-LAYER PCB

Publications (2)

Publication Number Publication Date
AT334452B AT334452B (en) 1976-01-25
ATA836473A true ATA836473A (en) 1976-05-15

Family

ID=3604813

Family Applications (1)

Application Number Title Priority Date Filing Date
AT836473A AT334452B (en) 1973-09-28 1973-09-28 METHOD OF MANUFACTURING A MULTI-LAYER PCB

Country Status (1)

Country Link
AT (1) AT334452B (en)

Also Published As

Publication number Publication date
AT334452B (en) 1976-01-25

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Legal Events

Date Code Title Description
ELJ Ceased due to non-payment of the annual fee