AT404524B - Process for producing self-aligned, lateral and vertical semiconductor components - Google Patents

Abstract

In a process for producing self-aligned, lateral and vertical semiconductor components, especially for the production of LSI and VLSI circuits, the objective is to achieve the self-positioning of all the component fields in relation to one another, coupled with a high packing density, in a multi-stage structuring and construction operation, and to permit the implementation of weakly doped and self-positioned source and drain areas, so that highly integrated and very highly integrated circuits can be produced with a high yield. <IMAGE>

Description

AT 404 524 B.

The invention relates to a method for producing self-aligned lateral and vertical semiconductor components with a plurality of successive silicon and insulator layers, in particular for the production of LSI and VLSI circuits.

Methods for manufacturing integrated circuits are known. N. MATSUKAWA u. a .: &quot; Selective Polysilicon Oxidation Technology for VLSI Isolation &quot;, in IEEE Transactions on Electron Devices, ED-29, No 4, April 1982, pp. 561-567, presented a method which is suitable for the production of integrated circuits .

In this method, the field oxide (thick oxide outside the active areas) is generated from an undoped polycrystalline silicon layer (polysilicon layer). The silicon nitride layer (Si nitride layer) is located on the polysilicon layer and does not come into contact with the monocrystalline silicon substrate (monosilicon substrate). Mechanical stresses are absorbed by the polysilicon. The so-called "bird beak" has only a limited development. The process is briefly outlined as follows:

P-type silicon (p-silicon) with a specific resistance pp = 2 Qcm is used as the starting material. A 50 nm thick adhesive oxide layer is produced. A 400 nm thick undoped polysilicon layer and a 300 nm thick silicon nitride layer (Si nitride layer) are deposited thereon in succession. The Si nitride layer is structured using a lacquer layer. The area of the later active areas is therefore protected by the Si nitride layer. A boron implantation follows with N = 1 · 1013 cm &quot; 2 at E = 160keV.

After the varnish has been removed, oxidation takes place at v = 1000 * C. A field oxide of dw = 800 nm with a length of the "bird's beak" is formed. of 0.15 µm.

After removal of the Si nitride layer in hot phosphoric acid, the undoped polysilicon layer is removed up to the adhesive oxide layer with the aid of reactive ion etching (RIE). It is then oxidized again in order to convert the residues of polysilicon into oxide. An oxide overetch then removes the adhesive oxide layer from the active areas. The length of the &quot; bird's beak &quot; also reduced. The gate oxidation follows with dox = 50 nm. The further process sequence then takes place in a conventional manner.

The disadvantage of this method is that no self-aligned source and drain regions can be implemented, that the parasitic capacitances cannot be reduced as a result, and that the gate oxide must be generated before the source and drain regions are implemented. Because the gate oxide must be generated very early in the technological process, there is a risk that the gate electrode will become charged and destroy the gate oxide. Special protective measures are required (see e.g. EP 110656).

According to EP 43944 by C.G. JAMBOTKAR; &quot; Self-Aligned Field-Effect Transistor Integrated Circuit Structure and Method for Making &quot; 13 to 20, self-positioning of the source and drain regions is achieved with the aid of a second field oxide. First, the field oxide and the p-channel stopper areas are generated. The field oxide is protected by a thin layer of Si nitride. In the area of the active areas, an oxide layer is structured in such a way that the monosilicon substrate is exposed on the left and right. With this structuring, incorrect positioning can easily occur. The monosilicon substrate is then lowered and a second field oxide layer is produced. This second field oxide is only realized at the bottom of the depression, so that the side walls are free of oxide. An n + -conducting polysilicon layer is then deposited and planarized until the oxide layer is exposed in the active region. This is followed by nitrogen implantation and tempering at 1000 to 1200 * C. This creates a thin protective layer of Si nitride on the n + -type polysilicon layer and also the n + -type source and drain regions in the monosilicon substrate. The oxide layer in the area of the active areas is then removed. A thick silicon oxide layer is then deposited and only removed from the horizontal surfaces using RIE. The channel implantation follows. The remnants of the thick silicon oxide layer are removed, and again a thinner silicon oxide layer is deposited and only removed from the horizontal surfaces by means of RIE. The side walls of the n + -conducting polysilicon layer are thus passivated. The active transistor channel is now exposed and can be oxidized. The gate oxide is generated. Another ^ -conducting polysilicon layer is then deposited and structured again.

According to this method, self-positioning of the source and drain regions is achieved, but a second field oxide is required for this, which requires additional space and thus reduces the packing density. Furthermore, no weakly doped source and drain regions can be produced, so that LDD transistors (lightly-doped-drain transistors) are not available. However, in the case of short-channel transistors in particular, these n-conducting regions are necessary in order to reduce the threshold voltage drift (temporal change in the threshold voltage). 2nd

AT 404 524 B.

According to EP 129045 by W. Kraft: "Method for producing an integrated insulating layer field-effect transistor with contacts self-aligned to the gate electrode", a method is also presented which also requires two field oxides for the production of integrated circuits. A silicon oxide (Si02) and a silicon nitride (Si3N4) layer are produced and structured on a substrate. The areas that are to receive the thin field oxide are then exposed. Before the oxidation, however, impurities causing n-conduction are first implanted. After the oxidation, the thin field oxide with underlying n-type regions is present. Another Si nitride layer is now deposited and structured. This layer covers the areas with the thin field oxide and the gate area (see FIG. 4 of EP 129045). A boron implantation is then carried out. Then it is oxidized. The thick field oxide and the p-type channel stopper areas are formed. The n-type regions expand further during this temperature treatment. The silicon nitride layer and the thin silicon oxide layer above the channel region are then removed. The gate oxide is then generated. The implantation follows to set the threshold voltage through the gate oxide. Highly doped polysilicon is then deposited and structured. With this structuring, however, it must be ensured that the polysilicon always covers the gate oxide. Then contact windows are created in the thin field oxide so that the n-type source and drain regions can then be contacted.

A disadvantage of this method is that the polysilicon gate must be precisely aligned with respect to the contact window. The contact windows must be in the area of the thin field oxide, otherwise there is no contact with the underlying n-type region, i. H. the length of the thin field oxide areas depends on the positioning accuracy. Small source and drain path areas cannot be realized with this method. As a result, there are still large pn junction areas of the source and drain regions to the substrate, which cause large reverse currents, large capacities and a reduction in yield.

In DE-OS 3419080 by W. T. Lynch u. a .: &quot; Method of making a field effect transistor &quot; Another method with self-alignment of the contacts to the transistor areas is presented. First, field oxide and gate oxide are generated. The transition from field oxide to gate oxide must be relatively abrupt. Then various polysilicon, metal or silicide and insulating layers are deposited. These layers are then removed in the area of the relatively steep steps, so that this layer structure is retained in the middle in the active transistor area. This is then protected by an Si02 layer. By removal using RIE, this Si02 layer is only retained at the vertical steps. An n + -doped polysilicon layer is then deposited and structured. During the deposition, the exposed palladium (Pd) reacts with the polysilicon to form a silicide, which is then selectively removed, the polysilicon being retained in the later source and drain region. The n + -conducting regions for source and drain are then created by diffusing out impurities from the n + -poly silicon. The entire structure is then protected with a phosphorus silicate glass layer (PSG layer), which is then structured for the aluminum (Al) contact. A disadvantage of this method is that a very precise lacquer structure is required to protect the gate electrode which is led out laterally on the field oxide, and that the gate oxide must be generated before the high-energy implantations, as in the known methods, with charges subsequently occurring can.

The object of the invention is to eliminate the disadvantages of the known methods, to achieve self-alignment of all component areas with one another, coupled with a high packing density and to enable the realization of weakly doped and self-aligned source and drain areas, so that highly and highly integrated circuits with one high yield can be produced.

According to the invention the object is achieved by a method for producing self-aligned lateral and vertical semiconductor components, in which a semiconductor substrate is used, that a protective layer is formed over it, that a thick polysilicon layer and a thick silicon nitride layer are successively deposited thereon, that the thick silicon nitride layer with the help is structured in a photoresist layer, that the thick polysilicon layer is only removed again from the exposed areas to a certain depth by means of reactive ion etching (RIE), a polysilicon mound being produced, a boron implantation being carried out, a thin silicon nitride layer being deposited, that this thin silicon nitride layer is only etched off from the horizontal surfaces by means of RIE, in such a way that a thick field oxide and underneath channel stopper regions are produced, which is patterned again, the thin silicon nitride sc hicht only removed at the source and drain connection and the thick silicon nitride layer in the exposed area are thinned so that the iso-silicon hill is removed on the exposed sides by an isotropic etching process, an undercut ("u") being produced that the remains of the two silicon nitride layers removed that by means of RIE the polysilicon mound is only removed from the horizontal surfaces by a certain amount, whereby a 3 ΑΤ 404 524 Β rectangular polysilicon mound is generated, that the exposed parts of the protective layer are removed by overetching, that a highly doped polysilicon layer is deposited and is patterned such that an insulator layer is deposited, that a photoresist layer is deposited and planarized, whereby only the insulator layer on the polysilicon hill is exposed, that the exposed insulator layer is etched down to the highly doped polysilicon layer that the exposed, highly doped polysilicon layer is removed down to the semiconductor substrate, the polysilicon hill also being etched away by a certain amount so that an impurity implantation is carried out to produce weakly doped source and drain regions, thin thermal oxide layers being produced on the free silicon areas and the doped regions, that a further insulator layer is deposited, that this insulator layer is only removed from the horizontal surfaces again by means of RIE, that the remnants of the polysilicon mound and the protective layer are completely removed, that a gate oxide layer is generated, that implantations for ion implantation are carried out in a known manner Setting the threshold voltages of the field-effect transistors are carried out such that a further highly doped polysilicon layer is deposited and planarized, that contact windows are generated in the insulator layer and that further interconnects d Insulating layers are deposited and structured. In this way, a self-alignment of all component areas with one another, coupled with a high packing density, is achieved, and the realization of weakly doped and self-aligned source and drain areas is made possible.

An advantageous variant achieves the object of the invention in that after the creation of a polysilicon hill as rectangular as possible, the impurity impingement is carried out, then the oxide layer and the weakly doped regions are produced, and by means of RIE the oxide layer is only removed from the horizontal surfaces in that the heavily doped The polysilicon layer is deposited and structured, the further insulator layer is deposited, the photoresist layer is deposited and planarized, the exposed insulator layer is removed from the polysilicon hill, and then the exposed polysilicon layer is removed by a certain amount, so that the insulator layer is deposited, the Wells are filled in, that the further insulator layer is applied again, that the rest of the polysilicon hill is then etched away, that the exposed protective layer is removed, that the gate oxide is produced It is also the case that the gate oxide performs the high-level implantations for setting the threshold voltage values, that the further highly doped polysilicon layer is deposited and planarized, that contact windows are generated in the insulator layer and that further interconnect and insulating layers are deposited and structured. The advantages of this design are discussed in detail in the following description of the figures.

In order to be able to produce bipolar transistors together with the MOS transistors, a further preferred variant is such that instead of the n + -doped polysilicon layer, an undoped polysilicon layer is deposited, that this undoped polysilicon layer in the emitter base region of a bipolar transistor is p-conducting and is doped n-type in the collector region that after removal of the polysilicon hill and the protective layer in the emitter base region of the bipolar transistor, a boron implantation is carried out with subsequent annealing to produce the p-type base region, that the further highly doped polysilicon layer is then deposited and that the subsequent one Annealing treatment the n-ieit areas for emitter and collector are generated. The advantages which can be achieved in this way are also illustrated with the aid of the exemplary embodiment shown in the drawing.

The invention will be explained below with reference to exemplary embodiments shown in the drawing. 1 to 10 cross sections of a MOS transistor each on the left in the source-drain direction, on the right transversely to the source-drain direction; 11 to 17 a further variant of the method and FIG. 18 a cross section of a bipolar transistor.

1, a p-type semiconductor substrate 1 is assumed. After the S1O2 protective layer 2 has been produced, a thick polysilicon layer 3 is deposited. This layer is undoped and will typically be 1.6 to 2.0 µm thick. A thick silicon nitride layer 4 is then deposited. The thickness of this layer is approximately 200 nm. The layer structure is coated with photoresist 5 and structured (1st mask). With the help of reactive ion etching (RIE), the thick Si nitride layer 4 and the thick polysilicon layer 3 are then removed, so that a polysilicon hill 6 is formed. However, a part of the thick polysilicon layer 3 of approximately 300 to 400 nm is still preserved in the removal area. The boron implantation 7 is then carried out. 1 shows the cross sections after this process step

The residues of the photoresist layer 5 are then removed. This is followed by the deposition of a thinner Si nitride layer 8. This layer is only removed from the horizontal surfaces by means of RIE, so that the polysilicon hill 6 is now protected on all sides with a Si nitride cap. Fig. 2 shows the cross sections after this substep. 4th

AT 404 524 B.

Then it is oxidized. This produces the thick field oxide 9 and the p-type channel stopper regions 10. The oxidation process continues until the thinned polysilicon layer 3 of approximately 300 to 400 nm is completely converted into silicon oxide. The oxide infiltration of the Si nitride layer 8 ("birds beak"; "bird beak") will be approximately 150 to 200 nm. Fig. 3 shows the corresponding cross sections.

It is structured again. With the help of a second mask, the thin Si nitride layer 8 is etched off in the source and drain region and at the same time the thick Si nitride layer 4 is thinned by the amount of the thin Si nitride layer 8. The structuring must take place on the polysilicon hill 6, because the Si nitride layer 8 must be preserved on the sides. The positioning accuracy is indicated on the right in Fig. 4 with Ab. The transistor will have a slightly longer channel length in this area. However, since the transistor width is b »Ab, Ab will only have a slight influence on the transistor property. 4 shows both cross sections after this method step.

The polysilicon hill 6 is then removed on the two exposed sides by an isotropic etching process. This creates the undercut “u”, the undercut not taking place evenly due to the hill, which is still partially protected. 5 again shows the corresponding cross sections.

The residues of the Si nitride layers 4 and 8 are subsequently removed. The polysilicon hill 6 is then removed by means of RIE. It is etched until the protective layer 2 is exposed in the undercut area. At the end of the etching process, the polysilicon hill 6 should be as rectangular as possible. The exposed parts of the protective layer 2 are then etched off. Fig. 6 shows both cross sections.

A highly doped n-type polysilicon layer 11 is now deposited and structured using the third mask. The position of this polysilicon layer 11 in the source-drain direction can be seen on the right in FIG. 7. This polysilicon layer 11 must run on the polysilicon hill 6. Ab may not exceed zero.

An insulator layer 12 follows. Then a photoresist layer 13 is deposited and planarized until the polysilicon mounds 6 covered with the layers 11 and 12 come to light (FIG. 7).

The exposed insulator layer 12 is then removed from the polysilicon hill 6. The exposed highly doped polysilicon layer 11 is then removed. It is etched until the highly doped polysilicon layer 11 is removed as far as the semiconductor substrate 1. The undoped polysilicon hill 6 is also partially removed if no protective measures are provided. If with an etch rate ratio of 2: 1 for n + poly: undot. Polysilicon is calculated, so about half of the undoped polysilicon hill 6 remains. This thickness is sufficient as protection for the following implantation. The implantation 22 is carried out. Phosphorus or arsenic are implanted for the later n ~ -containing regions of the FET transistor. The active transistor region is protected by the rest of the polysilicon hill 6 (FIG. 8).

An annealing follows, whereby thin oxide layers are formed on all free silicon surfaces. Tempering and implantation can also be reversed in order. During this tempering, the n-type impurities diffuse out of the highly doped polysilicon layer 11 and produce the n-type region 14. At the same time, the n-type region 15 is formed. Due to the lower surface concentration of the n -conducting region 15, a smaller depth of penetration occurs here. A further insulator layer 16 (e.g. SiO 2 layer) is subsequently deposited and only removed from the horizontal surfaces by means of RIE. The remains of the polysilicon hill 6 are thus exposed again (FIG. 9). The rest of the polysilicon hill 6 is then removed using silicon etching. The remainder of the protective layer 2 is removed by extensive oxide overetching and the lateral &quot; Vogelschnä-bel &quot; reduced. A gate oxide 17 is generated. This is followed by the implantations for setting the threshold voltages of the transistors. With the help of a paint mask, the depletion transistors are first protected (4th mask, 4th paint structure). The threshold voltage of the enhancement transistors is set by a boron implantation. The enhancement transistors are then protected (5th mask, 5th paint structure). The threshold voltage of the depletion transistors is set by a phosphor implantation. A further highly doped polysilicon layer 18 is then deposited and planarized. With this planarization, the gates are self-positioned. Longitudinal and transverse to the source-drain direction there are no significant overlaps in the area of thin oxide layers. 10 shows the cross sections after this method step.

In order to complete the layer structure, contact windows are produced in the insulator layer 12 (6th mask, 6th lacquer structure). Then further interconnect and insulating layers are deposited and structured. 5

AT 404 524 B.

This process sequence has resulted in transistor structures which have small n + / n - conductive source-drain regions in terms of area. The parasitic capacitances to the substrate thus also have very small values. The n “-conducting regions can significantly improve the electrical properties of the transistors (low threshold voltage drift, smaller substrate and gate currents). The length of the n-conducting regions can be set precisely and reproducibly. The fact that the gate oxide is generated almost at the end of the technological process means that only a low temperature and no radiation exposure of the gate oxide occurs. Very thin gate oxide layers can be reliably implemented.

The following procedure is used to further reduce the area of the railway area:

After realization of the polysilicon hill 6 according to FIG. 6, the phosphorus or arsenic implantation 22 is carried out (FIG. 11). It is then oxidized. This creates an oxide layer 20 and the n-doped regions 15 (FIG. 12). Thereafter, the oxide layer 20 is only removed from the horizontal surfaces by means of RIE and remains on the vertical surfaces.

The field oxide layer 9 is also removed by the amount of the oxide layer 20 (FIG. 13). The highly doped polysilicon layer 11 is then deposited. This is then structured. The insulator layer 12 is subsequently deposited. Thereafter, the photoresist layer 13 is deposited and planarized until the insulator layer 12 appears on the polysilicon hill 6 (Rg. 14). Polysilicon or similar materials can also be used instead of the photoresist layer 13. The planarization can also be implemented with the aid of a multilayer flare structure and a dummy mask.

The exposed insulator layer 12 is then removed from the polysilicon hill 6. The exposed polysilicon layer 11 is then removed. It is then etched until approximately half of the highly doped polysilicon layer 11 has been removed from the hill wall. The removal is not critical. Larger tolerances can be allowed (Fig. 15). This is followed by the deposition of the further insulator layer 16. This further insulator layer 16 is used to fill up the depressions between the insulator layer 12 and the oxide layer 20. Instead of the further insulator layer 16, a thin undoped polysilicon layer can also be deposited and then oxidized (Rg. 16).

The further insulator layer 16 is subsequently removed by an isotropic (i.e. uniform in all directions) etching process. The depressions remain filled. The rest of the polysilicon hill 6 is then etched off. The exposed protective layer 2 is then removed. The free insulator layers are diluted accordingly. The gate oxidation follows. This creates the gate oxide 17. The n-type regions 15 expand a little further and the insulator layers are compressed. The implantations for setting the threshold voltage values are then carried out by the gate oxide 17. The further highly doped polysilicon layer 18 is then deposited and planarized (FIG. 17). The insulator layer 12 is then structured. The contact windows to the polysilicon layer 11 are realized. In some variants, these can also be implemented immediately after the gate oxidation. This has the advantage that the contact windows are also filled with highly doped polysilicon in the further process. Steps at the contact window then no longer occur.

To complete the layer structure, further interconnect and insulating layers are then deposited and structured. With this method variant, very small, lightly doped railway areas can be realized. The out-diffusion from the highly doped polysilicon layer is small, since high-temperature treatment is only carried out by the gate oxidation.

If additional bipolar transistors are to be implemented in addition to the MOS transistors, the following process variant should be selected: The process sequence described until the polysilicon bump 6 is generated is retained (FIG. 6). In place of the n + -doped polysilicon layer 11, an undoped polysilicon layer is deposited. This undoped polysilicon layer is doped p-type in the emitter base region of the bipolar transistor and n-type in the collector region. The same procedure is followed for the MOS transistors. The n-channel MOS transistor is n-conducting in its area, the p-channel MOS transistor, on the other hand, is p-conducting. This means that the p-channel areas must first be protected, i. H. the emitter base region of the bipolar transistor and the p-channel MOS transistor are covered with a lacquer or oxide layer. The exposed parts of the undoped polysilicon layer are exposed to a phosphorus or arsenic implant. These areas are then protected and the remaining areas are subjected to a boron implantation. Then proceed as shown in marg. 7, 8 and 9. After removing the polysilicon hill 6, the protective layer 2 is initially retained. A photoresist layer is deposited, which is patterned so that the emitter base region of the bipolar transistor is exposed. This is followed by a boron implantation. With the aid of this boron implantation and a subsequent tempering, the p-type base region 21 of the bipolar transistor is generated (FIG. 18). The photoresist layer and the remnants of the protective layer 2 are then removed. Now the gate oxide layer 17 6

Claims (3)

AT 404 524 B. This arises on all exposed silicon areas of the semiconductor substrate 1, i. H. both in the MOS transistors and in the bipolar transistors. The implantation is then carried out to set the threshold voltage values for the MOS transistors. This happens on a large scale. The implanted impurities hardly influence the bipolar transistor, so that special protection is not necessary. The thin gate oxide layer in the region of the bipolar transistors is then removed. Here the MOS transistors must now be protected by means of a photoresist layer. After removing the photoresist layer, the highly doped polysilicon layer 18 is then deposited and planarized. In the subsequent heat treatment, impurities diffuse out of the n + -doped polysilicon layer 18 and produce the n-type regions 19. Finally, contact windows are etched into the insulator layer 12 again and further interconnect and insulating layers are deposited and structured. 18 shows a cross section of a completed bipolar transistor. 1. Process for the production of self-aligned lateral and vertical semiconductor components with a plurality of successive silicon and insulator layers, characterized in that a semiconductor substrate (1) is used, that a protective layer (2) is produced thereon, that a thick polysilicon layer (3 ) and a thick silicon nitride layer (4) are deposited, that the thick silicon nitride layer (4) is structured with the aid of a photoresist layer (5), that the thick polysilicon layer (3) by means of reactive ion etching (RIE) only from the exposed areas to a certain one Depth is removed again, a polysilicon mound (6) being produced, a boron implantation (7) being carried out (FIG. 1), a thin silicon nitride layer (8) being deposited, that this thin silicon nitride layer (8) using RIE only from the horizontal surfaces is etched away that a thick field oxide (9) and there down channel stopper areas (10) are generated (FIG. 3), which is structured again, the thin silicon nitride layer (8) being removed only at the source and drain connection and the thick silicon nitride layer (4) being thinned in the exposed area (FIG. 4), that the polysilicon bump (6) is removed on the exposed sides by an isotropic etching process, an undercut fu () being produced (FIG. 5), that the residues of the silicon nitride layers (4, 8) are removed, that the polysilicon bump ( 6) is only removed from the horizontal surfaces by a certain amount, whereby a polysilicon hill (6) which is as rectangular as possible is produced, so that the exposed parts of the protective layer (2) are removed by overetching (FIG. 6), that a highly doped polysilicon layer ( 11) is deposited and structured, that an insulator layer (12) is deposited, that a photoresist layer (13) is deposited and planarized (FIG. 7), whereby only the insulator layer (12) on the polysilicon hill (6) is exposed, that the exposed insulator layer (12) is etched off to the highly doped polysilicon layer (11), that the exposed highly doped polysilicon layer (11) is removed down to the semiconductor substrate (1), whereby the polysilicon hill (6) is also etched away by a certain amount so that an impurity implantation (22) is carried out in order to produce weakly doped source and drain regions (FIG. 8), thin thermal oxide layers being produced on the free silicon surfaces and the doped regions (14, 15), that a further insulator layer (16) is deposited, that this insulator layer (16) is only removed from the horizontal surfaces again by means of RIE ( Fig. 9) that the remnants of the polysilicon hill (6) and the protective layer (2) are completely removed, that a gate oxide layer (17) is produced, that ion implantations are carried out in a manner known per se to adjust the threshold voltages of the field-effect transistors be that another highly doped polysilicon layer (18) is deposited and planarized (Fig.10), that contact windows are generated in the insulator layer (12) and that further interconnect and insulating layers are deposited and structured. 2. The method according to claim 1, characterized in that after the generation of a rectangular polysilicon hill (6) the impurity implantation (22) is carried out (Fig.11) that the oxide layer (20) and the lightly doped regions (15) are then generated (Fig.12) that by means of RIE the oxide layer (20) is only removed from the horizontal surfaces (Fig.13), that the highly doped polysilicon layer (11) is deposited and structured, that the insulator layer (12) is deposited, that the Photoresist layer (13) is deposited and planarized, that the exposed insulator layer (12) is removed from the polysilicon hill (6) (FIG. 14), that the exposed polysilicon layer (11) is then removed by a certain amount (FIG. 15) that the further insulator layer (16) is deposited, the depressions being filled (FIG. 16), the further insulator layer (16) being applied again, and then the rest of the polysi silicon hill (6) 7 AT 404 524 B is etched away, that the exposed protective layer (2) is removed, that the gate oxide (17) is generated, that the ion implantations for setting the threshold voltage values are carried out by the gate oxide (17) the further highly doped polysilicon layer (18) is deposited and planarized (FIG. 17), that contact windows are produced in the insulator layer (12) and that further interconnect and insulating layers are deposited and structured. 3. The method according to claims 1 and 2, characterized in that in place of the n + -doped polysilicon layer (11) an undoped polysilicon layer is deposited, that this undoped polysilicon layer in the emitter base region of a bipolar transistor doped p-type and in the collector region n-type is that after removal of the polysilicon hill (6) and the protective layer (2) in the emitter base region of the bipolar transistor, a boron implantation is carried out with subsequent annealing to produce the p-type base region (21), and then the further highly doped polysilicon layer (18) is deposited and that the n-type regions (19) for the emitter and collector are produced in the subsequent annealing treatment (FIG. 18). Add 10 sheets of drawings 8