AT393427B - DEVICE FOR TRANSMITTING DATA - Google Patents

Description

AT 393 427 B

The invention relates to a device for transmitting data between a data terminal device and a remote station connected to the common transmission network, for example a counter station, with a modem that converts the signals arriving from the transmission network into a format suitable for processing in the data terminal device and that from the data terminal device converts incoming signals into a format suitable for transmission over the transmission network, and with a control unit which switches from transmission operation to control operation when receiving predetermined characters.

Nowadays in interface devices that are between one or more data terminal devices, such as. B. computers, data terminals, etc., and the telephone network are arranged, primarily modems used. The main purpose of a modem is to limit the digital data flow from the actual data terminal itself in the form of voltage levels in analog signals that are suitable for the analog telephone network, convert, and vice versa.

The limits of the telephone network have led to the development of a large number of modulation methods and the use of different data transmission speeds (baud rates) .According to the recommendation of CCTTT (Comitd Consultatif International Telegraphique et Telephonique), a number of different modulation methods and data speeds (baud rates) have been standardized Modems that meet the standards mentioned can establish a connection via the network.

Communication between the data terminal equipment (DEE) and the modem normally takes place via the interface (V.24), the multipole contact device connected to the unit transmitting serial data on one channel (103) and receiving serial data on another channel (104) Contact connections are designed in such a way that they inform the modem and data device in binary form about the various activities taking place. The control of the data terminal device is carried out according to a specific data program that must be read into the system before data can be transmitted.

Modem technology has led to the development of ever more sophisticated modulation and signal processing methods for better transmission over the telephone network, as well as the implementation of several functions to make it easier to set up and clear down telephone connections, for example the interface device (V.25) (according to the CdTT standard) that accepts a call - and automatic answering device.

It is known that the data channels (103) and (104) in the interface not only transmit information from one data terminal (DEE) to another, but also information between the data terminal and its modem for measurement purposes (interface (V.24)) and for other instructions (interface (V.25 to)) can transmit.

Automatic call control is described in U.S. Patents 4,125,872 and 4,387,440. The last-mentioned patent also discloses that all control commands are sent from the data terminal device to the modem via the data line to the modem and that every character sent from the data terminal device to the modem during a data transmission is checked via a shift register as long as the modem is transmitting data is switched. A certain data sequence is stored in the shift register If a character in the transmitted character sequence corresponds to a character stored in the shift register, the data transmission is interrupted and the modem is switched to control mode as soon as a comparison has shown a match between the received character and the character stored in the shift register Comparison can lead to errors if, for example, one of the incoming characters mistakenly matches the character stored in the shift register, in which case the modem switches to control mode even without a command.This can particularly occur if an outgoing data flow is distorted before transmission, in which case the data characters can take any shape as a result of this distortion. It is of course also possible that, for example, a received signal, which actually represents a signal stored in the shift register, is temporarily not recognized as such as a result of interferences, so that the modem remains switched to data transfer and thus does not react to the controller, which ultimately results in a block Of the whole system.

The object of the invention is to largely reduce the risks described above.

This object is achieved according to the invention in that the control unit contains a pause detection circuit for detecting pauses in the data stream coming from the data terminal device (DEE) and in that the control unit determines, upon detection of such a pause, whether a predetermined code word is present in a certain area and / or after the pause is contained in the data stream and, after detection of such a code word, the device switches from operating mode of data transmission to an operating mode in which control commands are carried out.

The present invention is based on the fact that a transmitted command to switch to control mode is naturally followed by a pause. There are various reasons for pauses in the transmission of a message. It is therefore essential to distinguish one break from another. Since the transmission speed over a line does not always match the operating speed of the data terminal device, modern modems contain a buffer memory in which received data are temporarily stored for transmission purposes. The buffer memory thus contains the data words last received and, according to the present invention, serves to check whether one of the data words last received is a switching command if a pause is longer than a predetermined time period. -2-

AT 393 427 B

A pause in the transmission process often occurs immediately before the transmission of a data word, which means a command to switch to control mode. This possibility can be used to further expand a system with a pause before the transmission of a switching code in such a way that the device according to the present invention also Checks incoming data words after a break if the data words received immediately before the break do not contain a valid switching code. This ensures that a data word that corresponds to a switching code arrives safely, even if it was distorted during transmission. When switching codes are transmitted to the modem, the data terminal device can also send two completely identical switching codes with a corresponding pause in between. It is very likely that at least one of the words will be transmitted correctly and no data wad will be mistaken for a switching code.

The system is designed so that one or more data words are checked in the vicinity of a pause and the word or words are compared with one or more switching codes. If the information read from a data word before and / or after a pause corresponds to a switching code, the subsequent data information is read as a message to the modem and is therefore not transmitted over the network. The command to the modem can be a call command, for example, which means that the modem clears the existing connection and dials a new connection or the like.

The invention is explained in more detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram of an embodiment of the device according to the invention, and FIGS. 2 and 3 schematically illustrate the mode of operation of the ring buffer memory according to FIG. 1.

In the case of asynchronous data transmission, data words are transmitted which are flanked by a start and a stop bit (and possibly also a parity bit). The transfer of a character can take place at any time. If no character is transmitted, the line is idle.

In the case of synchronous data transmission, transmission takes place over the line during the entire communication period, the data terminals involved being synchronized when the connection is established. The transmission of a character at a certain point in time is always initiated by synchronization characters. In the event of a temporary data pause, a character is usually sent in the header of the data block that " clear frame " means

Fig. 1 shows an embodiment of a modem in which the invention is applied. The data terminal device (DEE) is connected to the modem via interface (I). The interface (1) can contain a serial channel for incoming data and a serial channel for outgoing data with adapter circuits for voltage levels or the like. This eliminates the need for conventional multipole contact devices with multiple control channels to control the actual modem. Instead, the modem has a control unit (2), which can serve as a temporary storage »for the temporary storage of both incoming and outgoing data and which decides whether the transmitted data has a transmission character and for the transmission of information between the data terminal equipment of one station and the one above Data terminal equipment connected to the telephone network are intended in the front-door station or have the character of a control command and are used to control the modem or the actual transmission. The control unit (2) is described in more detail below.

The actual modulator / demodulator unit (3) is connected to the control unit (2). Output data to be transmitted to the front-door station are converted into analog data form in unit (3), which is suitable for transmission over the telephone network. This follows, for example, by frequency modulation with a frequency shift between the carrier frequencies of 1080 Hz and 1750 Hz, the higher frequency representing “0” and the lower frequency T. Incoming frequency-modulated analog signals are demodulated in the unit (3) and thus converted back into digital data signals. The unit (3) can be any conventional and commercially available single chip modem circuit, for example an AM 7910, XR 14412 VP, or the like. The unit (3) must be functionally controlled. The control unit (2) therefore has a number of control lines which are connected to the control connections of the unit (3) and thus enable control of the unit in acknowledgment mode. The control of and the control functions in modulator / demodulator units of the same type as unit (3) belong to the known prior art and are not described in detail since they are not part of the present invention.

The unit (3) is in turn connected to the telephone network (TN) via an interface (4). This interface is of a known type and contains not only call detectors for determining whether the station has been called by an outside station and signal transfer converters, but also a circuit for transmitting number code signals on the line when an outside station has been dialed automatically by the data terminal equipment. The number code is sent from the control unit (2) to the interface (4). The call signal from the call detector is applied to an input of the control unit (2)

The device according to the present invention can also be used to connect a data terminal device to an outdoor station via a data network or a telephone network for the purpose of transmitting PCM signals. In this case, the units (3 and 4) can be replaced by appropriate units for adapting the data signals to such a network.

The control unit (2) of the illustrated embodiment contains a processor unit (5) with peripheral devices for performing the necessary control functions. Single chip computer, i.e. H. Complete modules with processor and memory are common building blocks today that are both inexpensive and -3-

AT 393 427 B are reliable. Such components are therefore today preferred to the conventional circuits for performing control functions. The unit (2) is therefore preferably a single chip computer, the functional units illustrated in the block (2) are simulated by different program loops in the computer program. The units contained in block (2), including unit (5), can also be constructed using 5 conventional methods in order to achieve the same control function.

A data sequence is sent via the interface (1) from the data RAID device (DEE) to a serial / parallel converter (6). With asynchronous transmission, each character arrives in the form of a small block, which is surrounded by a start bit and a stop bit. The converter (6) is preferably designed such that it removes these surrounding bits when converted to parallel transmission. The block received is transmitted from the 10 converter (6) to the unit (5).

According to the present invention, a clock (8) is triggered as soon as a data block is received. The clock generator (8) can be equipped by the processor unit (5) immediately after the data block has been transmitted from the circuit (6) to the unit (5) or by the circuit (6) directly, and then expediently after receiving the stop bit. The timer (8) is triggered again after receipt of each data block. Another possibility would be to start the timer (8) on every positive edge in the data input. In the case of synchronous transmission, the clock generator can be triggered by reading the header information in each protocol, for example by reading certain characters which contain " clear frame " or the like, which then indicates a data pause, or a signal from the clock register to a specific input of the unit (at a predetermined time after the start, for example after a time period which corresponds to three or more data blocks). 5), which indicates 20 that a pause was found in the transmission.

A ring buffer memory (9) is connected to the data unit (5), i. H. the buffer memory »has cyclical data input and cyclical data output. Such a buffer memory (9) is used in modern modems to compensate for the difference between the Baude rate d »data terminal equipment and the Baude rate in the transmission network. 25 The mode of operation of a ring buffer memory is illustrated in FIG. 2, which has the properties required for use in a device according to the invention. The inner ring (Ij) represents the

Memory cells of the unit. It is advanced clockwise by one step for each output. Each step corresponds to a memory location with a content of one byte (8 bits). The data is output via the line shown on the right. The data input into the clockwise rotating inner storage ring 30 (Ij) takes place counterclockwise to the ring, so that the storage cells counterclockwise to the output line around the ring are filled with new information up to a stop (10), beyond which stop no more data the ring (Ij) can be stored. The spoke should be so large that not all

Cells in the ring (Ij) are filled anticlockwise until they stop (10) before they are dispensed. As is generally the case, a blocking function against overstoring is provided. Immediately after detection a "35 pause" the data read in immediately before the pause and in certain cases also the data read in in the memory immediately after the pause are checked. After a rumen the memory was completely read out, ie. H. the read-in display is at (a), an area in which no data can be read must be provided between the output line and the stop (10) so that data can be output before the pause in such cases. In this embodiment, therefore, at least in 40 specific cases, data containing a switching code are also output on the line if this is in the

Practice also has no adverse effects. Optionally, the processor (5) can be programmed so that it follows the number of steps between the read-in and output process and, after a pause, checks the contents of the memory locations around the pause if these locations have been indexed up to the output line. The storage space after the stop (10), in which no data can be read, is in this case 45 from the above. Reasons also necessary.

In a further variant, a delay in the registration of the incoming data flow occurs when the work content of the buffer memory, i. H. the address difference between the data word last read in and the data word last output decreases or becomes zero. Such a delay or a sequence of delays exceeding a predetermined value is registered as a pause and represents a state that the data words immediately before and / or after the pause with the current address code for the device, the control commands, etc. to be compared.

3 shows the operation of a ring buffer memory using another example. In this embodiment, too, the inner ring (I2) represents the memory cells of the memory. For each implemented one

The reading process is advanced by one step clockwise (I2), with each step corresponding to 55 memory locations with a content of one byte (8 bits). The output takes place via the outer ring in the same order in which the data was read. The output is thus sequentially counterclockwise through the outer ring to the right. In principle, in this embodiment, the entire memory (I2) can be read out, with the data read from the memory being output on the right-hand side via the output line. Alternatively, however, a stop (11) can also be provided, which causes 60 that a data output counterclockwise to the stop can only take place under a certain condition which is -4-

AT 393 427 B can determine that the area between the input line on the left-hand side and the stop (11) can only be read out if a pause has been sensed and a check of this area has shown that no switching code was read in this area.

2 and 3 show various methods in which the buffer memory can operate and be controlled in order to achieve the cyclic function mentioned. So z. B. a ring counter for read and output addresses (not shown) may be provided, which is controlled by the processor unit (5). The unit (5) transmits a signal present at an output (I) to an indexing input of an input ring counter, at whose parallel output a value is present which corresponds to the existing counter setting for the transmission to a first address input from the memories (Ij or I2 ) corresponds (see Fig. 2 or 3). The value measured on a data bus that connects the unit (5) and memory (9) to one another is read. In a similar way, an O-ring counter for reading an output signal at an output (A) of the unit (5) is indexed. This count value is transported to a second address input of the storage station (Ij or I2). The value stored in this address is sent to a via the data bus

Forwarded parallel / serial converter, which serializes the data and adds the start and stop bits before transmission to the unit (3).

According to the present invention, the last characters to be read into the buffer memory (e.g. three characters) are read out after each signal sent by the clock generator (8) to the data unit (5). Therefore, as illustrated in the example shown, an output (B) of the unit (5) can be coupled to a reverse indexing input on the read-in ring counter. If a pause is displayed, the counter is reversed, and the memory content of the reversely indexed addresses in the buffer memory is sent via the data bus to the output processor unit (5) and compared with the special codes stored in a memory (12) which indicate the transition from Effect data transfer to control mode. If one of the characters output matches one of the stored characters, the system is switched to the control mode represented by the character, for example from reception to transmission, adjustment of the baud rate, or the like. So there can be several different characters for different functions in the memory (12) can be saved.

The system can also be designed in such a way that data words which arrive after a pause from the data terminal device are either checked by themselves as an alternative to the example described above or additionally in order to achieve an even greater level of error security. In the latter case, the data terminal device (DEE) can be designed so that it sends two identical words, which represent switching commands, with a pause in between. Other combinations are also possible, such as. B. the transmission of a pause on each side of a switching command word or the transmission of two switching code words with a pause in between and a »pause before and / or after the sequence.

The memory (12) can be a reprogrammable memory. In addition, other information such as, for example, B. Telephone numbers, routine requests, etc. can be stored. In this case, the memory (12) is preferably an electrically changeable read-only memory (EAROM) or a RAM with a reserve.

It is remarkable that the control of the modem according to the invention is carried out only by signals which are transmitted in the normal data flow exclusively by the data terminal equipment (DEE). The external data arriving via the units (3 and 4) and via a serial / parallel converter (14), which has essentially the same properties as the converter (6), therefore contains no signals other than data for forwarding to the device ( DEE). These signals would therefore be temporarily stored in a conventional buffer memory (15). H. without there being any additional output possibility in the memory (9). The processor (5) then transports data from the buffer memory (15) via a parallel / serial converter (16) of essentially the same type as converter (13) and the interface (1) to the data terminal device (DEE).

As is customary in modern computer technology, the described function with buffer memories and their ring counters can easily be simulated by program loops in the program of the processor unit (5), and the memories (9, 15 and 12) can have different parts of one and the same working memory in one Be a single chip computer, in which case the information in the memory (12) remains stored by a reserve voltage source, for example a battery circuit or the like, even if the supply voltage for operating the modem is uninterrupted. The last data words entered are output at the address locations that are immediately in front of the address where the next data word should have been read. The clock (8) can also be simulated in a program loop, which is a matter of course today.

When transmitting data from the data terminal device (DEE) to the network, it is expedient to have the processor unit (5) only check data words after a pause. If a subsequent data word matches a switching code, the following data word is interpreted as a message to the modem and is not forwarded to the network, but rather deleted from the memory (9)

Since only the data words received around a pause are checked, there is a much greater security against incorrect switching of the modem than would be the case if every incoming data word with -5-

Claims (10)

AT 393 427 B would have to be compared data words which represent a conversion from the data transmission into the control function. Many modifications are still possible within the scope of the present invention. For example, instead of the ring buffer memory illustrated and described here, another embodiment of such a memory can also be used. 1. Device for the transmission of data between a data terminal device and a remote station connected to the common transmission network, for example a counter station, with a modem which converts the signals arriving from the transmission network into a format suitable for processing in the data terminal device and those arriving from the data terminal device Converts signals into a format suitable for transmission over the transmission network, and with a control unit which switches from transmission mode to control mode when receiving predetermined characters, characterized in that the control unit (2) has a pause detection circuit (5, 6, 8) for detecting Contains pauses in the data stream coming from the data terminal device (DEE) and that the control unit (2), upon detection, detects such a pause whether a predetermined code word is contained in a specific area before and / or after the pause in the data stream and after Fes Setting such a code word switches the device from the operating mode of the data transmission to an operating mode in which control commands are carried out. 2. Device according to claim 1, characterized in that the pause detection circuit (5, 6, 8) contains a timer (8) with a previously set time interval and triggers the clock (8) with each incoming data block. 3. Device according to claim 2, characterized in that the pause detection circuit (5,6,8) restarts the timer »(8) after receipt of the stop bit in each data block received during asynchronous data transmission. 4. Device according to claim 2, characterized in that the pause detection circuit (5,6,8) triggers the timer (8) on each »positive edge in the incoming data flow in the control unit. 5. Device according to claim 2, characterized in that in the case of synchronous transmission of the timer (8) from the pause detection circuit (5, 6, 8) after receipt of a certain character in the header information of a protocol, for example a character which is not " clear frame " means restarting. 6. Device according to one of claims 1 to 5, characterized in that the control device (2) contains a buffer memory (9), in which the data coming from the data terminal (DEE) is written under consecutive addresses and read out in the same order The readout speed can differ from the write speed and that the control unit monitors the address difference between the last written data words, a reduction in the address difference is registered as a delay in the incoming data stream and a pause is recognized by the fact that this delay or a Sequence of delays exceeds a predetermined value. 7. Device according to one of claims 1 to 5, characterized in that in the control unit (2) there is a buffer (9) which temporarily transmits the last data arriving from the data terminal device (DEE) to the transmission network (TN ) is prevented within a predetermined data area in the data flow, comprising a corresponding number of bytes (8 bits). 8. Device according to claim 6 or 7, characterized in that the buffer (9) contains a storage »device with cyclic reading and output possibility and the control unit (2) temporarily saves at least the last incoming data words. 9. Device according to claim 8, characterized in that the memory device (9) is a ring buffer memory »with cyclical» data input and output at different baud rates, the last (s) being read into the memory » n) data word (s) are output when the specified point in time in the timer device (8) has been reached -6- AT 393 427 B 10. Device according to one of claims 1 to 9, characterized in that the control unit (2) determines, after detection of a pause, whether the data stream in a region associated with the pause contains a predetermined combination of pauses and codewords. To this 2 sheets of drawings -7 -