AR127553A1 - Procesamiento de caja blanca para codificación con valores enteros grandes - Google Patents

Procesamiento de caja blanca para codificación con valores enteros grandes

Info

Publication number
AR127553A1
AR127553A1 ARP220103002A ARP220103002A AR127553A1 AR 127553 A1 AR127553 A1 AR 127553A1 AR P220103002 A ARP220103002 A AR P220103002A AR P220103002 A ARP220103002 A AR P220103002A AR 127553 A1 AR127553 A1 AR 127553A1
Authority
AR
Argentina
Prior art keywords
white box
secrets
encoding
integer values
box processing
Prior art date
Application number
ARP220103002A
Other languages
English (en)
Inventor
Lex Aaron Anderson
Original Assignee
Arris Entpr Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arris Entpr Llc filed Critical Arris Entpr Llc
Publication of AR127553A1 publication Critical patent/AR127553A1/es

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/723—Modular exponentiation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G06F7/725—Finite field arithmetic over elliptic curves
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/16—Obfuscation or hiding, e.g. involving white box

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Storage Device Security (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)

Abstract

Se describe un método y aparato para procesar de manera segura una entrada para generar una salida de acuerdo con uno o más secretos codificados. En una modalidad, el método comprende un conjunto de secretos S compuestos por una pluralidad de secretos s₁, s₂, ..., sₙ, generar una primera estructura de datos basada en la codificación aleatoria del primer secreto s₁, y realizar una pluralidad de operaciones criptográficas de acuerdo con la entrada y los secretos codificados s₂, ..., sₙ para calcular la salida de acuerdo con cada secreto en la implementación de la caja blanca, la implementación de caja blanca que tiene al menos una estructura de datos adicional que opera sobre los secretos codificados aleatoriamente.
ARP220103002A 2021-11-03 2022-11-02 Procesamiento de caja blanca para codificación con valores enteros grandes AR127553A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US202163275284P 2021-11-03 2021-11-03

Publications (1)

Publication Number Publication Date
AR127553A1 true AR127553A1 (es) 2024-02-07

Family

ID=84537898

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP220103002A AR127553A1 (es) 2021-11-03 2022-11-02 Procesamiento de caja blanca para codificación con valores enteros grandes

Country Status (4)

Country Link
US (1) US20230134216A1 (es)
AR (1) AR127553A1 (es)
TW (1) TW202324967A (es)
WO (1) WO2023081222A1 (es)

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8752032B2 (en) * 2007-02-23 2014-06-10 Irdeto Canada Corporation System and method of interlocking to protect software-mediated program and device behaviours
US8600047B2 (en) * 2008-05-07 2013-12-03 Irdeto Corporate B.V. Exponent obfuscation
US8751822B2 (en) * 2010-12-20 2014-06-10 Motorola Mobility Llc Cryptography using quasigroups
US9189425B2 (en) * 2011-09-01 2015-11-17 Apple Inc. Protecting look up tables by mixing code and operations
US9916538B2 (en) * 2012-09-15 2018-03-13 Z Advanced Computing, Inc. Method and system for feature detection
US10333702B2 (en) * 2012-03-20 2019-06-25 Irdeto B.V. Updating key information
CN104335219B (zh) * 2012-03-30 2018-06-05 爱迪德技术有限公司 使用变量相关编码来保护可访问的系统
US10372886B2 (en) * 2015-05-05 2019-08-06 Nxp B.V. Protecting the input/output of modular encoded white-box RSA/ECC
CA3046866C (en) * 2016-12-12 2022-07-05 Arris Enterprises Llc Strong white-box cryptography
MX2019008264A (es) * 2017-01-09 2020-01-27 Arris Entpr Llc Sistema homomorfico de caja blanca y metodo para utilizarlo.
EP3506558A1 (en) * 2017-12-28 2019-07-03 Koninklijke Philips N.V. Whitebox computation of keyed message authentication codes
EP3664359A1 (en) * 2018-12-07 2020-06-10 Koninklijke Philips N.V. A computation device using shared shares
US20200313850A1 (en) * 2019-03-29 2020-10-01 Irdeto Canada Corporation Method and apparatus for implementing a white-box cipher
US11556298B1 (en) * 2021-07-30 2023-01-17 Sigmasense, Llc Generation and communication of user notation data via an interactive display device

Also Published As

Publication number Publication date
US20230134216A1 (en) 2023-05-04
TW202324967A (zh) 2023-06-16
WO2023081222A1 (en) 2023-05-11

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