TWI456691B - Substrate processing method, electronic device manufacturing method and program - Google Patents

Substrate processing method, electronic device manufacturing method and program Download PDF

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TWI456691B
TWI456691B TW095104740A TW95104740A TWI456691B TW I456691 B TWI456691 B TW I456691B TW 095104740 A TW095104740 A TW 095104740A TW 95104740 A TW95104740 A TW 95104740A TW I456691 B TWI456691 B TW I456691B
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insulating film
forming
low dielectric
film
photoresist layer
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TW200636914A (en
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Eiichi Nishimura
Kenya Iwasaki
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Tokyo Electron Ltd
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    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04C—STRUCTURAL ELEMENTS; BUILDING MATERIALS
    • E04C2/00—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels
    • E04C2/30—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by the shape or structure
    • E04C2/32—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by the shape or structure formed of corrugated or otherwise indented sheet-like material; composed of such layers with or without layers of flat sheet-like material
    • E04C2/322—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by the shape or structure formed of corrugated or otherwise indented sheet-like material; composed of such layers with or without layers of flat sheet-like material with parallel corrugations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04B—GENERAL BUILDING CONSTRUCTIONS; WALLS, e.g. PARTITIONS; ROOFS; FLOORS; CEILINGS; INSULATION OR OTHER PROTECTION OF BUILDINGS
    • E04B1/00—Constructions in general; Structures which are not restricted either to walls, e.g. partitions, or floors or ceilings or roofs
    • E04B1/38—Connections for building structures in general
    • E04B1/61—Connections for building structures in general of slab-shaped building elements with each other
    • E04B1/6108—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together
    • E04B1/612—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces
    • E04B1/6125—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces with protrusions on the one frontal surface co-operating with recesses in the other frontal surface
    • E04B1/6137—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces with protrusions on the one frontal surface co-operating with recesses in the other frontal surface the connection made by formlocking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67201—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the load-lock chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step

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Claims (12)

一種基板之處理方法，係具有含碳之低介電率絕緣膜，該低介電率絕緣膜係具有碳濃度比該低介電率絕緣膜減低之表面損傷層的除去基板之上述低介電率絕緣膜之上述表面損傷層的處理方法，具備以下步驟：表面損傷層暴露步驟，使上述表面損傷層於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；及表面損傷層加熱步驟，使暴露於上述混合氣體環境之表面損傷層加熱至特定溫度。 A substrate processing method comprising a carbon-containing low dielectric constant insulating film, wherein the low dielectric constant insulating film has a low dielectric constant of a substrate for removing a surface damage layer having a carbon concentration lower than the low dielectric constant insulating film The method for treating the surface damage layer of the insulating film has the following steps: a surface damage layer exposure step, exposing the surface damage layer to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a specific pressure; and a surface damage layer heating step, The surface damage layer exposed to the above mixed gas atmosphere is heated to a specific temperature. 如申請專利範圍第1項之基板之處理方法，其中上述表面損傷層暴露步驟，係對上述基板施予無電漿蝕刻處理。 The method for processing a substrate according to claim 1, wherein the surface damage layer exposure step is performed by applying a plasma-free etching treatment to the substrate. 如申請專利範圍第1項之基板之處理方法，其中上述表面損傷層暴露步驟，係對上述基板施予乾燥洗淨處理。 The method for treating a substrate according to claim 1, wherein the surface damage layer exposure step is performed by applying a dry cleaning treatment to the substrate. 如申請專利範圍第1項之基板之處理方法，其中上述混合氣體中上述氟化氫對上述氨之體積流量比為1~1/2，上述特定壓力為6.7×10-2 ~4.0Pa。The method for processing a substrate according to claim 1, wherein a volume flow ratio of the hydrogen fluoride to the ammonia in the mixed gas is 1 to 1/2, and the specific pressure is 6.7×10-2. ~4.0Pa. 如申請專利範圍第1項之基板之處理方法，其中上述特定溫度為80~200℃。 The method for processing a substrate according to claim 1, wherein the specific temperature is 80 to 200 °C. 如申請專利範圍第1項之基板之處理方法，其中另具有：生成物產生條件決定步驟，用於測定具有上述表面損傷層之低介電率絕緣膜之形狀，依該測定之形狀決定上述混合氣體中上述氟化氫對上述氨之體積流量比與 上述特定壓力之中至少之一。 The method for processing a substrate according to claim 1, further comprising: a product generation condition determining step of measuring a shape of the low dielectric constant insulating film having the surface damage layer, and determining the mixture according to the shape of the measurement The volumetric flow ratio of the above hydrogen fluoride to the above ammonia in the gas At least one of the above specific pressures. 一種基板之處理方法，係具有至少由光阻劑膜或硬質遮罩膜構成之遮罩膜，該遮罩膜具有表面損傷層的除去基板之上述遮罩膜之上述表面損傷層的處理方法，具備以下步驟：表面損傷層暴露步驟，使上述表面損傷層於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；及表面損傷層加熱步驟，使暴露於上述混合氣體環境之表面損傷層加熱至特定溫度。 A method for processing a substrate, comprising: a mask film comprising at least a photoresist film or a hard mask film, wherein the mask film has a surface damage layer for treating the surface damage layer of the mask film of the substrate, The method includes the steps of: exposing the surface damage layer to a mixed atmosphere containing ammonia and hydrogen fluoride under a specific pressure; and heating the surface damage layer to heat the surface damage layer exposed to the mixed gas environment To a specific temperature. 一種電子裝置之製造方法，具備以下步驟：低介電率絕緣膜形成步驟，在半導體基板上所形成由下部電極、容量絕緣膜及上部電極構成之電容器上，形成含碳之低介電率絕緣膜；光阻層形成步驟，於上述形成之低介電率絕緣膜上形成特定圖案之光阻層；電漿加工形成步驟，使用該形成之光阻層，藉由電漿處理，於上述低介電率絕緣膜加工成形到達上述上部電極之連接孔；連接孔表面暴露步驟，使上述加工成形之連接孔表面，於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；及連接孔表面加熱步驟，使暴露於上述混合氣體環境之連接孔表面加熱至特定溫度。 A method of manufacturing an electronic device comprising the steps of: forming a low dielectric constant insulating film, forming a low dielectric constant insulating material containing carbon on a capacitor formed of a lower electrode, a bulk insulating film and an upper electrode on a semiconductor substrate; a film; a photoresist layer forming step of forming a photoresist layer of a specific pattern on the low dielectric insulating film formed; a plasma processing forming step, using the formed photoresist layer, by plasma treatment, at the above low Forming a dielectric film to form a connection hole of the upper electrode; and exposing the surface of the connection hole to expose the surface of the formed connection hole to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a specific pressure; and connecting the surface of the hole The heating step heats the surface of the connection hole exposed to the mixed gas atmosphere to a specific temperature. 一種電子裝置之製造方法，具備以下步驟： 層間絕緣膜形成步驟，在半導體基板上形成含碳之低介電率絕緣膜，於該低介電率絕緣膜上形成碳濃度低於上述低介電率絕緣膜的其他絕緣膜而形成層間絕緣膜；電漿加工形成步驟，藉由電漿處理於上述層間絕緣膜加工成形配線溝；配線溝表面暴露步驟，使至少上述低介電率絕緣膜中之配線溝表面，於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；配線溝表面加熱步驟，使暴露於上述混合氣體環境之配線溝表面加熱至特定溫度；其他絕緣膜除去步驟，除去上述其他絕緣膜；及配線形成步驟，於上述配線溝導入導電材料而形成配線。 A method of manufacturing an electronic device, comprising the steps of: An interlayer insulating film forming step of forming a carbon-containing low dielectric insulating film on the semiconductor substrate, and forming an interlayer insulating film on the low dielectric insulating film to form a lower insulating layer than the low dielectric insulating film a plasma processing forming step of forming a wiring trench by the plasma treatment on the interlayer insulating film; and a wiring trench surface exposure step of exposing at least the surface of the wiring trench in the low dielectric insulating film to a specific pressure In a mixed gas atmosphere containing ammonia and hydrogen fluoride; the surface of the wiring trench is heated to heat the surface of the wiring trench exposed to the mixed gas atmosphere to a specific temperature; the other insulating film removing step removes the other insulating film; and the wiring forming step is The wiring trench is introduced into a conductive material to form a wiring. 如申請專利範圍第9項之電子裝置之製造方法，其中具有：光阻層形成步驟，於上述其他絕緣膜上形成光阻層；及去灰步驟，除去該形成之光阻層；於該去灰步驟，使上述光阻層於特定壓力下暴露於含氨及氟化氫之混合氣體環境中，使暴露於上述混合氣體環境之上述光阻層加熱至特定溫度。 The method of manufacturing an electronic device according to claim 9, comprising: a photoresist layer forming step of forming a photoresist layer on the other insulating film; and a ash removing step of removing the formed photoresist layer; In the ash step, the photoresist layer is exposed to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a specific pressure to heat the photoresist layer exposed to the mixed gas atmosphere to a specific temperature. 一種電子裝置之製造方法，具備以下步驟：導電膜形成步驟，於半導體基板上形成含矽之導電 膜；低介電率絕緣膜形成步驟，在該形成之導電膜上，形成含碳之低介電率絕緣膜；光阻層形成步驟，於上述形成之低介電率絕緣膜上形成特定圖案之光阻層；電漿加工形成步驟，使用該形成之光阻層，藉由電漿處理，於上述低介電率絕緣膜加工成形到達上述上部電極之連接孔；連接孔表面暴露步驟，使上述加工成形之連接孔表面，於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；及連接孔表面加熱步驟，使暴露於上述混合氣體環境之連接孔表面加熱至特定溫度；去灰步驟，除去上述光阻層；及配線形成步驟，於上述連接孔導入導電材料而形成配線。 A method of manufacturing an electronic device, comprising the steps of: forming a conductive film to form a conductive layer containing germanium on a semiconductor substrate a low dielectric constant insulating film forming step of forming a carbon-containing low dielectric insulating film on the formed conductive film; and a photoresist layer forming step of forming a specific pattern on the formed low dielectric insulating film a photoresist processing step of forming a photoresist layer by using the formed photoresist layer to form a connection hole of the upper electrode by forming the low dielectric constant insulating film; and exposing the surface of the connection hole to enable The surface of the connecting hole formed by the above process is exposed to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a specific pressure; and the surface of the connecting hole is heated to heat the surface of the connecting hole exposed to the mixed gas atmosphere to a specific temperature; And removing the photoresist layer; and a wiring forming step of introducing a conductive material into the connection hole to form a wiring. 一種電子裝置之製造方法，具備以下步驟：導電膜形成步驟，於半導體基板上形成含矽之導電膜；低介電率絕緣膜形成步驟，在該形成之導電膜上，形成含矽之低介電率絕緣膜；反射防止膜形成步驟，在該形成之低介電率絕緣膜上，形成反射防止膜；光阻層形成步驟，於該形成之反射防止膜上形成對應 所期望之閘門形狀之圖案的光阻層；反射防止膜除去步驟，使用該形成之光阻層，藉由蝕刻上述反射防止膜進行部份地除去，使上述低介電率絕緣膜露出；低介電率絕緣膜除去步驟，使用上述形成之光阻層，藉由電漿處理除去上述露出之低介電率絕緣膜，使上述導電膜露出；低介電率絕緣膜側面暴露步驟，於特定壓力下，將於上述低介電率絕緣膜除去步驟中未被除去之上述光阻層下的於上述低介電率絕緣膜除去步驟中未被除去之上述光阻層下的上述低介電率絕緣膜之部份的側面暴露於含氨及氟化氫之混合氣體環境中；低介電率絕緣膜側面加熱步驟，使暴露於上述混合氣體環境之上述低介電率絕緣膜之部份的側面加熱至特定溫度；導電膜除去步驟，藉由蝕刻除去未被覆蓋於上述導電膜中上述未被除去之低介電率絕緣膜之部份的導電膜。 A method for manufacturing an electronic device, comprising the steps of: forming a conductive film, forming a conductive film containing germanium on a semiconductor substrate; forming a low dielectric insulating film, forming a low dielectric containing germanium on the formed conductive film An electric resistance insulating film; an anti-reflection film forming step of forming an anti-reflection film on the formed low-k dielectric insulating film; and a photoresist layer forming step for forming a corresponding on the formed anti-reflection film a photoresist layer having a pattern of a desired gate shape; a step of removing the anti-reflection film, using the formed photoresist layer to partially remove the anti-reflection film by etching, thereby exposing the low-k dielectric insulating film; a dielectric-rate insulating film removing step of removing the exposed low-k dielectric insulating film by plasma treatment to expose the conductive film by using a photoresist layer formed as described above; and exposing the low-dielectric insulating film side surface to a specific one The low dielectric under the photoresist layer which is not removed in the low dielectric insulating film removal step under the photoresist layer which is not removed in the low dielectric constant insulating film removing step, under pressure The side of the portion of the insulating film is exposed to a mixed gas atmosphere containing ammonia and hydrogen fluoride; the side of the low dielectric constant insulating film is heated to expose the side of the portion of the low dielectric insulating film of the mixed gas atmosphere Heating to a specific temperature; in the conductive film removing step, the conductive film not covering the portion of the above-mentioned conductive film which is not removed by the low dielectric insulating film is removed by etching.
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