Μ Β7 .doc/006 五、發明説明（/ ) 本發明是有關於一種協定轉換電路，且特別是有關於 —種DMA至USB之協定轉換電路及其資料傳輸方法，其 不論USB主控器是否知道傳輸之資料大小，可隨時通知 USB裝置發出短資料封包或零資料封包，以回應主控器來 結束USB IRP傳送= 直接記憶體存取（Direct Memory Access;以下簡稱DMA) 爲習知者所熟知的一種資料傳輸模式，用以從一裝置透過 一週邊裝置傳輸資料至另一裝置中，目前已在各主機系 統，甚至週邊裝置上應用己久，乃爲眾人所熟悉而不可偏 廢之。但是，通用串行匯流排(Universal Serial Bus ;以下簡 稱USB)係爲一新興起之傳輸協定，USB意圖將週邊琴1機 系統之傳輸方式統一化，使得未來週邊與主機之連結方式 都透過USB，以方便使用者連結各週邊與主機系統。 請參照第1圖，第i圖繪示的是傳統直接記憶體存取 (DMA)與通用串行匯流排（USB)間之協定轉換電路的方塊 圖。 由第1圖得知，DMA主控器(Master)lO讀取(RD)或DMA 從屬器(Slave)12寫入(WR)所得到的資料(DATA)，存放在內 部之先進先出(以下簡稱DAT A FIFO) 14內，其中DATA FIFO 亦即資料緩衝器。DATA FIFO 14可以爲一個以上，並且每 個FIFO 14之長度需足夠USB每個交易(Transaction)的資料 長度。在USB匯流排16端有一個USB裝置(USB Engine)18， 其用以負責將各個FIFO 14內的資料，依據USB協定回應 到USB匯流排16上。 3 本紙張尺度通用中國國家標準（CNS ) A4規格（210X297公釐） (¾先聞讀背面之注意事項再填拜本頁) .裝. -、tr 線 ；44273 ^ 3 685twf.doc/006 A7 B7 五、發明説明（2 ) 在USB系統中’所有裝置都是附屬裝置(ciient device)， 亦即都是被動的裝置。當USB主控器(USB host controller) 對此裝置下IN表徵封包(IN Token packet)時，裝置可回未 確認（No acknowledge ; NAK)之訊號交換封包（Handshake packet) ’以表示重試(retry)。或，可回予資料封包以提供資 料給主控器，來完成一次的交易。每次資料封包所含之最 大資料大小’即稱爲資料裝載(DATA payload)。而當一個資 料封包所含的資料大小小於資料裝載時，即稱爲短封包 (short packet)。而累積了多次的交易來傳送一個緩衝的資 料，稱爲完成一個輸入輸出要求封包(I/O Request Packet ; IRP)。 然而在DMA之協定中，從屬器12與主控器l〇間的訊 號有資料要求訊號(DRQ)、資料確認訊號(DACK)及結束訊 號(E0P)。當從屬器12準備(Ready)後，即啓動DRQ向主控 器10要求DMA週期(cycle)。而當主控器1〇準備後，即回 應以DACK及讀取/寫入訊號來做DMA之傳輸。等到主控 器10存取完資料後，即完成一次DMA週期。從屬器12可 再啓動DRQ進行下一個DMA週期，待傳輸到最後一個位 兀組之DMA週期時，主控器10同時觸動β〇ρ，以表示完 整傳輸完一個緩衝的資料。 若將兩系統結合在一起，此電路之動作將是—邊對 DMA做存取，一邊對USB之協定做回應。當電路內之無一 DATA HF0 14準備前，則回應USB NAK，亦即重試動作。 等到內部的任一DATA HFO 14準備後，則將data傳送p 4 本紙张尺度通川中囤囤家標準（CNS)A4说格（210X297公釐） (锖先閱讀背面之注意事項再填寫本頁) •裝. •訂 A7 B7 Λ 4273 4 3685twf.doc/006 五、發明説明（彡） USB匯流排16上，如此週而復始即可傳輸一連續之資料。 但問題在於DMA之協定含有位元組數量之訊息(EOP訊號 或位元組數量暫存器），而USB之協定卻沒有。當裝置所傳 輸之資料不爲資料裝載之整數倍時，此裝置可回應USB主 控器予短封包，以終止IRP。 當資料緩衝之大恰爲資料裝載之整數倍，除非USB主 控器預知資料大小，在取得足夠的資料後，不再啓動新的 交易，否則當USB主控器不知道資料大小時，勢必啓動下 一個交易。而此時DMA又以做完傳輸無DMA資料準備的 情況下，此裝置對此一新的USB交易，必回應以NAK，則 此系統鎖住(Lock)了。所以USB主控器預知整個傳輸過程 之資料大小，似乎是必須的，則裝置必須再透過另外的管 道，讓USB主控器知道資料大小，但如此又會加重額外硬 體與軟體的成本。 有鑒於此，本發明的目的就是在提供一種DMA至USB 之協定轉換電路及其資料傳輸方法，以解決習知無法隨時 回應主控器來結束USB IRP傳送所遇到的問題。 本發明的另一目的，提出一種DMA至USB之協定轉換 電路及其資料傳輸方法，可同時運用在DMA主控器或DMA 從屬器上。 爲達成本發明之上述和其他目的，一種直接記憶體存 取至通用串行匯流排之協定轉換電路及其資料傳輸方法， 可同時運用在DMA主控器或DMA從屬器上，係利用簡易 控制單元及簡單之邏輯電路，不論USB主控器是否知道傳 不‘-氏張尺度適用中囤固家標準（CMS ) A4現格（210X297公釐） ^ . W—-M-— '. 'S. (讀先閱讀背面之注意事項再功"本頁)Ｍ Β7.doc / 006 V. Description of the Invention (/) The present invention relates to a protocol conversion circuit, and in particular to a protocol conversion circuit of DMA to USB and its data transmission method, regardless of whether the USB host controller is or not Know the size of the data transferred, you can tell the USB device to send a short data packet or zero data packet at any time, in response to the host controller to end the USB IRP transmission = Direct Memory Access (hereinafter referred to as DMA) A well-known data transmission mode, which is used to transmit data from one device to another through a peripheral device, has been widely used on host systems and even peripheral devices for a long time. However, the Universal Serial Bus (hereinafter referred to as USB) is an emerging transmission protocol. USB intends to unify the transmission methods of the peripheral piano 1 system, so that in the future, the connection methods between the peripheral and the host will be via USB. , So that users can easily connect each peripheral with the host system. Please refer to Fig. 1. Fig. I shows a block diagram of a protocol conversion circuit between a conventional direct memory access (DMA) and a universal serial bus (USB). As can be seen from Figure 1, the data (DATA) obtained by the DMA master 10 read (RD) or DMA slave 12 (WR) is stored in the internal first-in-first-out (hereinafter DAT A FIFO) 14 in which DATA FIFO is the data buffer. There can be more than one DATA FIFO 14, and the length of each FIFO 14 needs to be sufficient for the data length of each transaction of the USB. There is a USB device (USB Engine) 18 at the end of the USB bus 16 which is responsible for responding to the data in each FIFO 14 to the USB bus 16 according to the USB protocol. 3 The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) (¾Please read the precautions on the back before filling this page). Install.-, Tr line; 44273 ^ 3 685twf.doc / 006 A7 B7 V. Description of the invention (2) In the USB system, 'all devices are ciient devices, that is, they are passive devices. When the USB host controller has an IN Token packet on this device, the device can return a Noshake (Nack) signal handshake packet to indicate a retry. . Or, the data packet can be returned to provide data to the main controller to complete a transaction. The maximum data size contained in each data packet is called a DATA payload. When the size of the data contained in a data packet is smaller than the data load, it is called a short packet. And accumulating multiple transactions to transmit a buffered data is called completing an I / O Request Packet (IRP). However, in the DMA agreement, the signal between the slave 12 and the master 10 has a data request signal (DRQ), a data confirmation signal (DACK), and an end signal (E0P). When the slave 12 is ready, it starts DRQ and requests the master 10 to request a DMA cycle. When the host controller 10 is ready, it responds with DACK and read / write signals for DMA transmission. After the host controller 10 has finished accessing the data, a DMA cycle is completed. The slave 12 can start DRQ again for the next DMA cycle. When it is transmitted to the DMA cycle of the last bit group, the master 10 simultaneously activates β0ρ to indicate that a buffered data is completely transmitted. If the two systems are combined together, the action of this circuit will be-while accessing the DMA, responding to the USB protocol. When no DATA HF0 14 in the circuit is ready, it responds to USB NAK, that is, retry the action. When one of the internal DATA HFO 14 is prepared, the data will be transmitted p 4 This paper size Tong Chuan Standard (CNS) A4 format (210X297 mm) (锖 Please read the precautions on the back before filling this page) • Installation. • Order A7 B7 Λ 4273 4 3685twf.doc / 006 V. Description of the invention (彡) On the USB bus 16, you can transfer a continuous data in this way. The problem is that the DMA protocol contains the number of bytes (EOP signal or byte number register), but the USB protocol does not. When the data transmitted by the device is not an integer multiple of the data load, the device can respond to the USB host with a short packet to terminate the IRP. When the size of the data buffer is exactly an integer multiple of the data load, unless the USB host controller predicts the data size and does not start a new transaction after obtaining sufficient data, it will inevitably start when the USB host controller does not know the data size. Next transaction. At this time, when the DMA is ready to transmit without DMA data, the device must respond to NAK for this new USB transaction, and the system is locked. Therefore, it seems necessary for the USB host controller to predict the data size of the entire transmission process. Then the device must pass another pipe to let the USB host controller know the data size, but this will increase the cost of additional hardware and software. In view of this, the object of the present invention is to provide a DMA-to-USB protocol conversion circuit and a data transmission method thereof, so as to solve the problems encountered in conventionally unable to respond to the host controller to end USB IRP transmission at any time. Another object of the present invention is to provide a DMA-to-USB protocol conversion circuit and a data transmission method thereof, which can be applied to a DMA master or a DMA slave at the same time. In order to achieve the above and other objectives of the present invention, a protocol conversion circuit for direct memory access to a universal serial bus and a data transmission method thereof can be applied to a DMA master or a DMA slave at the same time, using simple control Unit and simple logic circuit, regardless of whether the USB host controller knows whether it can pass or not'-Zhang's scale is applicable to the standard CMS A4 (210X297 mm) ^. W—-M-— '.' S . (Read the precautions on the back and then work " this page)
'1T 線 經Μ部屮戎i?·本U Τ;消仆合竹私卬妒 #i^r部中呔"^^h-·1·消介合作.^1印妒 442734 3685twf.d〇c/〇〇6 A7 ---------------- B7 五、發明説明（^：) 輸之資料大小，可隨時通知USB裝置發出短資料封包或零 資料封包，以回應主控器來結束USB irp傳送。且，本發 明之傳送致能產生電路可自動被致能或可由外部邏輯控 制’使得DMA至USB之傳輸通道可自動地再開始傳送。 此外’本發明所提供之直接記憶體存取至通用串行匯 流排之協定轉換電路，具有一主控器與一週邊裝置，主控 器透過一串行匯流排耦接週邊裝置，週邊裝置具有一 DMA 資料源裝置’ DMA資料源裝置用以透過週邊裝置與串行匯 流排傳送資料至主控器中，本發明之協定轉換電路包括串 行匯流排裝置、至少一資料緩衝器、DMA裝置及傳送致能 產生電路。上述串行匯流排裝置耦接串行匯流排用以管理 週邊裝置與主控器間之資料通訊，資料緩衝器用以儲存訊 息’ DMA裝置耦接資料緩衝器及DMA資料源裝置，用以 管理DMA資料源裝置與資料緩衝器間之資料傳輸，當DMA 資料源裝置之所有資料已傳送至資料緩衝器時，DMA裝置 會產生結束訊號，而傳送致能產生電路耦接上述DMA裝 置，用以依據結束訊號與致能訊號產生傳送致能訊號，藉 以驅動DMA裝置，使DMA裝置開始做區塊資料的傳送。 因此，由於本發明所提供之傳送致能產生電路可自動 被致能，使得DMA裝置可自動地傳送區塊資料，同時USB 主控器不論是否知道傳輸之資料大小，其可隨時通知USB 裝置發出短資料封包或零資料封包，以回應主控器來結束 USB IRP傳送，故不論USB主控器是否知道一個IRP的資 料大小，都可輕易地在USB與DMA之間做一個IRP之資'1T line through the Ministry of 屮 屮 i 本? Ben U Τ; eliminate servants together bamboo private 卬 jealousy # i ^ r 部 中 呔 " ^^ h- · 1 · eliminative cooperation. ^ 1 印 印 442734 3685twf.d 〇c / 〇〇6 A7 ---------------- B7 V. Description of the invention (^ :) The size of the data input can be notified to the USB device to send short data packets or zero data packets at any time. To end the USB irp transfer in response to the host controller. Moreover, the transmission enable generation circuit of the present invention can be automatically enabled or can be controlled by external logic 'so that the DMA to USB transmission channel can automatically resume transmission. In addition, the protocol conversion circuit for direct memory access to a universal serial bus provided by the present invention has a main controller and a peripheral device. The main controller is coupled to the peripheral device through a serial bus, and the peripheral device has A DMA data source device 'The DMA data source device is used to transmit data to the main controller through a peripheral device and a serial bus. The protocol conversion circuit of the present invention includes a serial bus device, at least one data buffer, a DMA device, and Transmission enabling circuit. The above-mentioned serial bus device is coupled to the serial bus to manage data communication between the peripheral device and the main controller, and the data buffer is used to store information. The DMA device is coupled to the data buffer and the DMA data source device to manage the DMA. Data transmission between the data source device and the data buffer. When all the data of the DMA data source device has been transferred to the data buffer, the DMA device will generate an end signal, and the transmission enable generation circuit is coupled to the above DMA device for The end signal and the enable signal generate an enable signal to drive the DMA device, so that the DMA device starts to transmit block data. Therefore, because the transmission enabling generating circuit provided by the present invention can be automatically enabled, the DMA device can automatically transmit block data, and the USB host controller can notify the USB device at any time whether it knows the size of the transmitted data or not. Short data packet or zero data packet, in response to the host to end the USB IRP transmission, so whether the USB host knows the data size of an IRP, it can easily make an IRP between USB and DMA.
„ . I 散-- (誚先閲讀背面之注意事項再填r§本頁J -訂 W線 本紙張尺度適扣中國國家標準（CNS ) A4現格（210X297公釐）„. I Scatter-(阅读 Read the precautions on the back before filling in r§ J-booking on this page W-line This paper size is deducted from the Chinese National Standard (CNS) A4 grid (210X297 mm)
4 42 73 A 3685twf.doc/006 A7 ______B7_ 五、發明说明（夂） 料傳輸。 本發明之USB主控器與DMA週邊裝置間之資料傳輸 的方法，包括下列步驟：首先啓始化資料傳輸，以做爲DMA 週邊裝置至USB主控器之DMA週期。接著當資料傳輸在 DMA週期期間完成時，產生一結束訊號於DMA週邊裝置。 最後提供以結束訊號爲基礎之一控制訊號至USB主控器， 以通知USB主控器在DMA週期期間之資料傳輸已完成。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖繪示的是傳統直接記憶體存取(DMA)與通用串 行匯流排(USB)間之協定轉換電路的方塊圖； 第2圖繪示的是依照本發明一較佳實施例的一種直接 記憶體存取與通用串行匯流排間之協定轉換電路的方塊 圖；以及 第3圖繪示的是本發明之協定轉換電路的操作時序 圖。 圖式之標號說明： 10、20 : DMA主控器 12、22 : DMA從屬器 14、30 :資料緩衝器 16 : USB匯流排 18、24 : USB 裝置 本紙张尺度適用中闽國家標準{ CNS ) A4规格（210X297公釐） ------Γ------ I (誚1閲讀背而之泣意事項再填寫本") 訂 44273 4 3 685twf.doc/006 B / 五、發明説明（6) 26 :傳送致能產生電路 28 :位元組計數器 32 :中斷電路 34 :啓始電路 實施例 如習知所述，當USB主控器作一傳輸，卻不知道全部 資料大小時，如何利用USB與DMA之傳輸特性來順利完 成傳輸，請參照第2圖與第3圖，第2圖繪示的是依照本 發明一較佳實施例的一種直接記憶體存取與通用串行匯流 排間之協定轉換電路的方塊圖，以及第3圖繪示的是本發 明之協定轉換電路的操作時序圖。 . 如第2圖所示並將之與習知第1圖相比較可發現，在 USB裝置24與DMA裝置例如DMA主控器20或DMA從屬 器22之間，我們僅需加入一個傳送致能產生電路(Transfer Enable Generation Circuit)26即可解決上述習知問題。 當啓始化（initial)完成，亦即啓始電路（Initialization Circuit)34依據選擇訊號及接收到之訊號例如內部起始訊 號或外部起始訊號，選擇性地產生一致能訊號來致能 (enable)傳送致能產生電路26後，DMA裝置才開始動作， 其中啓始電路34可以一多工器(Multiplexer ; MUX)來實現 之。而在DMA傳送完最後一個位元組時，其中最後一個位 元組可由E0P或位元組計數器28得知，然後就將傳送致 能產生電路26抑制(disable)後，DMA也不再做任何傳送動 作，直到傳送致能產生電路26又重新被致能，DMA才又 本紙張尺度適扣十闽囤家榇率（CNS ) A4現格（210X297公釐） (請先閲讀背面之注意事項再填窍本頁) 訂 44273 4 3685twf.doc/006 A 7 ____________________B7_ 五、發明说明（^/ ) 開始下一個區塊資料的傳送。因此，不論DMA裝置是DMA 主控器20或DMA從屬器22，都可輕易地加入此傳送致能 產生電路26 ’例如DMA主控器20可透過位元組計數器 28，而DMA從屬器22則由EOP可得知DMA的最後傳送 動作，而產生一淸除訊號（clear signal)來抑制傳送致能產生 電路26。 此外，USB對存取本身所有表徵都必須回應，如第2 圖所示，當傳送致能產生電路26被致能後，每當表徵來， USB裝置24就去查看有無有效之內部DATA FIFO 30，若 無表示DMA裝置正在工作，但無足夠之資料，可供做一次 USB交易。所以USB裝置26回應給USB主控器(未顯示）， 如此週而復始，直到傳送致能產生電路26被抑制後。當 USB裝置24接到表徵仍繼續査看有無有效之DATA FIFO 30，若有則繼續回應USB主控制資料封包，直到FIFO 30 內的資料都被傳送完畢，此時中斷產生電路（Interrupt Generation Circuit)32會產生一個中斷訊號(INT)通知其他邏 輯，告知此區塊的資料已全部傳送完。之後若USB主控器 再有IN之表徵，則USB裝置24會回應已沒有資料封包(零 資料封包(null data packet))，來通知USB主控器’此次IRP 已經結束，且已無多餘資料，除非再次致能傳送致能產生 電路26，然後再啓動下一個區塊之資料傳輸。· 依照本發明之架構，即可以很低的電路成本來實現一 功能爲當不論USB主控器是否知道一個IRP的資料大小’ 都可因而輕易地在USB與DMA之間做一個IRP之資料傳 中囤國家標準（CNS ) A4規格（210X297公釐） (誚先閲讀背面之注意事項再填寫本頁) -裝·4 42 73 A 3685twf.doc / 006 A7 ______B7_ 5. Description of the invention (夂) Material transmission. The method for data transmission between a USB host controller and a DMA peripheral device according to the present invention includes the following steps: First, data transmission is initiated as a DMA cycle from the DMA peripheral device to the USB host device. Then, when the data transfer is completed during the DMA cycle, an end signal is generated to the DMA peripheral device. Finally, a control signal based on the end signal is provided to the USB host controller to notify the USB host controller that the data transfer during the DMA cycle has been completed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 A block diagram of a protocol conversion circuit between a conventional direct memory access (DMA) and a universal serial bus (USB) is shown. FIG. 2 shows a direct memory according to a preferred embodiment of the present invention. A block diagram of a protocol conversion circuit between a bank access and a universal serial bus; and FIG. 3 shows an operation timing diagram of the protocol conversion circuit of the present invention. Description of the symbols in the drawings: 10, 20: DMA master 12, 22: DMA slave 14, 30: data buffer 16: USB bus 18, 24: USB device This paper standard applies to the national standard of China and Fujian {CNS) A4 specification (210X297mm) ------ Γ ------ I (诮 1 Read this somber and then fill out this ") Order 44273 4 3 685twf.doc / 006 B / V, Description of the Invention (6) 26: Transmission enabling generating circuit 28: Byte counter 32: Interrupt circuit 34: Start circuit As described in the conventional example, when the USB host makes a transmission, but does not know the total data size How to use USB and DMA transfer characteristics to successfully complete the transfer, please refer to Figures 2 and 3, Figure 2 shows a direct memory access and a universal serial port according to a preferred embodiment of the present invention The block diagram of the protocol conversion circuit between the buses, and FIG. 3 shows the operation timing diagram of the protocol conversion circuit of the present invention. As shown in Figure 2 and compared with the conventional Figure 1, it can be found that between USB device 24 and DMA device such as DMA master 20 or DMA slave 22, we only need to add a transfer enable A generation circuit (Transfer Enable Generation Circuit) 26 can solve the conventional problem. When the initialization is completed, that is, the Initialization Circuit 34 is selectively enabled according to the selected signal and the received signal, such as an internal start signal or an external start signal, to generate a uniform energy signal. ) The DMA device only starts to operate after the enabling enabling circuit 26 is transmitted. The starting circuit 34 can be implemented by a multiplexer (MUX). When the DMA transfers the last byte, the last byte can be known by E0P or byte counter 28. After the transfer enable generation circuit 26 is disabled, the DMA does not do any more. The transmission action, until the transmission enabling circuit 26 is re-enabled, the DMA will be deducted from the paper size (CNS) A4 (210X297 mm) (please read the precautions on the back first) Fill in this page) Order 44273 4 3685twf.doc / 006 A 7 ____________________B7_ V. Description of the Invention (^ /) Start the transmission of the next block data. Therefore, regardless of whether the DMA device is the DMA master 20 or the DMA slave 22, the transfer enable generation circuit 26 can be easily added. For example, the DMA master 20 can pass the byte counter 28, and the DMA slave 22 can According to the EOP, the last transfer operation of the DMA is known, and a clear signal is generated to suppress the transfer enable generation circuit 26. In addition, the USB must respond to all representations of the access itself. As shown in Figure 2, after the transmission enable generation circuit 26 is enabled, whenever the representation comes, the USB device 24 checks to see if there is a valid internal DATA FIFO 30. If there is no indication that the DMA device is working, but there is not enough information available for a USB transaction. Therefore, the USB device 26 responds to the USB host controller (not shown), and so on and so on, until the transmission enabling circuit 26 is suppressed. When the USB device 24 receives the characterization, it continues to check whether there is a valid DATA FIFO 30. If so, it continues to respond to the USB main control data packet until the data in the FIFO 30 has been transmitted. At this time, the Interrupt Generation Circuit 32 will generate an interrupt signal (INT) to notify other logic, and inform that the data of this block has been completely transmitted. After that, if the USB host has the IN character again, the USB device 24 will respond that there is no data packet (null data packet) to notify the USB host that 'this IRP is over and there is no more The data, unless the enable generation circuit 26 is enabled again, and then the data transmission of the next block is started. · According to the structure of the present invention, a function can be realized at a very low circuit cost. When the USB host controller knows the size of an IRP, it can easily perform an IRP data transfer between USB and DMA. China National Standard (CNS) A4 Specification (210X297 mm) (诮 Please read the precautions on the back before filling this page) -Packing ·
、1T 線 4 42 73 4 3685twf,doc/006 A7 ________B7 五、發明説明（》） 輸。 而傳送致能產生電路26之再次致能，可透過外部邏輯 以提供使用者便於控制。或，可透過USB裝置24在裝置 送出短資料封包或零資料封包之後，即表示USB裝置24 已告知USB主控器IRP已經結束，USB裝置24即可自行 再次致能傳送致能產生電路26,自動地再次啓動下一個區 塊之資料傳輸，如此即可達到智慧且自動之DMA至USB 之轉換電路。 綜上所述，本發明的特徵之一，係利用簡易控制單元 包括傳送致能產生電路及簡單之邏輯電路，不論USB主控 器是否知道傳輸之資料大小，可隨時通知USB裝置發出短 , 資料封包或零資料封包，以回應主控器來結束USB IRP傳 送。 本發明的特徵之二，係傳送致能產生電路可自動被致 能，使得DMA至USB之傳輸通道可自動地再開始傳送， 此外傳送致能產生電路亦可由外部邏輯控制。 本發明的特徵之三，可同時運用在DMA主控器或DMA 從屬器上。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適扣中國國家標準（CNS )六4说格（210X297公釐） -----------,)--裝！ .'/ί. (請先閲讀背面之注意事項再填巧本頁) 訂 .1}「線·、 1T line 4 42 73 4 3685twf, doc / 006 A7 ________B7 V. Description of invention ("). The re-enabling of the transmission enabling generating circuit 26 can provide external users with easy control through external logic. Alternatively, after the device sends a short data packet or a zero data packet through the USB device 24, it means that the USB device 24 has informed the USB host that the IRP has ended, and the USB device 24 can re-enable the transmission of the generation circuit 26 by itself. Automatically start the data transfer of the next block again, so that a smart and automatic DMA to USB conversion circuit can be achieved. In summary, one of the features of the present invention is to use a simple control unit including a transmission enabling generating circuit and a simple logic circuit. Regardless of whether the USB host controller knows the size of the transmitted data, the USB device can be notified to send short messages at any time. Packet or zero data packet in response to the host to end the USB IRP transmission. The second feature of the present invention is that the transmission enabling generating circuit can be automatically enabled, so that the DMA to USB transmission channel can automatically resume transmission, and in addition, the transmission enabling generating circuit can also be controlled by external logic. The third feature of the present invention can be applied to a DMA master or a DMA slave at the same time. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. The size of this paper is suitable for Chinese National Standards (CNS) 6-4 (210X297 mm) -----------,)-installed! . '/ ί. (Please read the notes on the back before filling out this page) Order .1} "Line ·