TW295696B - - Google Patents

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TW295696B
TW295696B TW084113611A TW84113611A TW295696B TW 295696 B TW295696 B TW 295696B TW 084113611 A TW084113611 A TW 084113611A TW 84113611 A TW84113611 A TW 84113611A TW 295696 B TW295696 B TW 295696B
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item
patent application
dielectric
silicon
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TW084113611A
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Texas Instruments Inc
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
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    • Y10S428/901—Printed circuit

Description

經濟部中央標隼局員工消費合作杜印製 A7 B7 五、發明説明（） : 發明背景 發明領域 本發明係關於一種在互連圖樣上形成平面介電層之方 法及其完整結構。 習知技藝之簡述 就幾何觀點而言，半導體電路已縮小至〇 5微米以下 ，因此對於在半導髏電路中之互連圖樣之内層間介電質（ I LD〉之需求變成非常嚴苛。I ld膜必需以較高孔徑 比充填間隙’且必需提供比現在使用之〗LD膜所需更低 的介電常數。降低介電常數可降低内層和外層電容，而此 兩者可減緩以現今使用於電絕緣之氧化物處理之電路操作 。聚所週知的是，當電路之複雜度增加時，減緩效果更顯 著0 習知技藝使用旋壓玻璃（SOG)以充填空隙和平面 部份或晶片或晶元之所有表面，因此，在多層互連系統中 之金屬之第二和後續層可受到曝光，顯影和蝕刻而無需使 引線變窄或發生其它已知之問題。在習知技藝中使用之 S OG本質上爲有機體，一般爲甲基甲矽烷。以較小的幾 何而言，當有機SOG曝光在通道中時，在導電金屬散佈 在通道中下，會釋出溼氣或其它會引起高電阻在通道中發 生之物質。此問題稱爲通道毒氣，且會發生在使用甲基甲 矽烷基旋壓玻璃以充填空隙和具有金屬互連之多層之積體 .本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） !| I— n ~~~ 裝 訂· n .1 線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消費合作社印製 A7 B7 - ----- ~ —----—_ 五、發明説明（） .* 電路平面化上。化學蒸氣沉積（CVD )鎢沉積在通道中 使有機S OG曝光在通道侧壁上之品質難以符合此嚴苛之 要求，通常會導致不完整的充填通道，由通道之頂部而來 具有高電陴及金屬成長之通道會引起和其它金屬線之短路 。因此，有機SOG之有機部份以鎢源材料而作用在相反 的效果上。 通道毒氣之問題之標準解答爲執行S OG之部份電漿 蚀回，而只留下SOG在金屬引線間或沿著金屬引線。此 種解答需要使設置在整個晶元上之半有機玻璃在電漿蝕刻 劑中蝕回。此步樣非常緩慢，非常髒，且會在晶元上留下 顆粒，並且不均勻。其它的方法，例如使用S OG之薄塗 層，藉由移動通道至SOG層較薄之位置或和細心硬化， 蝕刻，經由烘烤和金屬沉積步驟，以改變連續之程度。 現今，從未有解決高寄生電容和降低金屬引線間隔之 有效方法。已進行之研究包括氟化氣化物之高密度電漿沉 積，CVD parylene ，和其它旋壓材料之吸收，但是它 們需要特殊的處理0 發明概要 依照本發明’可消除相關於SOG之電漿蚀回之步碌 和設備，如此可導致循環時間之改善和成本之降低。平面 化改善了在S OG下之增加S OG厚度和降低氧化物之厚 度0此外，需用以沉積使用於SOG之沉積氧化物層之複 雜處理亦可顯著的降低。 諳 先 閲 讀 背 之 注
I 頁 裝 〇 訂 rv 線一 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印裝 五、發明説明（） 簡言之，本發明使用無機SOG之單厚層， 亚W下所 有的無機S OG在晶元上。且在金屬沉積步棵時， 町，無需在 硬化，或蝕刻上之特別處理。矽氧化物之無機源， *"只i •好爲倍半氧矽烷氫（HSQ)，具有化學式爲（HS i 〇3丫 2 ) η ，且已知爲Dow Corning公司所產製之9-5115介電材料 乃使用以取代在旋壓玻璃中之有機甲基甲矽洗。此種 料 之使用需配合精心之設計但是卻可提供簡化製造過程和 降 低介電常數之簡單處理步驟。HSQ膜之介電常數鏈結 在膜中之S i Η和一OH鍵，且具有比現今使用之内層介 電材料之電漿TEOS氧化物或臭氧TEOS氧化物更低( 的介電常數。再者，介電膜之密度和多孔性會經由對水之 吸收和排除而影響其介電常數0依照本發明，需要使用小 於4.0之介電常數之無機含梦組成物。s〇G之介電常數 可降至約3.0，而現今使用之材料具有約4.1之介電常數。 可使用矽酸鹽基S OG而不會產生通道毒氧。但是當它們 受到硬化處理和經歷未受控制和不可接受之龜裂時，會實 質的委梅。近來亦證明一些有機S 〇G可藉由結合遍体的 氧電衆處理和随後之熱處理而硬化以避免通道電阻和巍裂 ，但是如此仍需要額外的處理步驟。 依照本發明之處理流程，其可使用於D RAM和遲輯 電路製造，包括最初形成互連圖樣在基底上，如同在習知 技藝中，而該互連圖樣由例如轉，銘，銅等適當之材料形 成0電漿原矽酸四乙酯（TE〇s )氧化物具有厚度約 3〇〇0又至5000A，且最好爲4〇〇〇A ，於後沉 請 先 閑 南 之 注 1 裴 〇 訂 線 r\ 本紙張尺度適用中國國家標準（CNS ) Α4規格（21GX297公釐） 295696 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） ： 積在曝光表面上，留下凹痕或坑洞在介於互連圖樣之部份 間之區域中。厚度爲3 5 0 0又至7 3 0 0又，且最好爲 5 4 0 0又之HSQ塗層於後形成在TEOS氧化物上。 而後此結構藉由加熱3 7 5 °C至4 2 5 X：，且最好爲 4 0 0 °C，3 0分鐘至9 0分鐘，最好爲4 5分鐘，在約 6 0 0至7 6 OmTo r r之壓力下，在實質純氮環境中 ，且無氧氣或溼氣下硬化，以將HSQ轉換成實質不具有 —OH鍵之矽氧化物。含水量愈少，則愈少出現一 〇H鍵 ，而介於4.1至3.0之介電常數決定於一OH鍵之數目。所 得之氧化物具有S i Ox結構，其中1SxS2。此種氧 化物對於溼氣具有相當的不透水性，即使其些微的比典型 的S i 〇2之密度小。矽氧化物之介電常數約爲S.lto.i 。具有厚度爲2 0 0 0又至4 0 0 0又，且最好爲 3 0 0 0 X之TEOS氧化物層沉積在HSQ上，而後在 氮氣中，在3To r r至1 5To r r，且最好爲9 Tori· 之壓力下，在3 7 0 °C至4 1 0°C，且最好爲3 9 0 °C之 溫度下，在眞空室中烘烤以提供具有上述介電質之完整互 連層。現在即可以標準的方式對通道蝕刻至互連圖樣，且 藉由重覆上述之處理步驟，互連之進一步層可形成在具有 上述之介電質之介電層上。 藉由在倍半氧矽燒基氫SOG之硬化時，適當的選擇 時間，溫度，和環境，可獲得比現今使用之内層介電膜更 低之電容，且無需額外的處理時間或增加複雜性。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I I I n ^ n n n I n n (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製
Amended ^e^f~^ecjf~ication1n Chinesej^MlJ-- .....(民醺85^f上月夕日送呈） _ (SubmitleJ uji Dt!ct!mbET~~2-, 1990广 *" -----五、發明説明（f ) 附圖簡述 圖1 a至Ig·爲在DRAM之互連圖樣上提供平面介 電層之習知技藝之步驟之流程圖； 圖2 a至2 i爲在递轉電路之互連圖樣上提供平面介 電層之習知技藝之步驟之流程圖：和 a 圖3 a至3 d爲依照本發明可政用在DRAM和邏輯 電路製造之流程圖。 A7 B7 較佳實施例之説明 參考圖la至1宮，其中 上提供年面介電層之習知技藝 藉由沉積例如鎢之互接金屬而 樣和蚀刻如圖1 a所示。7 0 化物層5而後沉積在曝光表面 於互連圖樣之部份間之區域如 6 4 〇 〇又厚之有機SOG層 上，並硬化如圖1 C所示或蝕 先前之蝕回，圖1 C之構造乃 物5曝光如圖1 d所示，而後 合物9由氧氣電漿處理而移去 的聚合物和污染物以水沖洗而 。而後此結構在4 1 0 Ό之溫 5 0 〇 〇又厚之TEOS氧化 圖1 g所示，以提供平面表面 類示在D R 之流程。首 形成在基底 〇 〇 A厚之 上，留下凹 圖1 "b所示 8沉積在圖 回而後硬化 受到蚀回直 ，在此結構 ，如圖1 θ 由表面移去 度下烘烤约 物層1 1沉 A Μ之互連圖樣 先，互連®樣3 1上，而後定圖 電漿Τ Ε 〇 S氧 痕或坑洞7在介 ° 6 2 0 0 至 1 t所承力構造 。而後，妒果無 到Τ Ε Ο S & <匕 上收集之择何聚 所示。其必剩餘 ，如圖1 2V2分钂 積在表面 f所示 ，而後 >，如 ---.------^------、玎------^ t (請先閱讀背面之注意事項再矿¾本頁) 本紙張尺度適两中國國家標隼（CNS ) A4.规福飞210X297公釐） 經濟部中央橾準局員工消費合作社印製 A 7 -____ B7 五、發明説明（) ' ~"" - 參考圖2 a至2 i ，其中顯示在暹輯電路之互連圖樣 上提供平面介電層之習知技藝之流程。首先，互連圈樣 2 3藉由沉積例如鋁之互連金屬而形成在基底2 1上，而 後定圖樣和蚀刻如圖2 a所示。由於鋁會形成小丘，而此 小丘會引起重疊互連層之短路，其必需提供比Dram實 施例中所需更厚之介電層。因此，3 〇 〇 〇又厚之電漿 TEOS氧化物層2 5會沉積在曝光表面上，而留下凹痕 或坑洞2 7在介於互連圖樣之部份間之區域中，如圖2 b 〇 所示。而後爲氮氣電漿崴理，其次爲3 ο Ο 0A厚之臭氧 TEOS氣化物層2 9 ，如圖2 c所示，再次爲4 0 〇 0 厚之電漿TEOS氧化物層31，如圃2d所示0接下 來之步樣和上述對於dram所述之步嫌相同’亦即圖 1。至18相當於圖26至210 參考圖3 a至3d，其中顯杀依照本發明而可使用於 DRAM和邏輯電路製造之流稃。首先，立連圖樣3 3如 同習知技藝般的形成在基底3 5上，而該五連圖樣由適當 之金屬，如鎢，鋁，和銅所形成，如圖3 3所不。而後沉 積厚爲4 0 〇 〇 A之電漿TE〇S氧化物廣3 7在曝光表 面上，留下凹痕或坑洞3 9在介於互連圖，之部份間之區 域中，如圖3b所示。而後形成5 4 Ο 〇A厚之HSQ塗 層4 1在丁£〇3氧化物3 7上，如圖3 c所示。而後使 圖3 c之結構硬化且3 Ο Ο Ο X庳之丁£：〇3氧化物層 4 3沉積在HSQ上，如圖3d所示，以提供具有上述介 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） .. 0 0 1.1 — — II---^—1T1!·^ (請先閲讀背面之注意事項再填寫本頁) A7 --1---?Z_〆 五、發明説明（） . 電質之完整互連層。於此可以標準方式將扎"·.跑，真 圖樣3 3 ，且藉由重覆參考圖3 &至3 d之 連之進一步層可形成在具有上述介電質之膂v a茛速層 技螢中 蹀0 由上可知，本發明提供—種具有介€質一 +之問趙 .U ^ Ύ ^ ，其是平面的，且可克服隱藏在上述之皙知 ，且其需要比依照習知方法所需更少之處璞少 ^邡爲象 •5^ 積 關於進一步之實施例，層37和43在？ 滅準摻雜 摻雜以降低這些層之介電常數。藉由增加含 盛。典 μ述之株 劑，而形成層37和/或43時即可達成上 ς知 型的可使用之含氟材料爲四氟化碳（CF4)，丹π 氧可形成含矽氧化物之氟。 雖然本發明已參考特殊較佳之實施例而做説明，對於 熟悉此項技藝之人士而言仍有許多之變化和修飾之可能性 。因此，下述之申請專利範固應更寬廣的解釋以涵蓋所有 的變化和修飾。 (请先開读背希之注意事項真填寫本 -裝
G - ο —線 經濟部中央樣準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) M規格（2丨οχ297公釐）

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  1. 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 ： 1·一種在互連圖樣之上形成平面介電層之方法，包 含之步驟爲： ⑻提供第一基底具有電互連圖樣； (b)在該互連圖樣上形成介電質第一層； ⑹形成含矽介電質第二層，其與由無機含矽組成之在 第一介電層上之第一層不同：和 ⑹形成介電第三層，其與第二介電層上之第二層不同 〇 2.如申請專利範園第1項所述之方法，其中該第一 層爲電漿產生TEOS氧化物。 3 .如申請專利範園第1項所述之方法，其中該含矽 组成爲H S Q。 4 :如申請專利範園第2項所述之方法，其中該含矽 組成爲H S Q。 5.如申請專利範圍第1項所述之方法，其中該第三 層爲電漿產生TEOS氧化物。 6 .如申請專利範園第2項所述之方法，其中該第三 層爲電漿產生TEOS氧化物。 7 ·如申請專利範園第3項所述之方法，其中該第三 層爲電漿產生TEOS氧化物。 8 ·如申請專利範圍第4項所述之方法，其中該第三 層爲電漿產生TEOS氧化物。 9 ·如申請專利範圍第1項所述之方法，其中形成該 第二層之步驟包含之步驟爲：沉積可受到電解轉換爲矽氧 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） • ο: Γ ^ I I I I I I I I I I I I 訂 I I 1 線 (請先閱讀背面之注意事項再填寫本頁) 11
    申請專利範圍 化物之無機含梦组成在由步碌⑹而來之結構上，並放置所 經濟部中央標準局員工消費合作社印製 ::結構在"純氮且無渔氣之環境中，在等於或低於大 氣壓力之壓力下’而後加熱切組成在由3 7 5。〇至 4 2 5 °C之溫度下約3 〇至9 〇公接 梦氧化物。 分鐘轉換該切组成爲 …如申請專利範困第9項所述之方法，其 組成爲H S Q。 請專利範固第9項所述之方法，其中該溫度 約爲4 〇 〇。<：且加熱約4 5分鐘。 12. 如申請專利範園第1()項 〜〜万5*，其中該适 度約爲4 0 〇。(：且加熱約4 5分鐘。 13. 如申請專利範園第j項所 三層之步碌包含…爲1置由步碌(=其中形成第 ^ ^ ^ (C)而來之結構在眞 空室中，並在氮氣週園中加熱，壓力 叫0丄〇rr至15 Torr,溫度爲 350。(：至43() 加熱時間爲3〇 秒至Θ 〇秒，而後在該結構上沉積厚 〇 ^ ^ ώ 〇 4 〇 0 0 Α之電漿產生TE〇s氧化物層。 14. 如申請專利範園第丄3項所述之方法 度約爲3 9 0 °C，加熱時間約爲6 〇秒。 15. 如申請專利範園第工3項所 〜义方法 約爲9Torr。 16. 如申請專利範圍第1 3項所 〇 万法 約爲3 0 0 0 A。 17. —種多層互連圖樣，包含： A至 其中該ίί 其中壓；5 其中厚/ . 6 . ό^------tr------0 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐} 12 A8 B8 C8 D8 々、申請專利範圍 ： ⑻一基底具有電互連圖樣； (b) 介電第一層在該互連圖樣之上； (c) 含矽之介電第二層，其與在第一介電層上之第一層 不同，該第一介電層由可形成矽氧化物之無機含矽組成所 形成； (d) 介電第三層，其與在第二介電層上之第二層不同； 和 ⑻電互連圖樣設置在第三層之上。 18·如申請專利範圍第1 7項所述之圖樣，其中該含 碎組成爲HSQ。 19·如申請專利範園第1 7項所述之圖樣，其中第二 層具有之介電常數小於4.0。 20·如申請專利範圍第1 8項所述之圖樣，其中第二 層具有之介電常數小於4.0。 (請先閲讀背面之注意事項再填寫本頁) -裝· ο 訂 ο —線 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 13
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Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910003742B1 (ko) * 1986-09-09 1991-06-10 세미콘덕터 에너지 라보라터리 캄파니 리미티드 Cvd장치
JPH10163192A (ja) * 1996-10-03 1998-06-19 Fujitsu Ltd 半導体装置およびその製造方法
JP3123449B2 (ja) * 1996-11-01 2001-01-09 ヤマハ株式会社 多層配線形成法
US6030706A (en) * 1996-11-08 2000-02-29 Texas Instruments Incorporated Integrated circuit insulator and method
US5854503A (en) * 1996-11-19 1998-12-29 Integrated Device Technology, Inc. Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit
JP3109449B2 (ja) * 1997-04-25 2000-11-13 日本電気株式会社 多層配線構造の形成方法
US5866197A (en) * 1997-06-06 1999-02-02 Dow Corning Corporation Method for producing thick crack-free coating from hydrogen silsequioxane resin
TW392288B (en) * 1997-06-06 2000-06-01 Dow Corning Thermally stable dielectric coatings
GB2330001B (en) * 1997-10-06 1999-09-01 United Microelectronics Corp Method of forming an integrated circuit device
TW354417B (en) * 1997-10-18 1999-03-11 United Microelectronics Corp A method for forming a planarized dielectric layer
US5888898A (en) * 1997-10-23 1999-03-30 Advanced Micro Devices, Inc. HSQ baking for reduced dielectric constant
US6087724A (en) * 1997-12-18 2000-07-11 Advanced Micro Devices, Inc. HSQ with high plasma etching resistance surface for borderless vias
US6083850A (en) * 1997-12-18 2000-07-04 Advanced Micro Devices, Inc. HSQ dielectric interlayer
US5958798A (en) * 1997-12-18 1999-09-28 Advanced Micro Devices, Inc. Borderless vias without degradation of HSQ gap fill layers
KR100448245B1 (ko) * 1997-12-30 2004-11-16 주식회사 하이닉스반도체 반도체 소자의 금속배선간 절연막 형성방법
KR100476371B1 (ko) * 1997-12-30 2005-07-05 주식회사 하이닉스반도체 금속층간의평탄화절연막형성방법
US6054379A (en) * 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6833280B1 (en) 1998-03-13 2004-12-21 Micron Technology, Inc. Process for fabricating films of uniform properties on semiconductor devices
KR100643105B1 (ko) * 1998-05-06 2006-11-13 텍사스 인스트루먼츠 인코포레이티드 플립-칩 전자 디바이스를 언더필링하는 저응력 방법 및 장치
TW441006B (en) * 1998-05-18 2001-06-16 United Microelectronics Corp Method of forming inter-metal dielectric layer
US6350673B1 (en) * 1998-08-13 2002-02-26 Texas Instruments Incorporated Method for decreasing CHC degradation
US6384466B1 (en) * 1998-08-27 2002-05-07 Micron Technology, Inc. Multi-layer dielectric and method of forming same
KR20000024717A (ko) * 1998-10-01 2000-05-06 김영환 다공성 절연막 형성 방법
US6159842A (en) * 1999-01-11 2000-12-12 Taiwan Semiconductor Manufacturing Company Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections
US6211063B1 (en) 1999-05-25 2001-04-03 Taiwan Semiconductor Manufacturing Company Method to fabricate self-aligned dual damascene structures
US6358841B1 (en) 1999-08-23 2002-03-19 Taiwan Semiconductor Manufacturing Company Method of copper CMP on low dielectric constant HSQ material
US20050158666A1 (en) * 1999-10-15 2005-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple etch method for etching material etchable with oxygen containing plasma
US6372664B1 (en) 1999-10-15 2002-04-16 Taiwan Semiconductor Manufacturing Company Crack resistant multi-layer dielectric layer and method for formation thereof
US6403464B1 (en) 1999-11-03 2002-06-11 Taiwan Semiconductor Manufacturing Company Method to reduce the moisture content in an organic low dielectric constant material
US6531389B1 (en) 1999-12-20 2003-03-11 Taiwan Semiconductor Manufacturing Company Method for forming incompletely landed via with attenuated contact resistance
US6548901B1 (en) 2000-06-15 2003-04-15 International Business Machines Corporation Cu/low-k BEOL with nonconcurrent hybrid dielectric interface
US6642552B2 (en) * 2001-02-02 2003-11-04 Grail Semiconductor Inductive storage capacitor
US6759327B2 (en) * 2001-10-09 2004-07-06 Applied Materials Inc. Method of depositing low k barrier layers
US6838393B2 (en) * 2001-12-14 2005-01-04 Applied Materials, Inc. Method for producing semiconductor including forming a layer containing at least silicon carbide and forming a second layer containing at least silicon oxygen carbide
US6890850B2 (en) * 2001-12-14 2005-05-10 Applied Materials, Inc. Method of depositing dielectric materials in damascene applications
JP2003332423A (ja) * 2002-05-14 2003-11-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6925357B2 (en) * 2002-07-25 2005-08-02 Intouch Health, Inc. Medical tele-robotic system
US6727184B1 (en) * 2002-10-29 2004-04-27 Taiwan Semiconductor Manufacturing Co., Ltd Method for coating a thick spin-on-glass layer on a semiconductor structure
US6902440B2 (en) * 2003-10-21 2005-06-07 Freescale Semiconductor, Inc. Method of forming a low K dielectric in a semiconductor manufacturing process
US7030041B2 (en) * 2004-03-15 2006-04-18 Applied Materials Inc. Adhesion improvement for low k dielectrics
US20050233555A1 (en) * 2004-04-19 2005-10-20 Nagarajan Rajagopalan Adhesion improvement for low k dielectrics to conductive materials
US7229911B2 (en) * 2004-04-19 2007-06-12 Applied Materials, Inc. Adhesion improvement for low k dielectrics to conductive materials
US20050277302A1 (en) * 2004-05-28 2005-12-15 Nguyen Son V Advanced low dielectric constant barrier layers
US7288205B2 (en) * 2004-07-09 2007-10-30 Applied Materials, Inc. Hermetic low dielectric constant layer for barrier applications
KR100675895B1 (ko) * 2005-06-29 2007-02-02 주식회사 하이닉스반도체 반도체소자의 금속배선구조 및 그 제조방법
JP6726142B2 (ja) * 2017-08-28 2020-07-22 信越化学工業株式会社 有機膜形成用組成物、半導体装置製造用基板、有機膜の形成方法、パターン形成方法、及び重合体
JP6940335B2 (ja) 2017-08-30 2021-09-29 信越化学工業株式会社 有機膜形成用組成物、半導体装置製造用基板、有機膜の形成方法、パターン形成方法、及び重合体

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4756977A (en) * 1986-12-03 1988-07-12 Dow Corning Corporation Multilayer ceramics from hydrogen silsesquioxane

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