KR20000024717A - Forming method of porous insulating film - Google Patents
Forming method of porous insulating film Download PDFInfo
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- KR20000024717A KR20000024717A KR1019980041369A KR19980041369A KR20000024717A KR 20000024717 A KR20000024717 A KR 20000024717A KR 1019980041369 A KR1019980041369 A KR 1019980041369A KR 19980041369 A KR19980041369 A KR 19980041369A KR 20000024717 A KR20000024717 A KR 20000024717A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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Abstract
Description
본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 반도체 소자의 집적 공정에서 금속 배선간을 절연하기 위한 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method of forming an insulating film for insulating metal wirings in an integration process of semiconductor devices.
반도체 소자의 집적도가 증가됨에 따라 금속배선 사이의 간격이 좁아진다. 이에 따라 금속배선 사이의 기생 캐패시턴스(capacitance)가 증가하여 소자의 동작속도가 감소되는 문제점이 있다.As the degree of integration of semiconductor devices increases, the spacing between metal wirings becomes narrower. As a result, parasitic capacitances between metal wirings increase, thereby reducing the operating speed of the device.
첨부된 도면 도1은 고집적 반도체 소자에서 구동 속도에 영향을 미치는 저항 캐패시턴스 지연(이하, RC 지연이라 함) 요소를 설명하기 위한 모식도이다.1 is a schematic diagram illustrating a resistance capacitance delay (hereinafter referred to as RC delay) element that affects a driving speed in a highly integrated semiconductor device.
도1에 도시한 바와 같이 반도체 기판(도시하지 않음) 상에 제1 금속 패턴(M1), 제2 금속 패턴(M2), 제3 금속 패턴(M3) 각각을 동일한 절연막(I)을 사이에 두고 형성하였을 때, 수직으로 이웃하는 제1 금속 패턴(M1)과 제2 금속 패턴(M2), 제2 금속 패턴(M2)과 제3 금속 패턴(M3) 사이에는 수직 기생 캐패시턴스(Cv)가 발생하고, 수평으로 이웃하는 제2 금속 패턴(M2) 간에는 수평 기생 캐패시턴스(Ch)가 발생한다.As shown in FIG. 1, each of the first metal pattern M1, the second metal pattern M2, and the third metal pattern M3 is disposed on a semiconductor substrate (not shown) with the same insulating layer I therebetween. When formed, a vertical parasitic capacitance Cv is generated between the first neighboring first metal pattern M1 and the second metal pattern M2, the second metal pattern M2, and the third metal pattern M3. The horizontal parasitic capacitance Ch is generated between the second metal patterns M2 that are horizontally adjacent to each other.
이와 같이 소자를 연결하였을 때 구동 속도에 큰 영향을 미치는 RC 지연은 다음과 같은 관계에 있다.The RC delay, which greatly affects the driving speed when the devices are connected, has the following relationship.
먼저, 제2 금속 배선(M2)의 길이(도1에 나타나지 않음)가 L, 두께가 T 이고, 이웃하는 제2 배선층 간의 피치(pitch)가 P이며 비저항이 ρ일 때, 저항 R은 다음의 수학식1과 같은 관계에 있다. 상기 피치(P)는 제2 금속 배선(M2)의 폭(W)과 제2 금속 배선(M2) 간의 간격(S)의 합(P=W+S)이다.First, when the length (not shown in FIG. 1) of the second metal wiring M2 is L, the thickness is T, the pitch between neighboring second wiring layers is P and the specific resistance is ρ, the resistance R is It is in the same relationship as (1). The pitch P is the sum (P = W + S) of the interval S between the width W of the second metal wiring M2 and the second metal wiring M2.
제2 금속 패턴(M2)이 동일 간격(S)으로 배치될 때, 하나의 제2 금속 패턴(M2)과 그 양측의 제2 금속 패턴(M2) 사이에는 각각 수평 기생 캐패시턴스(Ch)가 발생한다. 또한, 제1 금속 패턴(M1)과 제2 금속 패턴(M2)의 간격과 제2 금속 패턴(M2)과 제3 금속 패턴(M3)의 간격이 동일할 때, 제1 금속 패턴(M1)과 제2 금속 패턴(M2) 사이와 제2 금속 패턴(M2)과 제3 금속 패턴(M3) 사이에는 각각 수직 기생 캐패시턴스(Cv)가 발생한다.When the second metal patterns M2 are disposed at equal intervals S, horizontal parasitic capacitances Ch are generated between one second metal pattern M2 and the second metal patterns M2 on both sides thereof. . In addition, when the interval between the first metal pattern M1 and the second metal pattern M2 and the interval between the second metal pattern M2 and the third metal pattern M3 are the same, the first metal pattern M1 Vertical parasitic capacitance Cv is generated between the second metal pattern M2 and between the second metal pattern M2 and the third metal pattern M3, respectively.
따라서, 하나의 제2 금속 패턴(M2)과 주변의 이웃하는 금속 패턴 사이의 총캐패시턴스(C)는 다음의 수학식2와 같은 관계에 있다.Therefore, the total capacitance C between one second metal pattern M2 and neighboring neighboring metal patterns has a relationship as shown in Equation 2 below.
수학식1 및 수학식2로부터 다음의 수학식3과 같이 RC를 얻는다.From Equations 1 and 2, RC is obtained as in Equation 3 below.
수학식3에서 ε0는 공기의 유전상수를 나타내고 k는 비례상수이다. 따라서 k·ε0는 절연막(I)의 유전율을 의미한다.In Equation 3, ε 0 represents the dielectric constant of air and k is the proportionality constant. Therefore, k ε 0 means the dielectric constant of the insulating film (I).
수학식3의 결과로부터 금속 패턴 간의 피치(P)가 작을수록 RC는 증가함을 알 수 있다. 즉, 집적도가 증가하면 금속 패턴 간의 피치가 작아지므로 RC는 증가한다. 또한, 비례상수 k가 클수록 RC는 증가한다. 따라서, 소자의 고집적화에 따라 필연적으로 수반되는 금속 패턴 간의 피치(P) 감소에 의해 RC가 증가되는 것을 억제하기 위해서는 유전율이 작은 절연막을 형성하여야 한다.It can be seen from the result of Equation 3 that the RC increases as the pitch P between metal patterns decreases. In other words, as the degree of integration increases, the pitch between metal patterns decreases, so that RC increases. In addition, RC increases as the proportional constant k increases. Therefore, in order to suppress the increase in RC due to the reduction of the pitch P between the metal patterns, which is inevitably accompanied by the high integration of the device, an insulating film having a small dielectric constant should be formed.
물질의 유전율은 유전율이 가장 낮은 공기(air)를 1로하여 상대적으로 나타낸다. 다양한 종류의 저 유전율 막에 대한 연구 결과, 절연막 내부에 빈 공간이 형성된 다공성 물질의 유전율이 비교적 낮음이 알려져 있다.The permittivity of a material is relatively represented by the air having the lowest permittivity (air) of 1. As a result of research on various kinds of low dielectric constant films, it is known that the dielectric constant of a porous material having an empty space inside an insulating film is relatively low.
이 다공성 물질은 졸(sol) 상태의 원물질(Precursor)을 큐어링(curing)하여 막 내부에 그 지름이 10 ㎚ 내지 30 ㎚인 기공들을 형성하거나, 원물질(Precursor)인 테트라에틸오르소실리케이트(tetra-ethyl-ortho silicate, 이하 TEOS라 함) 입자(particle) 사이에 약한 결합을 형성한 후 용매(solvent)를 급격히 빼내 다공성 구조가 그대로 유지되도록 하는 방법을 이용하여 형성한다. 원물질의 형성은 알콜류, 물 등의 용매, 액체상태인 TEOS 및 HCl, NH4OH 등의 촉매제 등을 가수분해 및 축합반응시켜 형성한다.This porous material cures sol-like precursor to form pores with a diameter of 10 nm to 30 nm in the membrane, or tetraethylorthosilicate as a precursor. (Tetra-ethyl-ortho silicate, hereinafter called TEOS) After forming a weak bond between the particles (particles) is formed by using a method to keep the porous structure as it is rapidly removed the solvent (solvent). Raw materials are formed by hydrolysis and condensation reaction of alcohols, solvents such as water, catalysts such as TEOS and HCl, NH 4 OH and the like in liquid state.
도2는 종래 기술에 따라 TEOS로 형성된 다공성 절연막의 단면도로서, TEOS에 의해 형성된 실리카(silica) 망목(network)(1)과 다공성 절연막 내부의 기공(porosity)(2)을 보이고 있다. 상기 실리카 망목(1)의 부피는 전체 구조의 30 % 정도이고 다공성 절연막의 나머지 부분은 기공(4)으로 구성된다. 또한, TEOS에 의해 형성된 실리카의 유전율은 공기 유전율의 4배 정도로 일반적인 실리콘 산화막(SiO2)과 유전율이 같다.FIG. 2 is a cross-sectional view of a porous insulating film formed of TEOS according to the prior art, and shows a silica network 1 formed by TEOS and a porosity 2 inside the porous insulating film. The silica mesh 1 has a volume of about 30% of the total structure and the rest of the porous insulating film is composed of pores (4). In addition, the dielectric constant of silica formed by TEOS is about the same as that of a general silicon oxide film (SiO 2 ), which is about four times the air dielectric constant.
다공성 물질의 전체 유전율은 기공(porosity)과 실리카의 부피비에 대한 유전율의 합으로 나타낼 수 있다. 기공은 공기로 채워져 있기 때문에 보다 저 유전율의 막을 만들기 위해서는 기공의 비율을 증가시키거나 실리카의 유전율을 낮추어야 한다. 그러나, 전자의 경우 기공의 비율이 증가하면 막의 구조적인 강도가 약해지기 때문에 기공의 비율을 증가시키는데 한계가 있다. 그러므로, 막의 구조적인 안정성을 유지하면서 저 유전율의 막을 형성하는데는 보다 낮은 유전율을 갖는 실리카를 이용하여 다공성 절연막을 형성하여야 한다.The total permittivity of the porous material can be expressed as the sum of the permittivity relative to the porosity and the volume ratio of silica. Because the pores are filled with air, to achieve a lower dielectric constant, the porosity must be increased or the dielectric constant of the silica lowered. However, in the case of the former, when the proportion of pores increases, the structural strength of the membrane is weakened, so there is a limit to increasing the proportion of pores. Therefore, to form a low dielectric constant film while maintaining the structural stability of the film, a porous insulating film must be formed using silica having a lower dielectric constant.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 구조적인 안정성을 유지하면서 보다 낮은 유전율을 갖는 다공성 절연막 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a porous insulating film forming method having a lower dielectric constant while maintaining structural stability.
도1은 구동 속도에 영향을 미치는 RC 지연 요소를 설명하기 위한 모식도,1 is a schematic diagram for explaining an RC delay element influencing driving speed;
도2는 종래 기술에 따라 TEOS로 형성된 다공성 절연막의 확대 단면도,2 is an enlarged cross-sectional view of a porous insulating film formed of TEOS according to the prior art;
도3은 실세스큐옥산(Silsesquioxane)의 단위구조,3 is a unit structure of silsesquioxane,
도4는 실록산(siloxane)의 단위구조,4 is a unit structure of siloxane,
도5는 본 발명에 따라 형성된 다공성 절연막의 단면도.5 is a cross-sectional view of a porous insulating film formed in accordance with the present invention.
* 도면의 주요부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
3: 실세스큐옥산, 실록산 또는 메톡실레이트 하이드로실라젠으로 형성된 실리카3: Silica formed of silsescuoxane, siloxane or methoxylate hydrosilagen
4: 기공4: pore
상기와 같은 목적을 달성하기 위한 본 발명은, 실세스큐옥산(Silsesquioxane)이 혼합된 졸(sol) 상태의 원물질(precursor)을 도포하는 단계; 및 용매의 삼중점을 넘는 조건에서 용매를 빼내는 초임계 건조(supercritical drying) 방법으로 다공성 절연막을 형성하는 단계를 포함하는 다공성 절연막 형성 방법을 제공한다.The present invention for achieving the above object, the step of applying a precursor of a sol (sol) state that the silsesquioxane (Silsesquioxane) is mixed; And it provides a porous insulating film forming method comprising the step of forming a porous insulating film by a supercritical drying method of removing the solvent in a condition exceeding the triple point of the solvent.
또한, 상기 목적을 달성하기 위한 본 발명은 실록산(Siloxane)이 혼합된 졸(sol) 상태의 원물질(precursor)을 도포하는 단계; 및 용매의 삼중점을 넘는 조건에서 용매를 빼내는 초임계 건조(supercritical drying) 방법으로 다공성 절연막을 형성하는 단계를 포함하는 다공성 절연막 형성 방법을 제공한다.In addition, the present invention for achieving the above object is a step of applying a precursor (sol) in the sol (sol) state in which siloxane (Siloxane) is mixed; And it provides a porous insulating film forming method comprising the step of forming a porous insulating film by a supercritical drying method of removing the solvent in a condition exceeding the triple point of the solvent.
또한, 상기 목적을 달성하기 위한 본 발명은 HxSiyO(y-1)C(y-1)의 조성을 갖는 메톡실레이트 하이드로실라젠(Methoylated hydrosilazane)이 혼합된 졸(sol) 상태의 원물질(precursor)을 도포하는 단계; 및 용매의 삼중점을 넘는 조건에서 용매를 빼내는 초임계 건조(supercritical drying) 방법으로 다공성 절연막을 형성하는 단계를 포함하는 다공성 절연막 형성 방법을 제공한다.In addition, the present invention for achieving the above object is a source of sol state in which methoxylated hydrosilazane (Methoylated hydrosilazane) having a composition of H x Si y O (y-1) C (y-1 ) is mixed Applying a precursor; And it provides a porous insulating film forming method comprising the step of forming a porous insulating film by a supercritical drying method of removing the solvent in a condition exceeding the triple point of the solvent.
본 발명은 실세스큐옥산(Silsesquioxane), 실록산(Siloxane) 또는 메톡실레이트 하이드로실라젠(Methoylated hydrosilazane)으로 원물질을 형성하고, 용매의 삼중점 이상의 조건에서 용매를 급격히 빼내는 초임계 건조(supercritical drying) 방법으로 다공성 절연막을 형성하는데 그 특징이 있다.The present invention is a supercritical drying method of forming a raw material with silsesquioxane, siloxane, or methoxylated hydrosilazane, and rapidly removing the solvent under conditions above the triple point of the solvent. This is characterized by forming a porous insulating film.
도3은 실세스큐옥산(Silsesquioxane)의 단위구조이다. 실세스큐옥산은 수소가 실리콘에 결합하고 있는 수소실세스큐옥산(Hydrogen-Silsesquioxane)과 메틸기(methyl group)가 실리콘에 결합하고 있는 메틸실세스큐옥산(Methyl-Silsesquioxane)이 있다. 수소실세스큐옥산의 유전율은 공기의 약 3배이고, 메틸실세스큐옥산의 유전율은 공기의 약 2.7 배이다.3 is a unit structure of silsesquioxane. Silsescuoxanes include hydrogen-silsesquioxanes in which hydrogen is bonded to silicon, and methyl-silsesquioxanes in which methyl group is bonded to silicon. The dielectric constant of hydrogen silsescuoxane is about three times that of air, and the dielectric constant of methylsilsescuoxane is about 2.7 times that of air.
도4는 유전율이 공기의 약 3배로서 SiO2보다 저 유전율을 갖는 실록산(siloxane)의 단위구조를 보이고 있다.4 shows a unit structure of siloxane having a dielectric constant of about three times that of air and having a lower dielectric constant than that of SiO 2 .
이하, 실세스큐옥산, 실록산 또는 메톡실레이트 하이드로실라젠을 이용한 다공성 절연막 형성 방법을 설명한다.Hereinafter, a method of forming a porous insulating film using silsescuoxane, siloxane, or methoxylate hydrosilagen will be described.
먼저, 졸(sol) 상태의 원물질(precursor)을 도포한다.First, a precursor is applied in a sol state.
상기 원물질로는 (HSiO1.5)x의 조성을 갖는 수소실세스큐옥산이 혼합된 것을 사용한다. 수소실세스큐옥산으로는 유전율이 공기의 약 3.2배인 사다리 구조의 수소실세스큐옥산 또는 유전율이 공기의 3.0배인 케이지(cage) 구조의 수소실세스큐옥산을 사용한다. 사다리 구조 수소실세스큐옥산의 용매는 이소프로필알콜(IPA) 또는 프로필렌글리콜모노메틸에테르(PGME)이고 용질의 고용체 함량(solid content)이 5 % 내지 30 % 분자량 비로 합성된 것을 사용한다.As the raw material, a mixture of hydrogen silsescuoxane having a composition of (HSiO 1.5 ) x is used. As the hydrogen silsescuoxane, a hydrogen silsescuoxane having a dielectric constant of about 3.2 times that of air or a hydrogen silsescuoxane having a cage structure having a dielectric constant of 3.0 times that of air is used. The solvent of the ladder structure hydrogen silsescuoxane is isopropyl alcohol (IPA) or propylene glycol monomethyl ether (PGME), and a solid content of the solute is synthesized at a molecular weight ratio of 5% to 30%.
또는, 상기 원물질로 유전율이 공기의 약 2.7배이며 (CH3SiO1.5)x의 조성을 갖는 메틸실세스큐옥산을 혼합하여 사용한다.Alternatively, a mixture of methylsilsescuoxane having a composition of (CH 3 SiO 1.5 ) x having a dielectric constant of about 2.7 times that of air is used as the raw material.
상기 원물질로 유전율이 공기의 약 2.9배이며 (CH3)xSiO(2-x/2)의 조성을 갖는 메틸실록산 또는 유전율이 공기의 약 3.2배이며 HxSiO(2-x/2)의 조성을 갖는 수소실록산을 사용한다.Methylsiloxane having a dielectric constant of about 2.9 times that of air and having a composition of (CH 3 ) x SiO (2-x / 2) , or a dielectric constant of about 3.2 times that of air, of H x SiO (2-x / 2) Hydrogensiloxane having a composition is used.
상기 원물질은 유전율이 공기의 약 3.5배이며 HxSiyO(y-1)C(y-1)의 조성을 갖는 메톡실레이트하이드로실라젠을 혼합하여 사용하기도 한다.The raw material may be used by mixing methoxylate hydrosilagen having a dielectric constant of about 3.5 times that of air and having a composition of H x Si y O (y-1) C (y-1) .
이어서, 용매(solvent)를 건조시켜 실리카 망목을 형성한다. 이 과정에서 용매의 건조 방법에 따라 다공성 절연막 내부의 실리카 망목과 기공구조가 변하게 된다. 즉, SOG막의 큐어링(Curing) 방법과 같은 열처리 공정으로 용매를 휘발시키면 수축으로 인해 치밀한 구조를 갖는 막이 형성되어 원하는 저 유전율의 다공성 절연막 특성을 얻지 못한다. 따라서, 용매의 삼중점 이상의 조건에서 용매를 급격히 빼내는 초임계 건조(supercritical drying) 방법으로 다공성 절연막을 형성한다. 이어서, 필요에 따라 열처리(annealing)를 실시하거나 표면을 화학처리(chemical treatment)한다.The solvent is then dried to form a silica mesh. In this process, the silica mesh and the pore structure of the porous insulating film are changed according to the drying method of the solvent. That is, when the solvent is volatilized by a heat treatment process such as a curing method of the SOG film, a film having a dense structure is formed due to shrinkage, thereby failing to obtain the desired low dielectric constant porous insulating film. Therefore, the porous insulating film is formed by a supercritical drying method in which the solvent is rapidly drawn out under the triple point condition of the solvent. Subsequently, annealing or chemical treatment of the surface is carried out as necessary.
도5는 전술한 바와 같은 방법으로 형성된 다공성 절연막의 단면도로서, 실세스큐옥산, 실록산 또는 메톡실레이트 하이드로실라젠으로 형성된 실리카(3)와 기공(4)으로 이루어지는 다공성 절연막을 보이고 있다.Fig. 5 is a cross-sectional view of the porous insulating film formed by the method described above, showing a porous insulating film made of silica 3 and pores 4 formed of silsescuoxane, siloxane, or methoxylate hydrosilagen.
상기와 같이 이루어지는 본 발명은 기존의 TEOS에 의해 형성되는 다공성 절연막보다 저유전 특성이 우수하여 소자의 RC 지연을 감소시켜 구동속도 등을 증가시킬 수 있고, 전력소모를 감소시킬 수 있어 소자의 특성을 크게 향상시킬 수 있다.The present invention made as described above is excellent in low dielectric properties than the porous insulating film formed by the TEOS can reduce the RC delay of the device to increase the driving speed, etc., can reduce the power consumption to improve the characteristics of the device It can greatly improve.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
Claims (7)
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| US5393712A (en) * | 1993-06-28 | 1995-02-28 | Lsi Logic Corporation | Process for forming low dielectric constant insulation layer on integrated circuit structure |
| JPH08162450A (en) * | 1994-05-20 | 1996-06-21 | Texas Instr Inc <Ti> | Small-permittivity material applied to electronic device |
| US5607773A (en) * | 1994-12-20 | 1997-03-04 | Texas Instruments Incorporated | Method of forming a multilevel dielectric |
| JPH1074837A (en) * | 1996-08-30 | 1998-03-17 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5393712A (en) * | 1993-06-28 | 1995-02-28 | Lsi Logic Corporation | Process for forming low dielectric constant insulation layer on integrated circuit structure |
| JPH08162450A (en) * | 1994-05-20 | 1996-06-21 | Texas Instr Inc <Ti> | Small-permittivity material applied to electronic device |
| US5607773A (en) * | 1994-12-20 | 1997-03-04 | Texas Instruments Incorporated | Method of forming a multilevel dielectric |
| JPH1074837A (en) * | 1996-08-30 | 1998-03-17 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
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