KR101783992B1 - Digital image transmitting/receiving system based on ethernet - Google Patents

Abstract

The present invention discloses an Ethernet-based digital image transmission / reception system.
An Ethernet-based digital image transmission / reception system of the present invention converts an analog image signal input from an image sensor into a digital signal of a luminance signal and a color signal, and multiplexes the analog image signal to generate a multiplexed signal having synchronization information. Or more, into an Ethernet transmission format and transmits the Ethernet transmission format; And a multiplexer for multiplexing the multiplexed signal and the multiplexed signal, separating a luminance signal and a color signal from the multiplexed signal, storing the separated luminance signal and the color signal, A digital image receiving apparatus for synchronizing and outputting images; And an Ethernet cable connecting the digital video transmitting apparatus and the digital video receiving apparatus to transmit the packet.

Description

Technical Field [0001] The present invention relates to a digital image transmitting / receiving system based on Ethernet,

The present invention relates to an Ethernet-based digital image transmission / reception system.

13 is a block diagram schematically showing a conventional video transmission / reception system.

Referring to FIG. 13, the video transmission / reception system 1 is a system using HD-SDI (HD-Serial Digital Interface) transmission technology.

The image transmitting apparatus 2 converts the electrical analog signal from the image sensor 11 into a parallel signal of the luminance signal Y and the color signal C in the image signal processing section 12, . At this time, when the encoder 13 is an HD-SDI encoder, the encoder 13 can convert a parallel signal into a serial signal of a single bit according to the HD-SDI standard. The serial signal is scrambled to remove the DC component from the scrambler 14 and transmitted to the coaxial cable 4 which is a serial line through the driver 14 for matching with the cable impedance.

The image receiving apparatus 3 restores the high frequency loss of the video signal received from the coaxial cable 4 through the equalizer (EQ) 16, descrambles the image signal in the descrambler 17, 18 converts the serial signal into a parallel signal. At this time, the decoder 18 can perform signal conversion according to the HD-SDI standard according to the encoder standard of the image transmitting apparatus 2. The parallel signal can be digitally processed in the control unit 19, and then transmitted through a digital compression, recording, or network.

The present invention provides a digital image transmission / reception system capable of realizing long distance transmission of a high image quality digital image signal at low cost.

According to another aspect of the present invention, there is provided an apparatus for transmitting an Ethernet-based digital image, comprising: a signal processor for converting an analog image signal input from an image sensor into a digital signal of a luminance signal and a color signal; A control unit for multiplexing the digitally converted luminance signal and the color signal and outputting a multiplexed signal having synchronization information; A medium access control (MAC) module for generating a packet including at least one of the multiplexed signals; And a physical (PHY) module that converts the packet into an Ethernet transmission format and transmits the packet through an Ethernet cable.

The control unit may include: a multiplexer for multiplexing the digital signal and the color signal; And a first memory for temporarily storing the multiplex signal, wherein the temporarily stored multiplex signal can be output by the MAC module in accordance with a transmission clock of the PHY module.

The transmitting apparatus may further include a compressing unit compressing the digitally converted luminance signal and the color signal when the bandwidth of the multiplex signal exceeds the Ethernet transmission bandwidth according to the image resolution. The compressor may utilize lossless compression, or at least one DPCM compression and subsampling rate control compression.

The MAC module may insert the line number of the multiplex signal into the packet.

Video resolution information may be embedded in the multiplexed signal or packet.

The control unit may further include a second memory for temporarily storing a control signal received according to a transmission clock of the PHY module via the Ethernet cable, and outputting the control signal according to an internal clock.

The Ethernet cable may be an unshielded twisted pair cable.

An Ethernet-based digital image receiving apparatus according to a preferred embodiment of the present invention is a device for receiving a packet including one or more multiplexed signals having synchronization information and a digital signal of a luminance signal and a color signal multiplexed through an Ethernet cable PHY) module; A medium access control (MAC) module for extracting the multiplexed signal from the packet; And a controller for separating the luminance signal and the color signal from the multiplexed signal, storing the separated luminance signal and the color signal, and synchronizing and outputting the signals based on the synchronization information.

Wherein the control unit comprises: a third memory for temporarily storing the multiplexed signal input in accordance with a reception clock of the PHY module and outputting the multiplexed signal according to an internal clock; A demultiplexer for separating the multiplexed signal into a luminance signal and a color signal; A frame memory for storing the separated luminance signal and the color signal in a line unit; And a synchronization signal generator for generating a vertical synchronization signal and a horizontal synchronization signal based on the synchronization information so that the brightness signal and the color signal stored in the frame memory are synchronized with each other and outputted.

The demultiplexer may demultiplex the control signal included in the multiplex signal.

The frame memory may store the luminance signal and the color signal in the corresponding line area based on the line number included in the packet.

The control unit may further include a fourth memory for temporarily storing an externally input control signal and outputting the control signal according to the received clock.

The receiving apparatus may further include a decompression unit decompressing the decompressed luminance signal and the chrominance signal when the chrominance signal is a compressed signal.

The Ethernet cable may be an unshielded twisted pair cable.

In the Ethernet-based digital image transmission / reception system according to the preferred embodiment of the present invention, an analog image signal input from an image sensor is converted into a digital signal of a luminance signal and a color signal and then multiplexed to generate a multiplexed signal having synchronization information A digital video transmission apparatus for converting a packet including at least one multiplexed signal into an Ethernet transmission format and transmitting the packet; And a multiplexer for multiplexing the multiplexed signal and the multiplexed signal, separating a luminance signal and a color signal from the multiplexed signal, storing the separated luminance signal and the color signal, A digital image receiving apparatus for synchronizing and outputting images; And an Ethernet cable connecting the digital video transmitting apparatus and the digital video receiving apparatus to transmit the packet.

The digital video transmission apparatus temporarily stores the multiplexed signal and outputs the multiplexed signal according to a transmission clock of the packet transmission module. The digital video reception apparatus temporarily stores the multiplexed signal input in accordance with the reception clock of the packet reception module And outputs the luminance signal and the color signal separated from the multiplexed signal on a line-by-line basis, and synchronizes and outputs the signals based on the synchronization information.

And a compression unit for compressing the digitally converted luminance signal and the color signal when the bandwidth of the multiplexed signal exceeds the Ethernet transmission bandwidth according to the resolution of the image, And a decompression unit for decompressing the compressed luminance signal and the color signal to be output in synchronization with each other based on the synchronization information.

The digital image transmitting apparatus inserts the line number of the multiplex signal into the packet, and the digital image receiving apparatus can store the separated luminance signal and the color signal in a frame memory on a line-by-line basis based on the line number.

The Ethernet cable may be an unshielded twisted pair cable.

The present invention can realize long distance transmission and reception of a high quality digital video signal at low cost.

1 is a block diagram illustrating an Ethernet-based digital image transmission / reception system according to an embodiment of the present invention.
2 is a diagram illustrating digitally converted Y signals and C signals according to an embodiment of the present invention.
Fig. 3 shows the code standards of Figs. 2 (a) and 2 (b).
4A and 4B show a multiplexed signal standard according to an embodiment of the present invention.
4C shows a timing specification of a multiplexed signal according to an embodiment of the present invention.
5A to 5D are diagrams showing the structure of a packet according to an embodiment of the present invention.
6 is a flowchart illustrating a packet generation method according to an embodiment of the present invention.
FIG. 7 is a block diagram schematically illustrating the configuration of a control unit of a video transmission apparatus according to an embodiment of the present invention.
8 is a block diagram schematically showing a configuration of a control unit of the image receiving apparatus according to an embodiment of the present invention.
9 is a flowchart illustrating a method of transmitting an image in an Ethernet-based digital image transmission apparatus according to an embodiment of the present invention.
10 is a flowchart illustrating a method of receiving and processing an image in an Ethernet-based digital image receiving apparatus according to an embodiment of the present invention.
11 is a block diagram illustrating a digital image data transmission / reception system according to another embodiment of the present invention.
12 is a block diagram schematically showing a digital image data transmission apparatus according to another embodiment of the present invention.
13 is a block diagram schematically showing a conventional video transmission / reception system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

The HD-SDI transmission system converts parallel video signals (Y / C signals) and audio signals into a single bit serial signal according to the HD-SDI standard and transmits it. At this time, since the frequency band reaches about 1.5 Ghz at a low frequency, an expensive coaxial cable having a high frequency attenuation characteristic is used. As a result, there is a problem that the construction is difficult such as being affected by the bending or pressing of the cable, the cost is high, and information can be transmitted only in one direction.

Also, in the case of a system for transmitting digital video / audio information and a control signal in parallel, a plurality of signal lines for connecting the transmitter and the receiver are required.

The present invention relates to a digital image transmission / reception system and method capable of realizing a long distance transmission of a video signal at a low cost by using an unshielded twisted pair (UTP) cable, which is a simple and widely used standard Ethernet cable, .

1 is a block diagram illustrating an Ethernet-based digital image transmission / reception system according to an embodiment of the present invention.

The digital video transmitting / receiving system 10 of the present invention applies a standard Ethernet transmission technology to the transmission of a digital video signal. To this end, the transmitting side multiplexes video signals, which are continuous parallel digital signals, into packet form, and the receiving side receives video signals on a packet basis. However, since Ethernet transmits data asynchronously, there is a difference between the transmitting clock and the receiving clock between the transmitting side and the receiving side which are connected to each other. Accordingly, there is a jitter between the packet and the packet although it is synchronized with the clock in one packet. Therefore, according to the present invention, a stable reference line synchronizing signal is generated according to the screen configuration, and the synchronization is ensured for each video line to be stabilized.

1, an Ethernet-based digital image transmission / reception system 10 includes an image transmission device 20, a video reception device 30, and an Ethernet (digital-to-analog) converter 30 for transmitting / receiving data between the image transmission device 20 and the image reception device 30. [ And a cable 40.

The Ethernet-based digital video transmitting / receiving system 10 of the present embodiment uses an Ethernet cable 40 instead of an expensive coaxial cable as a transmission medium. The Ethernet cable 40 supports a full duplex mode capable of bidirectional communication. An unshielded twisted pair (UTP) cable can be used as the Ethernet cable 40.

Hereinafter, an example in which 1000Base-T PHY technology used for standard Ethernet transmission is introduced as a transmission medium will be described. 1000BASE-T PHY technology is a technology standard for the next generation physical layer supporting a transmission speed of 1Gbps up to 100m using copper wire. 1000BASE-T PHY technology can reliably transmit information at 1Gbps at low cost using unshielded twisted pair (UTP) cable. Unshielded twisted pair cable is UTP Cat. 5, and Cat6. The present embodiment configures a video signal transmission format to conform to the Gigabit Ethernet transmission standard in order to transmit a 1 Gbps video signal through an unshielded twisted pair cable having a maximum transmission capacity of 1 Gbps.

The image transmitting apparatus 20 may include various digital image processing apparatuses such as a surveillance camera and a robot for performing digital image processing. The image transmitting apparatus 20 includes an image sensor 21, a video signal processing unit 22, a compression unit 23, a control unit 24, a MAC module 25, and a PHY module 26.

The image sensor 21 is a photoelectric conversion unit including an image pickup device such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal-Oxide-Semiconductor). The image sensor 21 converts the light from the optical portion into an electrical analog signal.

An image signal processor (ISP) 22 converts an electrical analog signal converted by the image sensor 21 into a luminance signal (hereinafter referred to as a 'Y signal') and a color signal (hereinafter referred to as a 'C signal' Into a parallel digital video signal. The digitally converted Y signal and C signal have synchronization information. Then, the video signal processing section 22 can receive and process the control signal input from the control section 24. The control signal may include a video signal.

2 is a diagram illustrating digitally converted Y signals and C signals according to an embodiment of the present invention.

Referring to FIG. 2A, a Y signal digitally converted into a predetermined bit is divided into a Start of Active Video (SAV), a Y signal (Active Y), an End of Active Video (EAV), and a blanking interval. 2 (a) shows a Y signal digitally converted to 10 bits.

Referring to FIG. 2B, a C signal digitally converted into a predetermined bit is divided into a Start of Active Video (SAV), a C signal (Active Cr / Cb), an End of Active Video (EAV), and a blanking interval do. In Fig. 2 (b), a C signal digitally converted to 10 bits is shown.

Referring to FIGS. 2 (a) and 2 (b), the digitally converted Y signal and the C signal include digital screen synchronizing signals SAV and EAV as synchronization information at the horizontal start and end positions, respectively. SAV is a code indicating the start of horizontal synchronization, and EAV is a code indicating the end of horizontal synchronization.

Fig. 3 shows the code standards of Figs. 2 (a) and 2 (b). Referring to FIG. 3 together, SAV and EAV are composed of 4 words, and three of the four words (3FF, 000, 000) are fixed preambles and the fourth word (XYZ) Is composed of horizontal sync and vertical sync, and status bits of F, V and H indicating field / frame information, and represents information of a current video signal.

F is field information, F is 0 when the image display system is a progressive mode, 0 is an interlaced mode, F is an even field if F is 0, and odd field when F is 1 .

V denotes a vertical blanking period, that is, a field / frame blanking interval. When V is 0, it indicates an active interval (i.e., a multiplexed signal interval).

H denotes a horizontal blanking interval, that is, a line blanking interval. When H is 0, it indicates an active interval (i.e., a multiplexed signal interval), and when H is 1, it indicates a horizontal blanking interval.

The values of the protection bits, P0, P1, P2 and P3, are determined by the values of F, V and H.

The compression unit 23 compresses the video signal when the data amount of the video signal to be transmitted exceeds the maximum transmission capacity of the Gigabit Ethernet according to the video resolution for Gigabit Ethernet transmission. That is, the compression unit 23 can be selectively used according to the image resolution, that is, the number of pixels of the image sensor 21. [ For example, in a Gigabit Ethernet having a maximum transmission capacity of 1 Gbits / s, a video signal is compressed when the amount of data of a video signal to be transmitted exceeds 1 Gbits / s.

The compression unit 23 can compress the image signal by at least one of lossless compression, DPCM compression, and subsampling ratio control. This compression is simpler than compression / coding like JPEC / MPEC and has the advantage of efficiently transmitting full-HD images while minimizing signal loss (that is, without affecting image quality). In addition, compression by DPCM compression and sub-sampling rate control can contribute to cost reduction by simpler compression method than lossless compression.

For example, in the case of a SD image, 10 bits are allocated to the Y signal and 10 bits are allocated to the C signal, and the structure has a resolution of 720x480, a frame rate of 30 fps, and a sampling frequency of 13.5 Mhz. Accordingly, when the video signal (Y signal and C signal) is multiplexed to 8 bits, it has a size of 270 Mbits / s, so that it can be sufficiently processed in the transmission band of 1 Gbits / s, I do not.

On the other hand, in the case of a full-HD image, 10 bits are allocated to the Y signal and 10 bits are allocated to the C signal, and a 1920x1080 resolution, 30 fps frame rate structure and a sampling frequency of 74.5 Mhz are provided. Accordingly, when the video signal (Y signal and C signal) is multiplexed to 8 bits, it has a size of 1.4 Gbits / s, which exceeds the transmission bandwidth of 1 Gbits / s. Therefore, the compression unit 23 needs to compress the video signal.

As an example of the compression, the compression unit 23 can be implemented as a lossless codec that reduces the bandwidth at a level that can not be visually influenced, thereby compressing the video signal. Accordingly, the bandwidth of the signal to be transmitted can be reduced to 1/2 to 1/6.

As another example, the compression unit 23 may compress the video signal by DPCM (Differential Pulse Code Modulation) compression, which codes the difference value between the Y signal and the C signal. Accordingly, by reducing the bits allocated to the Y signal and the C signal to 6 bits, the bandwidth of the signal to be transmitted can be reduced. At this time, the subsampling ratio of the Y signal and the C signal is maintained at 4: 2: 2.

As another example, the compression unit 23 can compress a video signal by performing a subsampling ratio of the Y signal and the C signal at 4: 1: 1. Accordingly, the number of bits allocated to the C signal is reduced to 4 bits, compared to the 8 bits allocated to the Y signal, thereby reducing the bandwidth of the signal to be transmitted.

As another example, the compression unit 23 may compress a video signal by performing DPCM (Differential Pulse Code Modulation) compression and a subsampling ratio of the Y signal and the C signal at 4: 1: 1. Accordingly, the bit to be allocated to the Y signal is reduced to 6 bits, and the bit allocated to the C signal is reduced to 3 bits, thereby reducing the bandwidth of the signal to be transmitted.

An image standard such as image resolution information (SD class, full-HD class, etc.) can be inserted into a packet when a multiplex signal or a packet is generated at the time of multiplexing a video signal to be described later.

The control unit 24 multiplexes the Y signal and the C signal corresponding to one line (hereinafter, referred to as 'video line') constituting an image. Then, the control unit 23 can multiplex the control signal with the video signal of the Y signal and the C signal. The control signal may be a voice signal from the voice input device. The multiplexed signal has synchronization information. The control unit 24 temporarily stores a digital signal multiplexed on a video line basis (hereinafter, referred to as a multiplex signal), and outputs the multiplexed signal in synchronization with the transmission clock of the PHY module 25. The control unit 24 may include the resolution information in the multiplex signal.

4A and 4B show a multiplexed signal standard according to an embodiment of the present invention. The multiplexed signal standard is classified into Start of Active Video (SAV), Multiplexed Signal (Active Y / Cr / Cb), End of Active Video (EAV), and Blanking Video. 4A and 4B show examples of multiplexed signals obtained by multiplexing 10-bit Y signals and C signals into 8 bits, respectively. When the Y signal and the C signal are compressed, the multiplexing bit may be different. The multiplexed signal also includes digital screen synchronization signals SAV and EAV at the start and end positions of each horizontal (video line) similarly to the Y and C signals. SAV indicates the start of horizontal synchronization and EAV indicates the end of horizontal synchronization. As shown in FIG. 4B, the multiplexed signal may include a video line number (LN) after EAV.

The code standards of FIGS. 4A and 4B can be applied to the code standards of FIG.

4C shows a timing specification of a multiplexed signal according to an embodiment of the present invention. It is possible to represent the corresponding position of the timing specification defined in FIG. 4C through the bit allocation details of the SAV and the fourth word of the EAV, so that the spatial layout of the field / frame can be expressed. The ancillary data may include a voice signal and a control signal other than the video signal. 4C shows an example in which the video line number LN is inserted. In the case where the video line number LN is not inserted, the video line number LN may be omitted in FIG. 4C.

Referring to FIG. 4C, F of all lines in the progressive scanning method is 0, F of the even field lines is 0, and F of the odd field lines is 1 in the interlaced scanning method. H repeats 0 and 1 for every line (row), V of each line of the multiplexed signal is 1, and V of the blanking interval and the auxiliary data interval is zero.

Referring again to FIG. 1, the MAC module 24 is a medium access control (MAC) layer module, and generates a packet including one or more multiplexed signals. The MAC module 24 may insert the line number of the multiplex signal into the packet.

5A to 5D are diagrams showing the structure of a packet according to an embodiment of the present invention.

5A and 5B are diagrams showing the structure of a packet including one multiplex signal. Referring to FIG. 5A, the MAC module 24 may insert a single multiplex signal into a data area of a packet to include one video line information in one packet. A header and a tailer are inserted before and after the multiplex signal, respectively. The header may indicate a preamble, a start of frame delimiter (SFD), a destination address, a source address, an upper layer protocol type, and the like. The Taylor may indicate an FCS (Frame Check Sequence) for error detection of the frame. The header included in the packet of the present invention and the information inserted into the tailer are not particularly limited. For example, it is possible to additionally include information other than the header and the Taylor example described above, and the destination and destination addresses in the header may be omitted when the transmitting apparatus and the receiving apparatus are connected in a one-to-one correspondence with a single cable.

5B differs from the packet of FIG. 5A in that a video line number (LN) is inserted into a packet, and other configurations are the same as those described above, and thus a detailed description thereof will be omitted. Referring to FIG. 5B, the MAC module 24 inserts a multiplex signal into the data area Data of the packet and inserts the video line number LN at the end of the multiplex signal.

5C and 5D are diagrams showing the structure of a packet including a plurality of multiplexed signals. Referring to FIG. 5C, the MAC module 24 may include a plurality of video line information in one packet by inserting two or more multiplexed signals into a data area Data of the packet. The number of multiplexed signals can be determined according to the size (amount of data) of the multiplexed signal and the transmission band of the transmission medium. A header and a tailer are inserted before and after the multiplex signal, respectively. The header may indicate a preamble, a start of frame delimiter (SFD), a destination address, a source address, an upper layer protocol type, and the number of multiplexed signals. The Taylor may indicate an FCS (Frame Check Sequence) for error detection of the frame. The header included in the packet of the present invention and the information inserted into the tailer are not particularly limited. For example, it is possible to additionally include information other than the header and the Taylor example described above, and the destination and destination addresses in the header may be omitted when the transmitting apparatus and the receiving apparatus are connected in a one-to-one correspondence with a single cable.

5D is different from the packet of FIG. 5C in that a video line number (LN) is inserted into a packet, and other configurations are the same as those described above, and thus a detailed description thereof will be omitted. Referring to FIG. 5D, the MAC module 24 may insert two or more multiplexed signals into a data area Data of a packet, and insert a video line number (LN) at the end of each multiplexed signal.

6 is a flowchart illustrating a packet generation method according to an embodiment of the present invention.

Referring to FIG. 6, the MAC module 24 determines whether an SAV code is detected in the multiplexed signal (S401). If the SAV code is detected, the MAC module 24 starts packet generation (S402).

The MAC module 24 monitors the frame change and determines whether the multiplexed signal is a new frame (S403). The MAC module 24 can determine whether the frame is a new frame based on the synchronization information of the multiplexed signal.

If it is determined that the video line number is inserted, the MAC module 24 initializes the video line number (S404). If it is determined that the video line number is not a new frame, the MAC module 24 increments the video line number (S405).

The MAC module 24 determines whether or not the EAV code is detected (S406). If the EAV code is detected, the MAC module 24 generates a header and a tailer having necessary information before and after the multiplex signal to complete packet generation. When the MAC module 24 is set to insert the video line number, the video line number is inserted after the EAV code (S407), and a header and a tailer having necessary information before and after the multiplex signal are generated to complete the packet generation.

When generating a packet including a predetermined number of multiplexed signals, the MAC module 24 may repeat steps S405 to S407 for a subsequent multiplexed signal.

Referring again to FIG. 1, the PHY module 25 is a Giga-PHY layer module, which converts a packet input from the MAC module 24 into an Ethernet transmission format and transmits the Ethernet transmission format over the Ethernet cable 40.

PHY module 25 may convert the packet into a Giga Ethernet standard signal, which is an Ethernet transmission format, according to the Gigabit Ethernet protocol and transmit it via an Ethernet cable (for example, Cat 5e Cable) 40. For example, when a 1000BASE-T PHY technique for simultaneously transmitting a 4D 5-PAM (4-Dimensional 5-level Pulse Amplitude Modulation) signal of 125Mbaud in both directions using four pairs of copper lines is applied, Converts the packet information, that is, an 8-bit multiplexed signal synchronized to a 125 MHz clock, into a 4D 5-PAM signal of 125 Mbaud using a 4D TCM (Trellis Coded Modulation) modulation technique. PHY module 25 can transmit 1 Gbps data in a full duplex mode through an Ethernet cable 40 composed of four pairs of copper lines.

The video signal processing unit 22, the control unit 24, the MAC module 25 and the PHY module 26 can perform both a conversion function for transmitting an Ethernet-based signal and an inverse conversion function for a signal received on an Ethernet basis . Accordingly, the video transmitting apparatus 20 can reverse-convert the audio signal and the control signal received from the video receiving apparatus 30 through the PHY module 26, the MAC module 25, and the control section 24. The control signal received through the Ethernet cable 40 includes a linear distortion generated by the frequency loss characteristic of the copper line, an echo signal echoed back from the hybrid circuit, and a Near-end Cross (NEXT) Talk and a far-end cross talk based on a remote transmission signal may be added. Thus, the inverse-transformed control signal can be signal processed, for example, by an equalizer and a NEXT canceller and an echo canceller. The setting and operation of the image transmitting apparatus 20 can be controlled by the inverse-converted control signal.

The video receiving apparatus 30 may include a digital video recorder (DVR), a network video recorder (NVR), a computer, and the like which are widely used as a closed-circuit TV (CCTV) system. The video receiving apparatus 30 includes a PHY module 31, a MAC module 32, a control section 33, and a restoration section 34. [

The PHY module 31 is a Giga-PHY layer module that converts a signal input through the Ethernet cable 40 into an Ethernet transmission format into a promised packet format. The PHY module 31 converts the input signal into a packet form in the reverse of the process of converting the packet into the Ethernet transmission format in the PHY module 25 of the image transmitting apparatus 20. [ A packet has synchronization information and includes at least one multiplexed signal in which a luminance signal and a digital signal of a color signal are multiplexed.

The MAC module 32 is a medium access control (MAC) layer module, and extracts a multiplex signal contained in a packet. The multiplexed signal includes a video signal (Y signal and C signal) and a control signal. The control signal may comprise a voice signal. The MAC module 32 performs error checking on the received packet, and can recover or discard the error of the packet in which the error occurred.

The control unit 33 demultiplexes the multiplex signal to separate the Y signal, the C signal, and the control signal, stores the Y signal and the C signal in the frame memory, and synchronizes and outputs the Y signal and the C signal based on the synchronization information of the multiplex signal .

The decompression unit 34 is a means for decompressing the video signal (Y signal and C signal) and the control signal, and may be provided or used as necessary. The decompression unit 34 can decompress the video signal and the control signal when the compressed signal is a signal (for example, a signal compressed by lossless compression, DPCM compression, and / or subsampling ratio control).

The PHY module 31, the MAC module 32, and the control unit 33 can perform both an inverse conversion function of an Ethernet-based signal and a conversion function for transmission of an Ethernet-based signal. Accordingly, the image receiving apparatus 30 can convert a voice signal and a control signal to be transmitted to the image transmitting apparatus 20 through the control unit 33, the MAC module 32, and the PHY module 31. The image receiving apparatus 30 can remotely control the setting and operation of the image transmitting apparatus 20 by a voice signal and / or a control signal.

The video and audio signals received through the Ethernet cable 40 include linear distortion generated by the frequency loss characteristic of the copper line, echo signals returned from the hybrid circuit, and NEXT Near-end cross talk) and a far-end cross talk (an interference signal based on a long-distance transmission signal) may be added. Accordingly, the video receiving apparatus 30 can process the converted video and audio signals by, for example, an equalizer, a NEXT eliminator, and an echo canceller.

Although not shown, the image receiving apparatus 30 may further include a network communication unit, a mux, a codec, and a storage device, which are controlled by separate control means. The image receiving apparatus 30 can digitally compress a video signal and a voice signal through a mux and a codec, store the same in a storage device, and reproduce the same. Also, the video receiving apparatus 30 can transmit and receive video and audio signals to / from an external terminal through a network communication unit.

FIG. 7 is a block diagram schematically illustrating the configuration of a control unit of a video transmission apparatus according to an embodiment of the present invention.

The control unit 200 of FIG. 7 can function as the control unit 24 of the video transmission device 20 of FIG. 1 by software and / or hardware configuration. Referring to FIG. 6, the controller 200 may include a first transmission controller 210 and a first reception controller 260.

The first transmission control unit 210 receives the digital video signals (Y signal and C signal) including the Y signal and the C signal, and the audio signal AUX (audio signal or control signal And outputs it to the MAC module 24. At this time, the video signal (Y signal and C signal) may be a signal compressed to fit the transmission band of the transmission medium. The voice signal may be a signal compressed by ADPCM (Adaptive Differential Pulse Code Modulation) method. The first transmission control unit 210 may include a multiplexer 220 and a first memory 230.

The multiplexer 220 multiplexes the digital video signal (Y signal and C signal) and the audio signal AUX_Tx according to the pixel clock (Pixel_CLK), and outputs the multiplexed signal to the first memory 230. Multiplexing can be performed on a video line basis. The multiplexed signal output from the multiplexing unit 220 includes synchronization information. The multiplexing unit 220 may further include resolution information (e.g., information indicating an SD level, an HD level, a Full HD level, or the like) of the video along with the synchronization information in the multiplex signal. The multiplexer 220 outputs (writes) the multiplexed signal to the first memory 230 in accordance with the internal system clock SYS_CLK, which is a video signal clock.

The first memory 230 temporarily stores the multiplexed signal in accordance with the internal system clock SYS_CLK. The first memory 230 may be a FIFO memory.

The MAC module 24 receives the transmission clock PHY_CLK from the PHY module 25 and reads the multiplexed signal stored in the first memory 230 according to the transmission clock PHY_CLK to generate a packet. The MAC module 24 may generate a packet including one or more multiplexed signals. The MAC module 24 may include resolution information of the image (for example, information indicating SD class, HD class, Full HD class, etc.) in the header or data area.

The multiplexed signal is stored in the first memory 230 in accordance with the internal system clock SYS_CLK. That is, the multiplexed signal is not synchronized with the Ethernet-based MAC module 24 and the PHY module 25. Accordingly, the MAC module 24 reads the multiplexed signal stored in the first memory 230 in accordance with the transmission clock PHY_CLK. The multiplexed signal is inserted into the Ethernet packet structure in the MAC module 24 and transmitted to the PHY module 25.

The first reception control unit 260 may receive and output a control signal from the image receiving apparatus 30 through the PHY module 25 and the MAC module 24. The first reception control unit 260 may include a second memory 270 and a host CPU 280.

The second memory 270 temporarily stores the control signal output from the MAC module 25 in accordance with the transmission clock PHY_CLK. The second memory 270 may be a FIFO memory. The control signal is output from the second memory 270 in accordance with the system clock SYS_CLK.

The host CPU 280 receives the vertical synchronization signal V_SYNC and the horizontal synchronization signal H_SYNC and outputs the control signal in synchronization with the vertical synchronization signal V_SYNC and the horizontal synchronization signal H_SYNC. The control signal may be the audio signal AUX_Rx. The host CPU 280 can communicate with the PHY module 25 and the MAC module 24 via a host bus.

The PHY module 25 can transmit and receive signals with the MAC module 24 by means of a GMII (Gigabit Media Independent Interface) signal supporting a full duplex mode and a Management Data Input / Output (MDIO) signal.

8 is a block diagram schematically showing a configuration of a control unit of the image receiving apparatus according to an embodiment of the present invention.

The control unit 300 of FIG. 8 may function as the control unit 33 of the video receiving device 30 of FIG. 1 by software and / or hardware configuration. Referring to FIG. 8, the controller 300 may include a second reception controller 310 and a second transmission controller 360.

PHY module 31 can transmit and receive signals to / from MAC module 32 by a GMII (Gigabit Media Independent Interface) signal supporting a full duplex mode and a Management Data Input / Output (MDIO) signal.

The second reception control unit 310 receives and outputs multiplexed signals input from the image transmitting apparatus 20 through the PHY module 31 and the MAC module 32. [ The second reception controller 310 may include a third memory 320, a demultiplexer 330, a frame memory 340, and a synchronization signal generator 350.

The MAC module 32 receives a packet input from the PHY module 31 as a reception clock PHY_CLK, and extracts synchronization information, resolution information, and multiplexed signals from the packet. When the video line number is inserted in the packet, the MAC module 32 can extract the video line number together. The MAC module 32 stores (records) the multiplexed signal (Y / C signal and control signal) output from the MAC module 32 in the third memory 320 in accordance with the reception clock PHY_CLK. When the video line number is present, the MAC module 32 may store the video line number in the third memory 320 together.

The third memory 320 temporarily stores the multiplexed signal (Y / C signal and control signal) output from the MAC module 32 in accordance with the reception clock PHY_CLK. The third memory 320 may be a FIFO memory. The multiplexed signal is output from the third memory 320 in accordance with the internal system clock SYS_CLK.

The demultiplexing unit 330 reads the multiplexed signal according to the internal system clock SYS_CLK. The demultiplexer 330 demultiplexes the multiplexed signal and separates the Y signal, the C signal, and the control signal AUX_Rx in accordance with the pixel clock Pixel_CLK. The demultiplexing unit 330 outputs the audio signal AUX_Rx to the second transmission control unit 360 and the Y signal and the C signal to the frame memory 340. The demultiplexer 330 outputs the synchronization information and the resolution information to the synchronization signal generator 350.

The demultiplexing unit 330 may estimate the video line number by counting the start of the frame and the number of video lines based on the synchronization information. The demultiplexer 330 may extract the video line number and store (record) the video line number in the corresponding area of the frame memory 340 according to the video line number when the multiplexed signal includes the video line number.

Although the demultiplexing unit 330 performs the function of counting the video lines in the case of the multiplexed signal in which the video line numbers are not included in the present embodiment, the video lines can be counted by a separate counter to be.

In the frame memory 340, the Y signal and the C signal are stored in accordance with the pixel clock (Pixel_CLK) generated by the synchronization signal generator 350. The frame memory 340 may store a plurality of video line signals in a corresponding area. The video signal stored in the frame memory 340 is output in synchronization with the horizontal and vertical sync signals H / V_SYNC generated by the sync signal generator 350. Thus, jitter between packets and packets, that is, image distortion due to jitter between video lines can be prevented. The frame memory 340 may comprise a line memory or a frame memory and store one or more lines of video signals.

If there is a video line number, the frame memory 340 stores the video signal (Y signal and C signal) in the corresponding area according to the video line number. Accordingly, when the video signal of the nth line of the current frame is discarded due to a loss or an error, it can be replaced with the video signal of the nth line of the previous frame previously stored in the area. In this case, when there is no video line number, when the video signal is stored in the frame memory 340 by counting or in the order of input, if any video line is lost or discarded, the video signal is not recognized, It is possible to solve the problem that the image quality is deteriorated due to being stored in the image line area. The Y signal and the C signal output from the frame memory 340 can be reproduced or stored. If the Y signal and the C signal output from the frame memory 340 are compression signals, they can be decompressed and then reproduced or stored.

The synchronization signal generating unit 350 receives the synchronization information and the resolution information from the demultiplexing unit 330 and generates a pixel clock signal Pixel_CLK and a horizontal and vertical synchronization signal (H / V_SYNC) to the frame memory 340. Accordingly, the image receiving apparatus can restore the received packet to the inter-line time information of the image signal before transmission.

The second transmission control unit 360 can receive the externally input control signal and output it to the video transmission apparatus 20. [ The second transmission control unit 360 may include a host CPU 370 and a fourth memory 380.

The host CPU 370 receives a control signal (control data) input from the outside and outputs the control signal to the fourth memory 380. The control signal may include a voice signal AUX_Tx. The host CPU 370 can receive the audio signal transmitted from the video transmitting apparatus 20 from the signal separating unit 330 and output it to the audio output apparatus. The host CPU 370 can communicate with the PHY module 31 and the MAC module 32 via a host bus.

The fourth memory 380 stores the control signal in synchronization with the system clock SYS_CLK. The control signal is output from the fourth memory 380 to the MAC module 32 in synchronization with the reception clock PHY_CLK. The fourth memory 380 may be a FIFO memory.

9 is a flowchart illustrating a method of transmitting an image in an Ethernet-based digital image transmission apparatus according to an embodiment of the present invention. Hereinafter, detailed description of the contents overlapping with those described with reference to Figs. 1 to 8 will be omitted. In addition, although the digital video transmitting apparatus can receive and process the control signal from the digital video receiving apparatus, the control signal receiving and processing method has been described above, and thus will not be described below.

Referring to FIG. 9, in operation S701, the digital image transmission apparatus converts an analog image signal from an image sensor into a parallel digital image signal including a Y signal and a C signal in operation S702.

If the bandwidth of the multiplexed signal exceeds the Ethernet transmission bandwidth according to the image resolution, the digital image transmitting apparatus can compress the digitally converted Y signal and the C signal (S703). Compression is performed using compression techniques with little signal loss.

The digital video transmitting apparatus can multiplex the Y signal, the C signal, and the control signal from the audio input apparatus (S704). The multiplexed signal can be performed on a video line basis. The multiplexed signal is stored in a temporary memory, such as a FIFO, according to the system clock, and is output according to the transmission clock of the Ethernet-based packet transmission module (PHY module).

The digital video transmission apparatus can generate a packet including a multiplex signal (S705). The digital video transmission apparatus can generate a packet including one or more multiplexed signals, and can optionally insert a video line number into a packet.

The digital video transmission apparatus converts the packet into the Ethernet transmission format according to the gigabit Ethernet protocol and transmits the packet through the Ethernet cable (S706). The Ethernet cable may be an unshielded twisted pair cable.

On the other hand, the digital image transmission apparatus can insert an image standard such as image resolution information (SD class, Full HD class, etc.) at the time of multiplex signal generation or packet generation.

10 is a flowchart illustrating a method of receiving and processing an image in an Ethernet-based digital image receiving apparatus according to an embodiment of the present invention. Hereinafter, detailed description of the contents overlapping with those described with reference to Figs. 1 to 8 will be omitted. Also, the digital video receiving apparatus can receive the control signal from the outside and transmit it to the digital video transmitting apparatus, but since the method of transmitting the control signal has been described above, the following description will be omitted.

 Referring to FIG. 10, a packet having synchronization information and including at least one multiplexed signal in which a Y signal, a C signal, and a control signal are multiplexed may be received through an Ethernet cable according to the Gigabit Ethernet protocol (S801). The cable may be an unshielded twisted pair cable.

The digital image receiving apparatus extracts the multiplexed signal included in the packet (S802). When the video line number is inserted in the packet, the digital video receiving apparatus can extract the video line number together with the multiplex signal.

The digital image receiving apparatus can separate the multiplexed signal into a video signal (Y / C signal) and a control signal, respectively (S803). The digital image receiving apparatus can extract the synchronization signal and the image resolution information. The digital image receiving apparatus may temporarily store the multiplexed signal input in accordance with the reception clock of the packet reception module (PHY module), and output the multiplexed signal according to the internal clock.

The digital image receiving apparatus stores a video signal (Y / C signal) in unit of a video line, and outputs a video signal by synchronizing the video lines based on the synchronization signal and the video resolution information (S804). The voice signal can be output through the voice output device. The digital image receiving apparatus stores the image signal (Y / C signal) in units of image lines according to the extracted image line number, synchronizes the image signal (Y / C signal) with the vertical synchronizing signal and the horizontal synchronizing signal, It can synchronize and output.

If necessary, the digital image receiving apparatus can decompress the image signal when the image signal is a compressed image signal (Y / C signal).

11 is a block diagram illustrating a digital image data transmission / reception system according to another embodiment of the present invention.

11, the video transmitting apparatus is implemented as a camera 20A, 20B, 20C, and 20D, and the video receiving apparatus is implemented as a digital video recorder (DVR) 30A. The embodiment of FIG. 11 has one or more cameras 20A, 20B, 20C and 20D and the DVR 30A is connected to each of the cameras 20A, 20B, 20C and 20D and the UTP cables 40A, 40B, 1 in that they are connected in a one-to-one manner via the first and second electrodes 40A, 40B, 40D. In the embodiment of FIG. 11, four cameras are shown for the sake of convenience, but the present invention is not limited to this, and it goes without saying that one or more cameras may be connected to each other by a DVR and a cable.

The camera 20A may include an image sensor 21A, a video signal processing unit 22A, a compression unit 23A, a control unit 24A, a MAC module 25A, and a PHY module 26A.

The digital video recorder (DVR) 30A may include a PHY module 31A, a MAC module 32A, a first control section 33A, and a restoration section 34A. The digital video recorder (DVR) 30A may further include a network communication unit 35, a mux and a codec 36, and a storage device 37 controlled by the second control unit 38. The DVR 30A digitally compresses the video signal and the audio signal through the mux and the codec 36, stores the digital video signal and the audio signal in the storage device 37, and reproduces the same. Also, the DVR 30A can transmit and receive video and audio signals to / from an external terminal via a network communication unit 35 by wire or wireless.

The cameras 20A, 20B, 20C and 20D and the digital video recorder (DVR) 30A are connected to each other using four pairs of Cat 5e as UTP cables 40A, 40B, 40C and 40D.

The configuration and operation of each camera and DVR are the same as those of the video transmitting apparatus 20 and the video receiving apparatus 30 shown in Figs. 1 to 8, and therefore, detailed description thereof will be omitted.

12 is a block diagram schematically showing a digital image data transmission apparatus according to another embodiment of the present invention.

12, the digital image data transmission apparatus 120 may include an image sensor 121, a video signal processing unit 123, an HD-SDI transmission module 125, and an Ethernet-based transmission / reception module 127.

The digital image data transmission apparatus 120 converts the analog image signal output from the image sensor 121 into a digital signal from the image signal processing unit 123. [ The converted digital signal includes a Y signal and a C signal having synchronization information.

In the HD-SDI transmission mode, the Y signal and the C signal are transmitted to the HD-SDI transmission module 125 for signal processing. The configuration of the HD-SDI transmission module 125 is the same as the configuration of the video transmission apparatus shown in FIG. 13, and a detailed description thereof will be omitted.

When the Y signal and the C signal are in the Ethernet based transmission / reception mode, they are transmitted to the Ethernet based transmission / reception module 127 and signal processed. The Ethernet-based transmission / reception module 127 is the same as the configuration of the video transmission apparatus shown in FIG. 1 to FIG. 8, and thus a detailed description thereof will be omitted.

The video transmitting apparatus of FIG. 12 has a separate port, and has an advantage of transmitting / receiving video signals using the coaxial cable in the HD-SDI transmission mode or transmitting / receiving video signals using the Ethernet cable in the Ethernet based transmission / reception mode have.

The present invention ensures a stable transmission band by matching UTP cable of Cat5e or Cat6 standard and Gigabit physical module (Giga-PHY), which can be purchased inexpensively with standardization, so that there is no transmission loss which is a problem in the conventional analog transmission method. In addition, since the present invention transmits digital signals without compression such as MPEG / JPEG, there is no deterioration of image quality, the structure of the camera side is simple, and delay time due to compression / restoration is eliminated.

The present invention enables Ethernet transmission by matching a Giga-PHY with a Giga-PHY by forming a video signal having a data structure and / or a different data rate as a packet. In addition, the present invention can achieve synchronization of a transmitting / receiving end through a FIFO memory. By using the reference synchronization according to the video standard, the receiver has a memory for one line or more, and controls the packets converted by the line-by-line video signal transmitted through the gigabit physical module (Giga-PHY) It can be restored to the lap time information of the signal.

The embodiments described above describe a 1Gbps Gigabit Ethernet based image transmission and reception system with 1000BASE-T PHY technology. However, the present invention is not limited to this, and it goes without saying that the present invention can be equally applied to an Ethernet-based video transmission / reception method in which a bandwidth is extended from several gigabits to several tens of gigabits. Accordingly, in the case of a multi-gigabit Ethernet based network, since the Ethernet transmission bandwidth increases and the amount of image signals that can be transmitted and received increases, it is also possible to perform image compression selectively according to the amount of image signals that can be transmitted and received.

The present invention can be applied to a surveillance system, and in particular, it is easy to construct a surveillance environment in a small-scale store where compatibility between the transmitting and receiving sides is not so great. For example, the present invention can be applied to a surveillance system kit for a small-scale store, which comprises a camera and a monitor-integrated recorder with a size of 4 to 16 cameras as a kit.

The system of the present invention multiplexes a digital image and a control signal of an HD-class surveillance camera outputting digital information from a transmitting device, converts the digital image and control signal into a packet form, and transmits the unshielded twisted-pair (UTP) signal through a general-purpose Gigabit- Cable. Then, the receiving apparatus receives the packet through the general-purpose gigabit physical module (Giga-PHY), removes the packet-unit jitter, corrects the synchronization, and restores the original image. Accordingly, it is possible to realize long distance transmission / reception of HD class high definition digital video signal at low cost.

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (10)

A signal processor for converting an analog video signal inputted from the image sensor into a digital signal of a luminance signal and a color signal;
A multiplexer for multiplexing the luminance signal and the color signal having the digital information and having the synchronization information on a line basis to generate a multiplexed image signal having the line unit synchronization information;
A first memory for temporarily storing the multiplexed video signal in accordance with an internal clock;
A medium access control (MAC) module for reading a multiplexed video signal stored in the first memory in accordance with the internal clock according to a transmission clock and generating a packet for each line including at least one multiplexed video signal; And
And a physical (PHY) module for converting the packet into an Ethernet transport format and transmitting the packet over an unshielded twisted pair cable. The method according to claim 1,
And a compression unit for compressing the luminance signal and the color signal when the bandwidth of the multiplexed video signal exceeds an Ethernet transmission bandwidth according to a video resolution. The image processing apparatus according to claim 2,
Lossless compression, DPCM compression, and sub-sampling rate control compression. The apparatus of claim 1, wherein the MAC module further comprises:
And inserts the line number of the multiplexed video signal into the packet. The method according to claim 1,
And the video resolution information is inserted into the multiplexed video signal or packet. The method according to claim 1,
And a second memory for temporarily storing a control signal received in accordance with a transmission clock of the PHY module via the unshielded twisted pair cable and outputting the control signal according to the internal clock. A luminance signal and a color signal, which are digitally converted from an analog video signal and have synchronization information, are multiplexed in a line unit, and a line unit packet including at least one multiplexed video signal including line unit synchronization information is transmitted through an unshielded twisted pair cable A receiving physical (PHY) module;
A medium access control (MAC) module for extracting the at least one multiplexed video signal and the line unit synchronization information in the packet;
A third memory in which the multiplexed video signal is temporarily stored according to a reception clock of the PHY module;
A demultiplexer for dividing the multiplexed video signal stored in the third memory in accordance with the reception clock into a luminance signal and a color signal in accordance with an internal clock;
A synchronization signal generator for generating a vertical synchronization signal and a horizontal synchronization signal based on the line unit synchronization information; And
And a frame memory for storing the separated luminance signal and the color signal in units of lines and outputting the synchronized signals in synchronization with the vertical synchronizing signal and the horizontal synchronizing signal. 8. The method of claim 7,
And a fourth memory for temporarily storing an externally input control signal in accordance with the internal clock, and outputting the control signal to the MAC module according to the received clock. 8. The method of claim 7,
And a decompression unit decompressing the decompressed luminance signal and the chrominance signal when the separated luminance signal and the chrominance signal are compressed signals. 8. The method of claim 7,
The demultiplexer demultiplexes the control signals included in the multiplexed video signal,
Wherein the frame memory stores the luminance signal and the color signal in a corresponding line area based on a line number included in the packet.

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