KR100476371B1 - Method of forming flattening insulating film between metal layers - Google Patents

Method of forming flattening insulating film between metal layers Download PDF

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KR100476371B1
KR100476371B1 KR1019970078010A KR19970078010A KR100476371B1 KR 100476371 B1 KR100476371 B1 KR 100476371B1 KR 1019970078010 A KR1019970078010 A KR 1019970078010A KR 19970078010 A KR19970078010 A KR 19970078010A KR 100476371 B1 KR100476371 B1 KR 100476371B1
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film
forming
sog film
insulating film
semiconductor device
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KR1019970078010A
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KR19990057931A (en
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오찬권
남철우
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Abstract

본 발명은 셀 영역과 주변 회로 영역간의 평탄화를 위한 반도체 소자 제조 방법에 관한 것으로써, 하부 금속배선이 형성된 기판 상부에 무기물 SOG막에 비해 상대적으로 낮은 식각율을 갖는 절연막을 형성하는 제1단계; 상기 제1단계가 완료된 결과물 상부에 상기 무기물 SOG막을 형성하고 큐어링하는 제2단계; 상기 무기물 SOG막을 화학적 기계적 연마하는 제3단계; 및 상기 제3단계 후에 플라즈마 화학기상 방법의 산화막을 형성하는 제4단계를 포함하여 이루어진다.The present invention relates to a method of fabricating a semiconductor device for planarization between a cell region and a peripheral circuit region, the method comprising: forming an insulating layer having an etching rate relatively lower than that of an inorganic SOG film on a substrate on which a lower metal wiring is formed; A second step of forming and curing the inorganic SOG film on the resultant of which the first step is completed; Chemical mechanical polishing the inorganic SOG film; And a fourth step of forming an oxide film of the plasma chemical vapor method after the third step.

Description

금속층간의 평탄화 절연막 형성 방법Method of forming planarization insulating film between metal layers

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 셀 영역과 주변 회로 영역간의 평탄화를 위하여 화학적 기계적 연마법을 사용하는 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a chemical mechanical polishing method for planarization between a cell region and a peripheral circuit region.

잘 알려진 바와 같이, 소자가 고집적화됨에 따라 적층형의 소자 형성 방법이 성행하고 있으며, 이러한 각각의 적층된 소자들은 층간절연막에 의하여 절연을 이룰 수 있다. 이러한 층간절연막으로 평탄화기 용이한 SOG(spin on glass)막이 주로 사용되며, 참고로 일반적인 SOG막은 메틸(-CH3)기가 실리콘 원자와 소정량 결합되어 있는 실록사인(siloxane)계의 유기물 SOG막이 사용된다.As is well known, as a device is highly integrated, a stacked device forming method is prevalent, and each of these stacked devices can be insulated by an interlayer insulating film. As the interlayer insulating film, an SOG (spin on glass) film that is easily planarized is mainly used. For reference, a general SOG film is a siloxane organic SOG film having a predetermined amount of methyl (-CH 3 ) group bonded to a silicon atom. do.

도1a 내지 도1c는 종래의 금속층간절연막 형성 공정과 그 문제점을 나타내는 공정 단면도로서, 먼저, 도1a에 도시된 바와 같이, 실리콘 기판(11) 상부에 하부 금속막으로 예를 들면 알루미늄(12)을 형성한 후, 이를 패터닝 한다. 이러한 알루미늄(12)의 절연을 위하여 산화막(13)을 증착한 후, 유기물 SOG막(14)을 회전 도포하여 알루미늄(12) 패턴 간극을 메우고, 평탄화를 이룬다. 그리고, 유기물 SOG막(14)에 포함되어 있는 수분을 증발시키기 위하여 적절한 온도에서 열처리(curing)한다. 그리고, 이러한 유기물 SOG막(14)을 선택식각하여 알루미늄(12)을 노출시키는 콘택홀을 형성하고, 알루미늄(12)과 콘택되는 상부 금속막 플러그를 형성한다.1A to 1C are cross-sectional views illustrating a conventional metal interlayer insulating film forming process and its problems. First, as shown in FIG. 1A, for example, aluminum 12 is formed as a lower metal film on the silicon substrate 11. After forming, it is patterned. After depositing the oxide film 13 to insulate the aluminum 12, the organic SOG film 14 is rotated and coated to fill the gap of the aluminum 12 pattern, thereby achieving planarization. Then, heat treatment is performed at an appropriate temperature in order to evaporate the moisture contained in the organic SOG film 14. Then, the organic SOG film 14 is selectively etched to form a contact hole exposing the aluminum 12, and an upper metal film plug contacting the aluminum 12 is formed.

그러나 이러한 유기물 SOG막(14)을 식각하여 알루미늄(12)과 상부 금속막과 콘택을 형성할 때 유기물 SOG막(14)의 잔류되어 있는 수분이 알루미늄(12)을 산화시켜 Al2O3층(도시되지 않음)을 형성시킴으로써 콘택 저항을 증가시켜 전기적 특성을 악화시키는 결과를 가져온다. 이러한 문제점을 해결하기 위하여 추후 진행되는 콘택홀의 형성시 SOG막(14)을 식각제에 노출시키지 않기 위한 목적으로 알루미늄(12)상부에 형성되는 SOG막(14)을 모두 제거하여 알루미늄(12) 패턴 간극에만 SOG막(14)을 잔류시키기 위한 방안으로 전면 식각공정 및 화학적 기계적 연마 공정을 실시한다.However, when the organic SOG film 14 is etched to form a contact with the aluminum 12 and the upper metal film, the remaining water of the organic SOG film 14 oxidizes the aluminum 12 to form an Al 2 O 3 layer ( (Not shown) increases contact resistance resulting in worsening electrical characteristics. In order to solve this problem, the aluminum 12 pattern is removed by removing all the SOG film 14 formed on the aluminum 12 for the purpose of not exposing the SOG film 14 to the etchant during the formation of a contact hole. In order to leave the SOG film 14 only in the gap, the entire surface etching process and the chemical mechanical polishing process are performed.

다음으로, 도1b는 SOG막(14)을 전면식각한 상태의 단면도로써, 도시된 바와 같이 주변 회로 영역(B)과 셀 영역(A)의 패턴 (도면의 12) 밀도차에 의해 주변회로 영역(B)에서는 디싱(dishing) 현상이 발생하여 광역 평탄화가 불가능하다. 또한 식각제에 의한 파티클(15)이 평탄화된 표면 상부에 잔류하여 추후 진행되는 상부 금속막 형성 공정시 콘택 저항을 증가시키는 문제점을 유발시킨다.Next, FIG. 1B is a cross-sectional view of the SOG film 14 with the entire surface etched. As shown in FIG. 1B, the peripheral circuit region is formed by the density difference between the peripheral circuit region B and the cell region A (12). In (B), dishing occurs and wide area planarization is impossible. In addition, the particles 15 due to the etchant remain on the flattened surface, which causes a problem of increasing contact resistance in a subsequent upper metal film formation process.

다음으로, 도1c는 도1a의 상태에서 SOG막(14)을 화학적 기계적 연마한 상태의 단면도로써, 일반적인 유기물 SOG막의 연마 특성상 산화막(13)이 유기물SOG막(14)에 비해 빠른 연마 속도를 가짐으로서 과도 연마가 발생하였을 경우, 셀 영역(A)과 주변회로 영역(B)의 경계부위에서의 알루미늄(12)이 화학적 기계적 연마에 노출되어 소자 페일의 문제점을 가져온다.Next, FIG. 1C is a cross-sectional view of a state in which the SOG film 14 is chemically mechanically polished in the state of FIG. 1A, and the oxide film 13 has a faster polishing rate than the organic SOG film 14 due to the polishing characteristics of the general organic SOG film. As a result, when excessive polishing occurs, aluminum 12 at the boundary between the cell region A and the peripheral circuit region B is exposed to chemical mechanical polishing, resulting in a device fail.

따라서 이러한 문제점들을 극복할 수 있는 반도체 소자의 평탄화 방법의 개발이 필요하게 되었다.Therefore, it is necessary to develop a planarization method of a semiconductor device that can overcome these problems.

전술한 바와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 반도체 소자의 셀 영역과 주변 회로 영역의 평탄화 공정시, 평탄화 특성을 향상시키며 평탄화 공정시 파티클 문제 및 하부 금속막이 오픈되는 문제점을 극복할 수 있는 반도체 소자 제조 방법을 제공함을 그 목적으로 한다.The present invention devised to solve the above-described problems can improve the planarization characteristics in the planarization process of the cell region and the peripheral circuit region of the semiconductor device, and can overcome the problem of particle problems and the lower metal film opening during the planarization process. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

상기와 같은 목적을 달성하기 위하여 본 발명의 반도체 소자 제조 방법은, 하부 금속배선이 형성된 기판 상부에 무기물 SOG막에 비해 상대적으로 낮은 식각율을 갖는 절연막을 형성하는 제1단계; 상기 제1단계가 완료된 결과물 상부에 상기 무기물 SOG막을 형성하고 큐어링하는 제2단계; 상기 무기물 SOG막을 화학적 기계적 연마하는 제3단계; 및 상기 제3단계 후에 플라즈마 화학기상 방법의 산화막을 형성하는 제4단계를 포함하여 이루어진다.In order to achieve the above object, the semiconductor device manufacturing method of the present invention includes a first step of forming an insulating film having a relatively low etching rate compared to the inorganic SOG film on the substrate on which the lower metal wiring is formed; A second step of forming and curing the inorganic SOG film on the resultant of which the first step is completed; Chemical mechanical polishing the inorganic SOG film; And a fourth step of forming an oxide film of the plasma chemical vapor method after the third step.

본 발명은 무기물 SOG 막을 사용하여, 이를 화학적 기계적 연마 공정 방법을 사용하여 전면식각할 때, 하부의 절연막에 의하여 연마공정이 정지되는 것을 이용한다.In the present invention, when the inorganic SOG film is etched entirely by using the chemical mechanical polishing process method, the polishing process is stopped by the insulating film at the bottom.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도2a 내지 도2c는 본 발명의 일실시예에 따른 금속층간절연막 형성 공정도이다.2A through 2C are flowcharts of forming an interlayer dielectric film according to an exemplary embodiment of the present invention.

먼저, 도2a에 도시된 바와 같이, 실리콘 기판(21) 상부에 하부 금속막으로 예를 들면 알루미늄(22)을 형성한 후, 이를 패터닝 한다. 이러한 알루미늄(22)의 절연을 위한 절연막으로 실리콘 질화 산화막(SiOxNy)(23)을 증착한다. 경우에 따라 이러한 절연막은 실리콘이 함유된 산화막(Si rich oxide), MTO(medium temperature oxide), HTO(high temperature oxide), SiH4 가스를 소스로 하는 PECVD(plasma enhanced CVD)에 의한 SiO2막(PE- SiH4 Undoped Silicate Glass) 또는 TEOS(Tetra ethyl orthosilicate)를 소스로 하는 PECVD에 의한 SiO2막을 400Å 내지 4000Å으로 증착한다. 바람직하게 이러한 절연막은 SOG에 흡착된 수분이 알루미늄(22) 등의 하부층으로 침투되는 것을 효과적으로 차단하며 수소 이온에 의한 소자의 열화를 방지하는 수분 침투 방지막으로도 작용한다. 또한 무기물 SOG의 화학적 기계적 연마시 연마정지층 역할을 한다.First, as shown in FIG. 2A, for example, aluminum 22 is formed as a lower metal layer on the silicon substrate 21, and then patterned. A silicon nitride oxide film (SiOxNy) 23 is deposited as an insulating film for insulating the aluminum 22. In some cases, the insulating film may be a SiO 2 film formed by a plasma enhanced CVD (PECVD) sourced from a silicon-containing oxide (Si rich oxide), a medium temperature oxide (MTO), a high temperature oxide (HTO), or a SiH 4 gas. SiO 2 film by PECVD with PE-SiH 4 Undoped Silicate Glass (TEOS) or Tetra ethyl orthosilicate (TEOS) as a source is deposited at 400 kPa to 4000 kPa. Preferably, the insulating film effectively blocks the moisture adsorbed on the SOG from penetrating the lower layer such as aluminum 22, and also acts as a moisture penetration prevention film to prevent deterioration of the device by hydrogen ions. It also serves as a polishing stop layer for chemical mechanical polishing of inorganic SOG.

다음으로, 도2b에 도시된 바와 같이, 무기물 SOG막(24)을 4000Å 내지 10000Å의 두께로 형성한 후 400℃내지 600℃로 열처리한다. 여기서 이러한 무기물 SOG막(24)으로는 예컨데 하이드로겐 실세스퀴옥사인(hydrogen silsesquiozane )또는 실리게이트 SOG를 사용한다.Next, as shown in FIG. 2B, the inorganic SOG film 24 is formed to a thickness of 4000 kPa to 10000 kPa, and then heat treated at 400 ° C to 600 ° C. The inorganic SOG film 24 may be, for example, hydrogen silsesquiozane or silicide SOG.

다음으로, 도2c에 도시된 바와 같이, 화학적 기계적 연마 공정을 실시하여 상기 무기물 SOG막(24)의 연마공정을 진행하면 실리콘 질화 산화막(23)에 의하여 연마 공정이 정지된다. 즉, 실리콘 질화 산화막(23)은 무기물 SOG막(24)에 비하여 1/3정도 느리게 연마되는 특징을 나타낸다. 본 발명에서 제시하는 바람직한 화학적 기계적 연마 공정은 슬러리내의 연마재로 실리카를 사용하며, 실리카의 크기를 50㎚ 내지 300nm로 유지하며, 슬러리의 유량은 100㎖/분 내지 400㎖/분으로 유지하며, 슬러리의 pH는 9 내지 13으로 유지하는 것이다. 이러한 평탄화 공정이 완료된 후에 재차 PECVD 산화막을 500Å 내지 6000Å의 두께로 증착한다.Next, as shown in FIG. 2C, the polishing process of the inorganic SOG film 24 is performed by performing a chemical mechanical polishing process to stop the polishing process by the silicon nitride oxide film 23. That is, the silicon nitride oxide film 23 is polished about 1/3 slower than the inorganic SOG film 24. The preferred chemical mechanical polishing process proposed in the present invention uses silica as the abrasive in the slurry, maintains the size of the silica at 50nm to 300nm, the flow rate of the slurry is maintained at 100ml / min to 400ml / min, Is maintained at 9 to 13. After the planarization process is completed, the PECVD oxide film is deposited again to a thickness of 500 kV to 6000 kV.

전술한 바와 같이 이루어지는 본 발명은, 금속 층간절연막인 무기물 SOG막에 비해 연마 속도가 1/3 정도 느린 실리콘 질화 산화막의 증착 두께를 증가시켜 연마 정지층으로 이용하여 화학적 기계적 평탄화 공정을 진행함으로써 웨이퍼내 연마 균일도를 향상시킨다.The present invention as described above increases the deposition thickness of the silicon nitride oxide film, which is about 1/3 slower than that of the inorganic SOG film, which is a metal interlayer insulating film, and performs a chemical mechanical planarization process using the polishing stop layer as a polishing stop layer. Improves polishing uniformity

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

상기와 같이 이루어지는 본 발명은, 반도체 소자 제조시 하부 금속막의 형성후에 금속 산화 방지막으로 SOG막보다 1/3정도 식각비가 느린막을 형성하고, 이를 화학적 기계적 연마 공정을 SOG막에 적용할 때, 연마 정지층으로 사용함으로써, 하부 금속막이 오픈되는 것을 방지하여 소자의 수율을 향상시킨다.According to the present invention as described above, after forming the lower metal film during the manufacture of a semiconductor device, a film having an etch rate of about 1/3 slower than that of the SOG film is formed as a metal oxide film, and when the chemical mechanical polishing process is applied to the SOG film, polishing stops. By using it as a layer, the lower metal film is prevented from opening to improve the yield of the device.

또한 금속 산화 방지막이 식각되지 않음으로써 후속의 상부 금속막 형성시EM(Electro Migration) 및 SM(Stress Migration) 현상 발생을 억제함으로써 금속 배선 의 전기적 저항을 감소시켜 소자 특성을 향상시킨다.In addition, since the metal oxide film is not etched, it suppresses the occurrence of EM (Electro Migration) and Stress Migration (SM) during subsequent formation of the upper metal film, thereby reducing the electrical resistance of the metal wiring to improve device characteristics.

도1a 내지 도1c는 종래 기술에 따른 금속층간절연막 형성 공정도.1A to 1C are process steps for forming an interlayer dielectric film according to the prior art;

도2a 내지 도2c는 본 발명의 일실시예에 따른 금속층간절연막 형성 공정도.2A to 2C are process diagrams for forming an interlayer dielectric film according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 실리콘 기판 22 : 알루미늄21: silicon substrate 22: aluminum

23 : 실리콘 질화산화막 24 : 무기물 SOG막23 silicon nitride oxide film 24 inorganic SOG film

Claims (6)

하부 금속배선이 형성된 기판 상부에 무기물 SOG막에 비해 상대적으로 낮은 식각율을 갖는 절연막을 형성하는 제1단계;Forming an insulating film having an etching rate relatively lower than that of the inorganic SOG film on the substrate on which the lower metal wiring is formed; 상기 제1단계가 완료된 결과물 상부에 상기 무기물 SOG막을 형성하고 큐어링하는 제2단계;A second step of forming and curing the inorganic SOG film on the resultant of which the first step is completed; 상기 절연막을 연마정지층으로하여 상기 무기물 SOG막을 화학적 기계적 연마하는 제3단계; 및Chemical mechanical polishing the inorganic SOG film using the insulating film as a polishing stop layer; And 상기 제3단계 후에 플라즈마 화학기상 방법의 산화막을 형성하는 제4단계A fourth step of forming an oxide film of the plasma chemical vapor method after the third step 를 포함하여 이루어지는 반도체 소자 제조 방법.A semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 절연막이 SiOxNy, 실리콘이 포함된 산화막, MTO, HTO 및 PECVD 산화막중 어느 하나인 반도체 소자 제조 방법.The insulating film is a semiconductor device manufacturing method of any one of SiOxNy, oxide containing silicon, MTO, HTO and PECVD oxide. 제1항에 있어서,The method of claim 1, 상기 절연막의 두께가 400Å 내지 4000Å인 반도체 소자 제조 방법.A semiconductor device manufacturing method, wherein the insulating film has a thickness of 400 kPa to 4000 kPa. 제3항에 있어서,The method of claim 3, 상기 무기물 SOG막의 두께가 4000Å 내지 20000Å인 반도체 소자 제조 방법.The inorganic SOG film has a thickness of 4000 kPa to 20000 kPa. 제4항에 있어서,The method of claim 4, wherein 상기 SOG막의 큐어링을 400℃ 내지 1000℃에서 실시하는 반도체 소자 제조 방법.The semiconductor device manufacturing method which performs curing of the said SOG film at 400 degreeC-1000 degreeC. 제1항에 있어서,The method of claim 1, 상기 제4단계의 플라즈마 화학기상 방법의 산화막이 500Å 내지 6000Å인 반도체 소자 제조 방법.The oxide film of the plasma chemical vapor deposition method of the fourth step is a 500Å to 6000Å semiconductor device manufacturing method.
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