JPS6038912B2 - Signal processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing system, and more particularly to a system for producing various special effects on a television screen by processing a plurality of video signals.

Such special effects include, for example, differentially mixing two video signals A and B to create an initial video signal A.
There is a dissolve technique that transforms an image containing only video signal B into an image containing only video signal B.

In this case, a technique in which one of the video signals A and B is in the form of a black burst and the other is in the form of an image signal is called a fade technique. Furthermore, the effect in which the A and B signals are fixed at 50% of each other's level is called a mix, and the dissolve period is called a duration. Also, when the duration is 0, the effect of switching from the A signal to the B signal is cut. Typically, to provide such a dissolve effect, a variable gain intensifier is used that receives input video signals and differentially changes and mixes the levels of these video signals.

Additionally, external lamp control signals are provided to such intensifiers to control the gain of such intensifiers. The initial level of the lamp is controlled so that only the A signal is output from the intensifier.
As the lamp oscillation increases, the mixing ratio of the B signal increases,
At the final value of the ramp, only the B signal will be output from the intensifier. In this manner, the slope of the ramp represents the rate of mixing of the A and B signals. Different durations can be obtained by changing the slope without changing the initial and final levels of the ramp. FIG. 1 shows a typical conventional scheme for obtaining such lamp control signals from frame pulses.

The frame pulse fv input to terminal 10 is applied as a clock counting input to an 8-bit counter 12, and the counter output is input to an 8-bit D/A converter 14, the output of which is a gain-controlled gain control according to an external data source 16. 20, producing a lamp control voltage Vo at the output terminal 22. In this configuration, the frame pulses to be counted and the duration to be set are matched, so if the duration is small, the linearity of the ramp signal will be impaired, as shown in Figure 2. I end up. That is, the output voltage V is plotted on the vertical axis. In Figure 2, where the duration value n in frame units is taken for horizontal coins,
If n is 1 (frame), the operation will be the same as cutting one frame later than the starting point. In this method, in order to expand the controllable duration value n (frames), it is necessary to increase the number of bits of the counter 2 and the D/A converter 14, and an intensifier with programmable gain is required. 20 saturation levels, ie, the dynamic range needs to be expanded. Multi-bit counters and D/A converters are expensive, and such changes in multipliers complicate the construction and increase cost. Further, the reason why a frame pulse is used as the clock pulse of the counter 12 is that the start of the dissolve effect is performed in correspondence with the frame of the screen. In one embodiment of the invention, as shown in FIG.
Three types of clock signals can be selectively used as inputs.

That is, a frame pulse fv is applied to the terminal 24, a double frame pulse v is applied to the terminal 26, and the frame pulse fV is divided by the frequency divider 28 to produce a frequency of f>. The switch 3 allows pulses of these three frequencies, 2v.fV and 5V, to be used selectively. In the above configuration, when the set duration value n (frame) is ISnSI27, the field pulse of the public v is counted as a clock, and if the gain data setting of the multiplier 20 is set to small, the output control voltage Vo is ,V.

For example, when the duration n is 4, the linearity (that is, the resolution) of the lamp is improved by twice as much as shown in FIG.

When the set duration n is 128 Sn - 255, frame pulses fv are counted in the same manner as the conventional method described above.

If the intensification degree of the intensifier is set to n, the output voltage will be V
.

=Harm-n:k.

Furthermore, when the set duration value n is 256SnS511, it can be used as a clock.
Count responses.

If the intensification degree of the intensifier is set to the desired value, the output voltage Vo will be V in this case as well.

=equal sign=k.

Here, the resolution of the control voltage is half of that when the frame pulses fv are counted, but it can be ignored with respect to the set duration value n. With the above configuration, the final lamp output level k is kept constant.

By controlling the clock frequency and the gain of the multiplier in a correlated manner, the nonlinearity of the output ramp waveform when the duration setting value is small can be improved without the need to increase the number of bits of the counter and D/A converter. can. Furthermore, even if a long duration is selected, it is possible to handle this with a 4-bit counter by reducing the counting frequency. It should be understood that the embodiment of FIG. 3 is merely an illustration of a specific example of the present invention, and the numerical values used in the explanation are not limiting.

Furthermore, the switches 30 may be electronic switches and may be controlled in response to an external command signal along with the gain control of the intensifier. Counters and D/A converters other than those having an 8-bit configuration may be used. A clock source whose frequency changes with the set duration may be used.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a conventional dissolve control ramp signal generation circuit, FIG. 2 is an output waveform diagram for explaining its operation, FIG. 3 is an explanatory circuit diagram of an embodiment of the present invention method, and FIG.
The figure is an output waveform diagram for explaining one motion elbow b mode of the figure 3 method. In the figure, 24 is an fv clock input terminal, 26 is a public v clock input terminal, 28 is a frequency divider, and 3o is a switch.
Traditional maple*2 Figure 3 Figure 4

Claims (1)

[Claims] 1 Varying the mixing ratio of the input signals by outputting at least two signals to a variable gain amplifier and controlling the gain of the amplifier by a level changing signal having predetermined initial and final levels. In such a signal processing system, a clock signal generation device that generates a plurality of clock signals frequency-related to the signal components of the input signal, a selection circuit that selects the plurality of clock signals, and the selection circuit a counter that counts based on a selected clock signal; a D/A converter that converts the output of the counter into an analog level signal; and a variable gain amplifier that outputs the level change signal using the output of the D/A converter. A signal processing method comprising: changing a gain change rate of the variable gain amplifier to the output of the D/A converter in accordance with selection of the clock frequency.