JPS60192447A - Faulty data reception preventing circuit - Google Patents
Faulty data reception preventing circuitInfo
- Publication number
- JPS60192447A JPS60192447A JP59048818A JP4881884A JPS60192447A JP S60192447 A JPS60192447 A JP S60192447A JP 59048818 A JP59048818 A JP 59048818A JP 4881884 A JP4881884 A JP 4881884A JP S60192447 A JPS60192447 A JP S60192447A
- Authority
- JP
- Japan
- Prior art keywords
- control information
- length
- circuit
- maximum data
- slave device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L13/00—Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）１発明の技術分野
本発明は異常データ受信防止回路に係り、特に主装置か
ら制御情報を受信して動作する従装置の異常データ受信
防止回路に関するものである。Detailed Description of the Invention (a) 1 Technical Field of the Invention The present invention relates to an abnormal data reception prevention circuit, and more particularly to an abnormal data reception prevention circuit for a slave device that operates by receiving control information from a main device. .
（ｂ）、従来技術と問題点
電子交換機等に於いて主装置から制御情報を受信して動
作する従装置は、常に其の受信部をイネーブル状態に保
持して主装置からの制御情報を受信出来る状態にしてお
かなければならない。(b), Prior Art and Problems In electronic exchanges, etc., slave devices that operate by receiving control information from the main device always keep their reception section enabled to receive control information from the main device. You have to make it possible.
第１図は従装置内に設けられる主装置からの１ｉｆｔ御
情報を受信する回路の一実施例を示す概略図である。FIG. 1 is a schematic diagram showing an embodiment of a circuit provided in a slave device for receiving 1ift control information from a main device.
図中、Ｉ）ＭＡＣはダイレクトメモリアクセスコントロ
ーラ、ＡＤＬＣはアドバンストデータリンクコントロー
ラ、ＭＥＭはメモリ、Ｃ０ＮＴは制御回路、ＰＩＡはべ
りフェラルインターフェイスアダプタである。尚以下全
図を通じ同一記号は同一対象物を表す。In the figure, I) MAC is a direct memory access controller, ADLC is an advanced data link controller, MEM is a memory, C0NT is a control circuit, and PIA is a ferrule interface adapter. The same symbols represent the same objects throughout all the figures below.
主装置から従装置に対し送信する制御情報は普通ＤＭＡ
方式によりデータ転送される。即ち主装置からの制御情
報はアドバンストデータリンクコントローラＡＤＩ、Ｃ
に入る。アドバンストデータリンクコントローラＡＤＬ
Ｃはシリアルデータの送受信回路でシリアル形式で送ら
れて来る制御情報を受信し、ダイレクトメモリアクセス
コントローラＤＭＡＣの制御によりメモリＭＥＭに収容
される。The control information sent from the main device to the slave device is usually DMA.
Data is transferred according to the method. That is, the control information from the main device is sent to the advanced data link controller ADI, C.
to go into. Advanced data link controller ADL
C is a serial data transmitting/receiving circuit that receives control information sent in serial format, and stores it in the memory MEM under the control of the direct memory access controller DMAC.
制御回路Ｃ０ＮＴは此の様にして主装置から受信した制
御情報をメモリＭＥＭから読み出し従装置としての機能
を実行する。The control circuit C0NT reads out the control information received from the main device from the memory MEM in this way and executes the function as a slave device.
此の様な従装置に於いて例えば伝送路等の故障及び主装
置からの情報に誤りが生ずる等の原因により従装置が異
常データを受信する時は従装置内のメモリＭＥＭを書き
換える結果となり、従装置の通常処理に大きい影響を与
え、甚だしい時は暴走すると云う欠点があった。In such a slave device, when the slave device receives abnormal data due to causes such as a failure in the transmission line or an error in information from the main device, the memory MEM in the slave device is rewritten. It has the drawback that it has a large effect on the normal processing of the slave device, and in extreme cases can cause the system to go out of control.
（Ｃ）１発明の目的
本発明の目的は従来技術の有する上記の欠点を除去し、
異常データを受信した場合一時入力をガードし、従装置
の定常内部処理を優先することにより従装置の動作安定
度を向上し得る異常データ受信防止回路を提供すること
である。(C)1 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art;
An object of the present invention is to provide an abnormal data reception prevention circuit that can improve the operational stability of a slave device by temporarily guarding input when abnormal data is received and giving priority to steady internal processing of the slave device.
（ｄ）８発明の構成
上記の目的は本発明によれば、主装置からの制御情報を
受信し各種処理を行う従装置にインヒビソト回路及びタ
イマ回路を設け、且つ前記制御情報の最大データ長を予
め設定して置き、前記最大データ長を超えるデータを前
記主装置から受信した場合、前記タイマ回路を駆動し成
る一定時間前記インヒビット回路を動作させて前記従装
置の受信動作を停止ｌ二させることを特徴とする異常デ
ータ受信防止回路を提供することにより達成される。(d) 8 Structure of the Invention According to the present invention, the above object is to provide an inhibit circuit and a timer circuit in a slave device that receives control information from a main device and performs various processes, and to increase the maximum data length of the control information. Set in advance, when data exceeding the maximum data length is received from the main device, the inhibit circuit is operated for a certain period of time by driving the timer circuit to stop the receiving operation of the slave device. This is achieved by providing an abnormal data reception prevention circuit characterized by:
即ち本発明に於いては主装置から受信する制御情報の最
大データ長を予め設定して置き若し受信した制御情報が
此の最大データ長を紹える場合は此の制御情報を誤りと
判定して以後一定時間受信を停止りして従装置を保護し
、従装置の動作安定度の向」−を計るものである。That is, in the present invention, the maximum data length of control information received from the main device is set in advance, and if the received control information introduces this maximum data length, this control information is determined to be an error. After that, reception is stopped for a certain period of time to protect the slave device and to measure the operational stability of the slave device.
（ｅ）０発明の実施例
第２図は従装置内に設けられる本発明に依る異常データ
受信防止回路の一実施例を示す概略図である。(e) 0 Embodiment of the Invention FIG. 2 is a schematic diagram showing an embodiment of an abnormal data reception prevention circuit according to the present invention provided in a slave device.
図中、ＦＦはフリップ・フロップ回路、ＴＩＭはタイマ
回路、Ｇ１、Ｇ２は夫々インヒビソトゲートである。In the figure, FF is a flip-flop circuit, TIM is a timer circuit, and G1 and G2 are inhibit gates.
主装置から従装置に対し送信する制御情報は普通ＤＭＡ
方式によりデータ転送される。即ち主装置からの制御情
報はインヒビソトゲートＧ１経由アドバンストデータリ
ンクコントローラＡＤＬＣに入る。The control information sent from the main device to the slave device is usually DMA.
Data is transferred according to the method. That is, control information from the main device enters the advanced data link controller ADLC via the inhibit gate G1.
アドバンストデータリンクコントローラＡＤＬＣにより
シリアル形式で送られて来る制御情報を受信し、ダイレ
クトメモリアクセスコントローラＤＭＡＣの制御により
メモリＭＥＭに収容される。Control information sent in serial format by the advanced data link controller ADLC is received and stored in the memory MEM under the control of the direct memory access controller DMAC.
制御回路Ｃ０ＮＴは３の様にして主装置から受信した制
御情報をメモリＭＥＭから読み出し従装置としての機能
を実行する。The control circuit C0NT reads the control information received from the main device from the memory MEM as shown in 3 and executes the function as a slave device.
本発明では主装置から受信した制御情報をメモＵ Ｍ
Ｅ Ｍに書き込む前に其のデータ長を制御回路Ｃ０ＮＴ
により検査して規定の最大データ長より長いか否かを判
定し、規定の最大データ長より短い時は其の侭メモリＭ
ＥＭに書き込むが、若し規定の最大データ長より長い時
は周辺機器制御用インタフェイスの機能を有するペリフ
ェラルインターフェイスアダプタＰＩＡを介してフリッ
プ・フロップ回路ＦＦ、及びタイマ回路ＴＩＭをセント
する。フリップ・フロップ回路ＦＦがセットされること
によりインヒビソトゲートＧ１のインヒビソト機能が働
いて受信を停市する。In the present invention, control information received from the main device is stored in a memo U M
Before writing to EM, control circuit C0NT determines the data length.
to determine whether the data length is longer than the specified maximum data length, and if it is shorter than the specified maximum data length, the side memory M
The data is written to EM, but if the data length is longer than the specified maximum data length, the data is written to the flip-flop circuit FF and the timer circuit TIM via the peripheral interface adapter PIA, which has the function of a peripheral device control interface. By setting the flip-flop circuit FF, the inhibit function of the inhibit gate G1 is activated to stop reception.
又タイマ回路ＴＩＭがセントされて計時動作を開始し、
成る一定時間経過するとタイマ回路ＴＩＭはフリップ・
フロップ回路ＦＦをリセットし、インヒビットゲートＧ
１を開き、再び主装置からの受信をイネーブル状態に復
元する。Also, the timer circuit TIM is clocked and starts timing operation,
After a certain period of time has elapsed, the timer circuit TIM flips.
Reset the flop circuit FF and inhibit gate G
1 and restores reception from the main device to the enabled state again.
此の為伝送路等の故障により主装置から異常データを受
信する場合孔れを防止することが可能となる。For this reason, it is possible to prevent a hole when abnormal data is received from the main device due to a failure in the transmission line or the like.
（ｆ）０発明の効果
以上詳細に説明した様に本発明によれば、異常データを
受信した場合一時入力をガードし、従装置の定常内部処
理を優先することにより従装置の動作安定度を向上し得
る異常データ受信防止回路を実現出来ると云う大きい効
果がある。(f) 0 Effects of the Invention As explained in detail above, according to the present invention, when abnormal data is received, the operation stability of the slave device is improved by temporarily guarding the input and giving priority to the steady internal processing of the slave device. This has the great effect of realizing an improved abnormal data reception prevention circuit.
第１図は従装置内に設けられる主装置からの制御情報を
受信する回路の一実施例を示す概略図である。
第２図は従装置内に設けられる本発明に依る異常データ
受信防止回路の一実施例を示す概略図である。
図中、ＤＭＡＣはダイレクトメモリアクセスコントロー
ラ、ＡＤＬＣはアドバンストデータリンクコントローラ
、ＭＥＭはメモリ、Ｃ０ＮＴは制御回路、ＰＩＡはべり
フェラルインターフェイスアダプタ、ＦＦはフリップ・
フロップ回路、ＴＩＭはタイマ回路、Ｇ１、Ｇ２は夫々
インヒビソトゲートである。
￥−２酊FIG. 1 is a schematic diagram showing an embodiment of a circuit provided in a slave device for receiving control information from a master device. FIG. 2 is a schematic diagram showing an embodiment of an abnormal data reception prevention circuit according to the present invention provided in a slave device. In the figure, DMAC is a direct memory access controller, ADLC is an advanced data link controller, MEM is a memory, C0NT is a control circuit, PIA is a ferrule interface adapter, and FF is a flip controller.
The flop circuit, TIM is a timer circuit, and G1 and G2 are inhibit gates. ￥-2 drunkenness
Claims (1)
インヒビット回路及びタイマ回路を設け、且つ前記制御
情報の最大データ長を予め設定して置き、前記最大デー
タ長を超えるデータを前記主装置から受信した場合、前
記タイマ回路を駆動し成る一定時間前記インヒビソト回
路を動作させて前記従装置の受信動作を停止させること
を特徴とする異常データ受信防止回路。A slave device that receives control information from the main device and performs various processes is provided with an inhibit circuit and a timer circuit, and a maximum data length of the control information is set in advance, and data exceeding the maximum data length is transmitted to the main device. 2. An abnormal data reception prevention circuit, characterized in that when the data is received from the slave device, the inhibit circuit is operated for a certain period of time by driving the timer circuit to stop the receiving operation of the slave device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59048818A JPS60192447A (en) | 1984-03-14 | 1984-03-14 | Faulty data reception preventing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59048818A JPS60192447A (en) | 1984-03-14 | 1984-03-14 | Faulty data reception preventing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60192447A true JPS60192447A (en) | 1985-09-30 |
Family
ID=12813794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59048818A Pending JPS60192447A (en) | 1984-03-14 | 1984-03-14 | Faulty data reception preventing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60192447A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5784739A (en) * | 1995-10-16 | 1998-07-28 | Kawada Industries, Inc. | Super-long span suspension bridge |
| US6233626B1 (en) * | 1998-10-06 | 2001-05-15 | Schneider Automation Inc. | System for a modular terminal input/output interface for communicating messaging application layer over encoded ethernet to transport layer |
| US6732191B1 (en) | 1997-09-10 | 2004-05-04 | Schneider Automation Inc. | Web interface to an input/output device |
| US6853867B1 (en) | 1998-12-30 | 2005-02-08 | Schneider Automation Inc. | Interface to a programmable logic controller |
| US7032029B1 (en) | 2000-07-07 | 2006-04-18 | Schneider Automation Inc. | Method and apparatus for an active standby control system on a network |
| US7035898B1 (en) | 1997-09-10 | 2006-04-25 | Schneider Automation Inc. | System for programming a factory automation device using a web browser |
| US7058693B1 (en) | 1997-09-10 | 2006-06-06 | Schneider Automation Inc. | System for programming a programmable logic controller using a web browser |
| US7519737B2 (en) | 2000-07-07 | 2009-04-14 | Schneider Automation Inc. | Input/output (I/O) scanner for a control system with peer determination |
| US8291121B2 (en) | 1997-09-10 | 2012-10-16 | Square D Company | System and method for interfacing with a controller |
-
1984
- 1984-03-14 JP JP59048818A patent/JPS60192447A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5784739A (en) * | 1995-10-16 | 1998-07-28 | Kawada Industries, Inc. | Super-long span suspension bridge |
| US6732191B1 (en) | 1997-09-10 | 2004-05-04 | Schneider Automation Inc. | Web interface to an input/output device |
| US7035898B1 (en) | 1997-09-10 | 2006-04-25 | Schneider Automation Inc. | System for programming a factory automation device using a web browser |
| US7058693B1 (en) | 1997-09-10 | 2006-06-06 | Schneider Automation Inc. | System for programming a programmable logic controller using a web browser |
| US8291121B2 (en) | 1997-09-10 | 2012-10-16 | Square D Company | System and method for interfacing with a controller |
| US6233626B1 (en) * | 1998-10-06 | 2001-05-15 | Schneider Automation Inc. | System for a modular terminal input/output interface for communicating messaging application layer over encoded ethernet to transport layer |
| US6466995B2 (en) | 1998-10-06 | 2002-10-15 | Schneider Automation, Inc. | Messaging application layer over ethernet to transport layer (TCP) communications method and apparatus for a modular terminal input/output system |
| US6853867B1 (en) | 1998-12-30 | 2005-02-08 | Schneider Automation Inc. | Interface to a programmable logic controller |
| US7032029B1 (en) | 2000-07-07 | 2006-04-18 | Schneider Automation Inc. | Method and apparatus for an active standby control system on a network |
| US7519737B2 (en) | 2000-07-07 | 2009-04-14 | Schneider Automation Inc. | Input/output (I/O) scanner for a control system with peer determination |
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