JPH09230788A - Encoding method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease a circuit scale of an encoding device. SOLUTION: An operation core part 11 generates work keys 1-3 by selecting a data key from a first selection part 12 to input thereto, and selecting system keys 1-4 from a second selection part 13 to input thereto. Next, work keys 4-7 are generated by the operation core part 11 by inputting output data of the operation core part 11 and also inputting system keys 5-8. Further, a work key 8 is generated by inputting the output of the operation core part 11. Next, by inputting input data and generated work keys 1-4, encoding processing is performed by the operation core part 11 and its output is inputted. Then, by inputting work keys 5-8, encoding processing is further performed and encoded data are outputted from the operation core part 11. Thus, the operation core part is able to perform key schedule processing and encoding processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encryption method and apparatus for encrypting and outputting plaintext.

[0002]

2. Description of the Related Art It has been conventionally known to encrypt information in order to keep information confidential in communication, recording and the like.
In this encryption, information is encrypted so that it does not make sense, and the encrypted information is transmitted or recorded on a recording medium or the like. Then, the encrypted information is received and decrypted to obtain the original information. Such encryption / decryption is roughly classified into a secret key cryptosystem (conventional key cryptosystem) and a public key cryptosystem. The secret key cryptosystem uses the same key for encryption and decryption, and the encryption side and the decryption side have the same key in secret. On the other hand, the public key cryptosystem is a system in which different keys are used on the encryption side and the decryption side, and the encryption side key is made public, but the decryption side key is not made public.

As one of the conventional key cryptosystems for such an encryption / decryption system, DE, which is a standard system in the United States, is used.
An encryption algorithm of the S (Data Encryption Standard) system is known. In this DES method, the cryptographic algorithm is made public and the cryptographic strength is maintained only by the cryptographic key. Even if a cryptographic algorithm is made public, if it does not have an encryption key, the amount of calculation for decryption will be enormous, and even if a high-speed arithmetic device is used, it is expected to take hundreds or thousands of years or more. Because it is. By the way, basically, encryption is performed by combining transposition for changing the order of characters and substitution for replacing one character with another according to a certain rule. Then, the encryption algorithm and the encryption key indicate in what order characters are to be exchanged and which characters are to be replaced.

By the way, there are various types of cryptographic algorithms, not limited to DES, and a system having higher security and higher speed has been developed. As an example of this, US Pat. No. 4,982,429, US Pat.
The encryption method (MULTI2 method) described in Japanese Patent No. 3,479 and Japanese Patent Laid-Open No. 1-276189 is known. The International Organization for Standardization (ISO) also has an encryption method registered as ISO9979 / 0009 and an encryption use mode registered as ISO / IEC10116.

In the above-mentioned MULTI2 encryption method,
Input data size is 64 bits, output data size is 6
A 4-bit work key of 256-bit size for encryption and a system key of 256-bit size,
It is generated from a 64-bit size data key. Also,
The number of encryption steps is a positive integer step. FIG. 4 shows a schematic configuration of the encryption algorithm in this MULTI2 system.
As shown in FIG. 4, the MULTI2 system generates a 256-bit work key Kw by executing an encryption algorithm using a 64-bit data key Ks and a 256-bit system key J. This is called a key schedule process, and this key schedule process is executed by the cryptographic algorithm executing means C. The generated work key Kw is encrypted by encrypting the plaintext of the 64-bit block supplied to the encryption algorithm execution means F and input. The cryptographic algorithms executed by the cryptographic algorithm executing means C and the cryptographic algorithm executing means F can be the same cryptographic algorithm.

[0006] Such encryption is a basic encryption algorithm of the MULTI2 system. In this method, the distribution of the frequency of occurrence of characters or words is statistically processed in advance, and the character string of the obtained encrypted text is obtained. The plaintext may be estimated (deciphered) by matching the pattern frequency distribution. Therefore, there is a method of creating an encrypted text by calculating the exclusive OR of the encrypted 64-bit cipher block and the next input 64-bit input data. CBC (Ciph
er Block Chaining) mode. In addition, in the above-mentioned cryptographic algorithm execution means F, such a cryptographic algorithm in the CBC mode is executed.

There is a communication system in which the unit of data to be communicated is predetermined such as packet communication, but in the block encryption system in which 64 bits are one block, the number of bits of one block is When a data unit that cannot be divided is input, fractional data that is less than one block is generated. Therefore, the rounding process is OF
Processing is performed in B (Output Feedback) mode. That is, when the data has a fractional part, the fractional part of the data is supplied to the encryption algorithm executing means G,
The OFB mode is set so that the random number generated using the work key Kw is used for encryption. This gives 6
It becomes possible to obtain a ciphertext of data which is less than 64 bits when 4 bits are set as one block. In addition,
The CBC mode and the OFB mode are called the encryption use mode.

FIG. 5 shows a schematic structure of a decoding algorithm in the MULTI2 system. As shown in FIG. 5, 64
A 256-bit work key Kw is generated by executing an encryption algorithm using the 256-bit system key J for the bit data key Ks. The generation of this work key is performed by the key schedule process of the same encryption algorithm as the encryption side. This cryptographic algorithm is executed by the cryptographic algorithm executing means c. The generated work key Kw is supplied to the decryption algorithm executing means f and the input 64-bit ciphertext is decrypted.

In this decryption algorithm, the substitution and transposition algorithms in the encryption algorithm of the encryption algorithm executing means F are performed in the reverse order. The ciphertext encrypted in the OFB mode is supplied to the encryption algorithm executing means g and decrypted by using the random number generated using the work key Kw. As a result, one block of 64-bit ciphertext can be decrypted to obtain a 64-bit block of plaintext. Further, the decryption algorithm executing means f is CBC.
It is designed to perform mode decryption algorithms.

Here, the encryption use mode will be described with reference to FIG. 6. FIG. 6A shows a schematic configuration of encryption / decryption in the CBC mode, and FIG. 6B shows an OFB mode. 2 shows a schematic configuration of encryption / decryption of. In the CBC mode, as shown in FIG. 6A, the i-th plaintext block M (i) is input to the exclusive OR circuit 101, delayed by the register (REG) 103, and fed back by one block. The exclusive OR with the ciphertext block C (i-1) is calculated. The calculated data is encrypted by the encryption algorithm executing means 102 with the work key generated based on the data key Ks. The encrypted i-th ciphertext block C (i) can be expressed as C (i) = EKs (M (i) .EOR.C (i-1)). However, EKs (m) means that m is encrypted with Ks, and EOR indicates that an exclusive OR operation is performed.

Then, the ciphertext block C (i) is transmitted and received at the receiving side. The received ciphertext block C (i) is decrypted by the decryption algorithm executing means 111 using the work key generated based on the data key Ks, and is supplied to the exclusive disjunction circuit 113. The exclusive OR circuit 113 has a register (RE
G) The delayed ciphertext block C (i-1) one block before is input in 112, and the exclusive disjunction of the two is calculated. At this time, the data keys Ks on the transmitting side and the receiving side are equal to each other, whereby the i-th plaintext block M (i) is decrypted by the exclusive OR circuit 113. The i-th plaintext block M (i) can be expressed as follows. M (i) = DKs (C (i) .EOR.C (i-1)) where DKs (c) indicates that Ks decrypts c.

In the OFB mode, the i-th plaintext block M (i) is supplied to the exclusive OR circuit 105 as shown in FIG. 6B. This exclusive OR circuit 105
Is supplied with the output of the cryptographic algorithm executing means 104 which is randomized by the work key generated based on the data key Ks. The cryptographic algorithm execution means 1
The output of 04 is delayed by one block by the register 103 and returned to the encryption algorithm execution means 104 by one block. As a result, the exclusive OR circuit 1
From 05, a ciphertext block C encrypted with a random number
(i) is output.

Then, this ciphertext block C (i) is transmitted and received at the receiving side. The received ciphertext block C (i) is supplied to the exclusive disjunction circuit 114. The exclusive OR circuit 114 is supplied with a randomized output using a work key generated based on the data key Ks in the encryption algorithm executing means 115. The output of the encryption algorithm executing means 115 is delayed by one block in the register (REG) 112 and returned to the encryption algorithm executing means 115. In this case, the random number supplied to the exclusive OR circuit 114 is equal to the random number supplied to the exclusive OR circuit 105, whereby the i-th plaintext block M ( i) is obtained.

FIG. 7 shows a schematic configuration of the encryption / decryption method having the above-described encryption use mode. In this figure, the transmission side is provided with an encryption device for encrypting data, and the encrypted transmission data is transmitted. This encrypted transmission data is propagated through a transmission path such as space and is received by the receiving side. The receiving side is provided with a decryption device, and the decryption device decrypts the transmitted data, restores it to the original data, and outputs it.

The encryption device is Encr which is an encryption algorithm executing means for encrypting the input data (plaintext) inputted.
yptor 102, register 103, CBC mode encryption unit composed of exclusive OR circuit (EX-OR) 101, and Encryptor 104 which is encryption algorithm execution means.
And an exclusive OR circuit (EX-OR) 105
It is composed of an FB mode encryption unit. Encryptor 10 that generates a work key from the data key and system key
6 is also provided in the encryption device. The generated work key is supplied to the Encryptor 102, 104. By the way, Encryptor 102, Encryptor 104, Encryptor
Since 106 can have the same encryption algorithm, one Encryptor can also be used as three Encryptors. The operations of the CBC mode encryption unit and the OFB mode encryption unit are as described above, and will not be repeated here.

The decryption device provided on the receiving side is
Decryptor 111, which is a decryption algorithm executing means for decrypting input received data (ciphertext), a register 112, a CBC mode decryption unit including an exclusive OR circuit (EX-OR) 113, and an encryption algorithm execution Means Encryptor 115 and exclusive OR circuit (EX
-OR) 114 of the OFB mode decoding unit. An Encryptor 116 for generating a work key from the data key and the system key is also provided in the decryption device. The generated work key is Decryptor 111 and En
Supplied to cryptor 115. In addition, Encryptor 11
5. Encryptor 116 can use the same encryption algorithm, so one Encryptor can be used for two Encr
Can also be used as yptor. The operations of the CBC mode decoding unit and the OFB mode decoding unit are the same as described above, and will not be repeated here.

Next, the encryption algorithm of the encryption process of the Encryptor will be described with reference to FIG. FIG. 8 shows an encryption algorithm of the encryption process. The 64-bit width input data is divided into upper 32 bits of data and lower 32 bits of data and input to the four arithmetic stages 130. The input high-order 32-bit data and low-order 32-bit data are subjected to the operation of the function π1 in the first stage of the four-stage operation stage 130. Then, in the second stage, the operation of the function π2 is applied to the output of the first stage. In this case, the second
The work key 1 having a 32-bit width is input to the stage, and the work key 1 is used to perform the operation of the second stage.

Further, in the third stage, the output of the second stage is calculated by the function π3. In this case, the work key 2 and the work key 3 having a 32-bit width are input to the third stage, and the operation is performed using the work key 2 and the work key 3. Subsequently, in the fourth stage, the output of the third stage is subjected to the operation of the function π4. In this case, the work key 4 having a 32-bit width is input to the fourth stage, and the work key 4 is used for the calculation. Further, it is input to the operation stage 131 which performs four operations, and the output of the operation stage 130 is subjected to the operation of the function π1 in the first stage. Then, in the second stage, the operation of the function π2 is applied to the output of the first stage. In this case, the work key 5 having a 32-bit width is input to the second stage, and the work key 5 is used for the calculation.

Further, in the third stage, the output of the second stage is calculated by the function π3. In this case, the work key 6 and the work key 7 having a 32-bit width are input to the third stage, and the operation is performed using the work key 6 and the work key K7. Subsequently, in the fourth stage, the output of the third stage is subjected to the operation of the function π4. In this case, the work key 8 having a 32-bit width is input to the fourth stage, and the work key 8 is used for the calculation. In this way, the 256-bit work key is divided into eight with a 32-bit width (work key 1 to work key 8) and supplied to each operation stage, and the upper 32 bits for which encryption processing has been performed,
Encrypted data having a total of 64-bit width of the lower 32 bits is obtained. Further, the encryption processing of the four operation stages 130 and 131 may be repeated a plurality of times in order to increase the encryption strength. The operation of the function performed in each operation step is a substitution operation that replaces a character with another character according to a certain rule, and a transposition operation that changes the order of characters.

Next, FIG. 9 shows an algorithm of a key schedule process for generating a 256-bit wide work key from a 64-bit wide data key and a 256-bit wide system key. As shown in FIG. 9, the key schedule process is an algorithm in which four operation stages 132 and 133 are two stages and one operation stage 134 is cascade-connected. That is, in the first stage of the first four arithmetic stages 132, the operation of the function π1 is performed on the 64-bit wide data key divided into the upper 32 bits and the lower 32 bits. Next, in the second stage, the operation data of the function π2 is applied to the output data of the first stage using the system key 1 of 32 bit width, and the output of the upper 32 bit width is output as the work key 1. Next, in the third stage, the system key 2 and the system key 3 are added to the output data of the second stage.
Is used to calculate the function π3, and the output of the lower 32 bits is output as the work key 2. Further, in the fourth stage, the output data of the third stage is subjected to the calculation of the function π4 using the system key 4, and the output of the upper 32 bits width is output as the work key 3.

Subsequently, in the first stage of the next four operation stages 133, the output data of the operation stage 132 is subjected to the operation of the function π1 and the output of the lower 32 bits width is output as the work key 4. Next, in the second stage, the output data of the first stage is subjected to the operation of the function π2 by using the system key 5 having the 32-bit width, and the output of the upper 32-bit width is output as the work key 5. Next, in the third stage, the output data of the second stage is subjected to the calculation of the function π3 using the system key 6 and the system key 7, and the output of the lower 32 bits width is output as the work key 6. Further, in the fourth stage, the output data of the third stage is subjected to the calculation of the function π4 by using the system key 8, and the output of the upper 32 bit width is output as the work key 7. Further, in the succeeding arithmetic stage 134, the arithmetic stage 1
The output data of 33 is subjected to the operation of the function π1, and the lower 32
The output of the bit width is output as the work key 8.

[0022]

By the way, in the above-mentioned digital data encryption / decryption system, high speed is required, and it is desired to integrate the encryption device into an LSI. However, although the LSI has been highly integrated recently, the encryption algorithm and the key schedule algorithm have many steps and are complicated as shown in FIGS. 8 and 9, and the circuit scale when the LSI is implemented is large. Become. Therefore, there is a problem that the cost of the LSI increases due to a problem such as yield.

Therefore, an object of the present invention is to provide an encryption method and an encryption device which can execute a predetermined encryption algorithm and a key schedule algorithm with a simple structure.

[0024]

In order to achieve the above object, the encryption method of the present invention comprises a work key generation step of generating a work key by executing an encryption algorithm, and a work key generation step. A cryptographic processing step of creating a ciphertext by performing cryptographic processing of a plaintext with a predetermined cryptographic algorithm using the generated work key, the work key generating step and the ciphertext executed in the cryptographic processing step. The algorithm is executed by circulating the operation in the arithmetic core that executes a part of the cryptographic algorithm a plurality of times.

Further, the encryption apparatus of the present invention is a first selection means for selecting an arithmetic core for executing a part of an encryption algorithm and input data to be arithmetically processed by the arithmetic core, and inputting to the arithmetic core. And second selection means for selecting the key information necessary for the arithmetic operation of the arithmetic core and supplying it to the arithmetic core, and key information for outputting the key information generated by the arithmetic core during execution of the cryptographic algorithm. Output means for executing the cryptographic algorithm to output the output data encrypted by the arithmetic core, and inputting the output data to the first selecting means; the first selecting means; By controlling the second selection means and the key information output means, the work key can be generated by the arithmetic core and the encryption processing can be performed.

According to the encryption method and the encryption device of the present invention as described above, the encryption algorithm can be executed by cyclically using one arithmetic core, so that the encryption process can be performed with a simple structure. It can be carried out. Also,
The algorithm of the key schedule can also be executed by using one arithmetic core that executes the encryption algorithm, so that the encryption process can be performed with a simpler configuration.

[0027]

FIG. 1 is a block diagram showing a configuration of an embodiment of an encryption apparatus of the present invention which realizes an encryption method of the present invention. The configuration of FIG. 1 can execute an encryption algorithm for encryption processing and a key schedule algorithm for generating a work key. In FIG. 1, the arithmetic core unit 11 performs basic arithmetic operations of a cryptographic algorithm and a key schedule algorithm, as will be described later, and the arithmetic core unit 11 is circulated to repeatedly perform arithmetic operations to obtain a cryptographic algorithm and a key schedule. I'm trying to run the algorithm.

A data key having a 64-bit width, 64-bit block input data, and output data calculated by the calculation core unit 11 are input to the first selecting unit 12. The first selection unit 12 receives the control signal from the control unit 10,
Arithmetic core unit 11 by selecting any of the input data
Is being entered. In addition, the second selection unit 13 has 256
Bit system keys are system keys 1-4 and system key 5
The input work is divided into two groups (1 to 8), and the generated 256-bit work keys are divided into two groups, that is, the work keys 1 to 4 and the work keys 5 to 8 and input. The second selection unit 13 selects the key information of any of the input groups according to the control signal of the control unit 10 and supplies the selected key information to the arithmetic core unit 11.

The key information output unit 14 is the arithmetic core unit 11
The work keys that are generated by and are output in time series are work keys 1 to 3 and work keys 4 to 4 under the control of the control unit 10.
7 and the work key 8 are divided and output.
Note that the control unit 10 controls the first selection unit 12 and the second selection unit 13 so that the arithmetic core unit 11 calculates the encryption algorithm of the encryption process and the key schedule algorithm for generating the work key. Ready to run.

Next, the operation of the encryption device shown in FIG. 1 will be described. First, the control unit 10 controls the first selection unit 12 to select the 64-bit wide data key, and the arithmetic core unit. 11 to be input. At the same time, the second selection unit 13 is controlled so that four system keys 1 to 4 each having a 32-bit width are supplied to the arithmetic core unit 11. Then, the arithmetic core unit 11 receives the supplied system key 1
To 4 are used to perform arithmetic operations on the data key to sequentially generate work keys 1 to 3 each having a 32-bit width, and supply the work keys to the key information output unit 14. In this case, the arithmetic core unit 11 performs the arithmetic operation executed by the arithmetic stage 132 shown in FIG.

Next, the 64-bit wide arithmetic output of the arithmetic core unit 11 is selected by the first selecting unit 12, and the four system keys 5 to 8 each having a 32-bit width are selected from the second selecting unit 13 by the arithmetic core unit. The second selection unit 13 is controlled so as to be supplied to 11. As a result, the arithmetic core unit 11
Are the supplied system keys 5-8, each 32 bits wide
By further performing an operation on the fed back operation data of 32 bit width, the work keys 4 to 7 of 32 bit width are sequentially generated to generate the key information output unit 14.
To supply. In this case, the arithmetic core unit 11 performs the arithmetic operation executed by the arithmetic stage 133 shown in FIG.

Subsequently, 3 output from the arithmetic core unit 11
The operation data having a 2-bit width is again selected by the first selection unit 12 and input to the operation core unit 11, and the operation data fed back is subjected to an operation, whereby 3
The 2-bit width work key 8 is generated and the key information output unit 14 is generated.
Is supplied to. In this case, the arithmetic core unit 11 performs the arithmetic operation executed by the arithmetic stage 134 shown in FIG. In this way, the arithmetic core unit 11 is cycled twice and ¼ times to repeatedly perform operations, thereby executing the algorithm of the key schedule shown in FIG. 8 is a key information output unit 14
Will be stored in a register (not shown).

Next, the work keys 1 to 1 thus generated are
An operation performed by the encryption device shown in FIG. 1 will be described as an encryption algorithm of an encryption process for encrypting input data using 8. First, the first selection unit 12 selects input data having a 64-bit width under the control of the control unit 10 and inputs it to the arithmetic core unit 11. At the same time, the second selection unit 13 outputs four work keys 1 each having a 32-bit width out of the work keys having a width of 256 bits generated by the key schedule process.
4 are selected and supplied to the arithmetic core unit 11. As a result, the cryptographic algorithm executed by the operation stage 130 shown in FIG. 8 is executed and output from the operation core unit 11.

Next, the first selection unit 12 is the arithmetic core unit 1
The output data from 1 is selected and input to the arithmetic core unit 11. At the same time, the remaining four work keys 5 to 8 each having a 32-bit width are selected from the 256-bit width work keys generated by the key scheduling process in the second selecting unit 13 and supplied to the arithmetic core unit 11. As a result, the cryptographic algorithm executed by the operation stage 131 shown in FIG. 8 is executed and output from the operation core unit 11. This output data is encrypted data obtained by performing an encryption process on the input data, and may be output as it is. However, in order to increase the encryption strength, the output data is input to the arithmetic core 11 again and the work keys 1 to 8 are used. You may repeat the encryption process as shown in FIG. The control unit 10 controls the switching of the first selection unit 12 and the second selection unit 13 and the control of the key information output unit 14 in the above-described key schedule process and encryption process.

Next, the configuration of the arithmetic core unit 11 is shown in FIG. As shown in this figure, the arithmetic core unit 11 is configured by connecting four arithmetic stages 11-1 to 11-4 in cascade. Then, the operation stage 11- for performing the operation of the first stage function π1
1 has an input terminal 21 for inputting upper 32-bit data of 64-bit width data and an input terminal 22 for inputting lower 32-bit data. Further, the 32-bit width key information input terminal 25 to be supplied to the operation stage 11-2 for performing the function π2 at the second stage and the operation stage 11-3 for performing the operation at the third stage function π3 are supplied. Two 32-bit wide key information input terminals 26 and 27, and a fourth
3 to be supplied to the operation stage 11-4 which performs the operation of the stage function π4
A 2-bit width key information input terminal 28 is provided.

Further, the fourth operation stage 11-4 to 4
An output terminal 23 for outputting the upper 32 bits of the operation data operated by the operation stages and an output terminal 24 for outputting the lower 32 bits are provided. Furthermore,
An output terminal 29 for the operation data of the lower 32 bits output from the first operation stage 11-1 and the second operation stage 11-2.
From the output terminal 30 for the upper 32-bit operation data output from the third operation step 11-3
An output terminal 31 for 2-bit operation data and an output terminal 32 for upper 32-bit operation data output from the fourth operation stage 11-4 are provided.

When executing the key schedule process in the arithmetic core unit 11 as described above, first, the input terminals 21,
A data key having a 64-bit width is divided into two parts, that is, a high-order bit having a 32-bit width and a low-order bit having a 32-bit width, and the data key is input to 22. Further, four system keys 1 to 4 obtained by dividing the 256-bit width system key into eight 32-bit widths are input to the input terminals 25 to 28, respectively. As a result, the arithmetic operations are performed in the arithmetic stages 11-1 to 11-4, and the arithmetic results of the arithmetic stages 11-2 to 11-4 are output from the output terminals 30 to 32 as the work keys 1 to 3.

In this way, in the arithmetic core unit 11, 4
When the calculation of the stage is completed, the calculation data output from the output terminals 23 and 24 are fed back to the input terminals 21 and 24.
22. At this time, 32 to the input terminals 25 to 28
The remaining four system keys 5 to 8 divided into 8 bit widths are respectively input. Then, each operation stage 11-1 to 11
-4, the operation is performed in each operation stage 11-1 to 11-
The calculation result of 4 is output keys 29 to 3 as work keys 4 to 7.
It is output from 2. Further, the operation data output from the output terminals 23 and 24 of the operation core unit 11 are fed back and input to the input terminals 21 and 22, and the first operation stage 1
The calculation of the function π1 is performed in 1-1, and the output terminal 29
Outputs the work key 8. In this way, the processing of the arithmetic core unit 11 is cycled twice and ¼ times, so that the key schedule process for generating the work keys 1 to 8 is executed by the arithmetic core unit 11.

Next, description will be made regarding the case where the arithmetic core unit 11 performs the cryptographic processing. First, the input data of the 64-bit width is input to the input terminals 21 and 22 and the upper bits of the 32-bit width and the high-order bits of the 32-bit width.
It is input after being divided into two lower bits of the bit width. Further, four work keys 1 to 4 obtained by dividing a work key having a 256-bit width into eight into 32-bit width are input to the input terminals 25 to 28, respectively. Thereby, each operation stage 11-1 to 1
Calculation is performed in 1-4, and the calculation data is output to the output terminal 2
It is output from 3, 24.

In this way, in the arithmetic core unit 11, 4
When the calculation of the stage is completed, the calculation data output from the output terminals 23 and 24 are fed back to the input terminals 21 and 24.
22. At this time, 32 to the input terminals 25 to 28
The remaining four work keys 5 to 8 divided into 8 bit widths are respectively input. Thereby, each operation stage 11-1 to 1
The calculation is performed in 1-4, and the encrypted encrypted data is output from the output terminals 23 and 24. Further, in order to increase the encryption strength of the encrypted encrypted data, the encrypted data output from the output terminals 23 and 24 of the arithmetic core unit 11 is fed back and input to the input terminals 21 and 22. In the above, the calculation of the cryptographic algorithm described above is repeatedly performed. In this way, the encryption processing is executed in the arithmetic core unit 11 by the processing of the arithmetic core unit 11 being cycled at least twice.

Next, FIG. 3 shows a flowchart when the arithmetic core unit 11 performs the above-mentioned key schedule process and encryption process. In this flowchart, when the processing of the arithmetic core unit 11 is started, the system key is set in step S10. In this process, the system key input to the second selection unit 13 is selected and supplied to the arithmetic core unit 11. Next, in step S11, the data key is set. In this process, the data key input to the first selection unit 12 is selected and input to the arithmetic core unit 11. Then, the algorithm of the key schedule process shown in FIG. 9 is executed using the system key as the data key input in step S12.

The work key generated by this processing is output from the key information output unit 14 in step S18 and stored in a register (not shown). Then, step S13
The 64-bit input data input to the first selection unit 12 is selected and input to the arithmetic core unit 11, and the generated work key is selected by the second selection unit 13 in step S14. Is supplied to the arithmetic core unit 11,
The encryption processing algorithm shown in FIG. 8 is executed. When this encryption process is completed, the encrypted data is output from the arithmetic core unit 11, and it is determined in step S16 whether or not the arithmetic core unit 11 circulates a predetermined number of times to perform the encryption process. Here, when the calculation which is circulated a predetermined number of times has not ended, it is determined as NO and the process returns to step S13, and the first selection unit 12 calculates the calculation core unit 1
The data output from 1 is selected and input to the arithmetic core unit 11.

Then, in step S14, the encryption algorithm of the encryption process is executed using the work key as described above. When such a calculation is executed by the calculation core unit 11 a predetermined number of times, YES is determined in step S16 and the process proceeds to step S17. And step S
The encrypted data encrypted in step 17 is output, the next 64-bit input data is fetched, and step S13 is performed.
Then, the processing described above is repeated.

As described above, in the present invention, it is sufficient to physically have only one arithmetic core, and input data and key information are switched to this arithmetic core at a predetermined timing according to the processing to be executed. By supplying
Key scheduling processing and encryption processing can be performed. In the above description, 64-bit block input data is generated using 64-bit data key and 256-bit system key to generate 64-bit block encrypted data. The number of bits is not limited and can be any number.

[0045]

Since the present invention is configured as described above, the encryption algorithm can be executed by cyclically using one arithmetic core, and therefore the encryption processing can be performed with a simple configuration. You can Also, the algorithm of the key schedule can be executed by using one arithmetic core that executes the encryption algorithm, so that the encryption process can be performed with a simpler configuration. Therefore, when the encryption device of the present invention is integrated into an LSI,
Since the number of gates can be significantly reduced, the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an encryption device of the present invention which executes an encryption method of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of an arithmetic core according to the present invention.

FIG. 3 is a flowchart executed by an arithmetic core according to the present invention.

FIG. 4 is a diagram showing a conventional encryption algorithm.

FIG. 5 is a diagram showing a conventional decryption algorithm.

FIG. 6 is a diagram showing a configuration of an encryption use mode of a CBC mode and an OFB mode.

FIG. 7 is a diagram showing a configuration of a conventional encryption / decryption system.

FIG. 8 is a diagram showing an encryption algorithm of a conventional encryption process.

FIG. 9 is a diagram showing an algorithm of a conventional key schedule process.

[Explanation of symbols]

10 control unit, 11 arithmetic core unit, 12 first selection unit, 13 second selection unit, 14 key information output unit, 21
22, 25-28 input terminals, 23, 24, 29-32
Output terminal

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Claims (2)

[Claims] 1. A work key generation step of generating a work key by executing a cryptographic algorithm, and a cryptographic process of a predetermined cryptographic algorithm for plain text using a work key generated in the work key generation step. And a cryptographic processing step for creating a ciphertext according to the above, wherein the work key generation step and the cryptographic algorithm executed in the cryptographic processing step are performed in an arithmetic core that executes a part of the cryptographic algorithm a plurality of times. An encryption method characterized by being executed by circulating. 2. An arithmetic core that executes a part of a cryptographic algorithm, a first selection unit that selects input data that is arithmetically processed by the arithmetic core, and inputs the selected input data to the arithmetic core; Second selection means for selecting necessary key information and supplying it to the arithmetic core; key information output means for outputting the key information generated by the arithmetic core during execution of the encryption algorithm; By executing, the output unit that outputs the output data encrypted by the arithmetic core and inputs the output data to the first selecting unit, the first selecting unit, the second selecting unit, and the An encryption device, characterized in that a work key can be generated by the arithmetic core and an encryption process can be performed by controlling the key information output means.