JPH0714842A - Inspection of bump and manufacture of semiconductor device - Google Patents

Inspection of bump and manufacture of semiconductor device

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Publication number
JPH0714842A
JPH0714842A JP14242293A JP14242293A JPH0714842A JP H0714842 A JPH0714842 A JP H0714842A JP 14242293 A JP14242293 A JP 14242293A JP 14242293 A JP14242293 A JP 14242293A JP H0714842 A JPH0714842 A JP H0714842A
Authority
JP
Japan
Prior art keywords
bump
bumps
substrate
volume
inspection method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP14242293A
Other languages
Japanese (ja)
Inventor
Koji Ono
光司 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14242293A priority Critical patent/JPH0714842A/en
Publication of JPH0714842A publication Critical patent/JPH0714842A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To make it possible to measure the volume of each bump of a plurality of bumps with good accuracy and easily. CONSTITUTION:A method of inspecting bumps is a method of controlling the volume of each bump of a plurality of pieces of the bumps 2, which are dispersedly arranged on one substrate 1, for example, a method wherein the surface, on which a plurality of bumps 2 consisting of a Pb/Sn alloy, an In/Pb alloy or the like are provided, of a substrate 1 is pressed 4 by a flat plate parallel to the substrate 1 in a state that the plurality of the bumps 2 are heated 5 at normal temperature or a temperature less than the melting point of a substrate composing the bumps, for example, to crush the plurality of the bumps 2 to a uniform height and thereafter, the bump arrangement surface of the substrate 1 is observed by a microscope from directly over. The method is constituted so as to have a process in which an image observed by the microscope is binarized to distinguish the part 102 of each bump 2 of the plurality of the bumps from a part 101 other than the bump and the volume of each bump 2 is measured by calculating individually the number of pixels of the part 102 of each bump 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は一基板上に多数個分散配
設されるバンプ(バンプ電極)の体積の分布を、所定の
幅に管理するためのバンプの検査方法及び該バンプの検
査方法を含む半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump inspection method and a bump inspection method for controlling a volume distribution of bumps (bump electrodes) arranged in a distributed manner on a substrate to a predetermined width. And a method for manufacturing a semiconductor device including the above.

【0002】近年、LSIは高集積化、高速化が進み、
LSIチップの実装技術もそれに対応して、フリップチ
ップ、MCM(Multi Chip Module) 等の高密度実装がで
きる方法が要求されている。これらの高密度実装になく
てはならないのが、鉛(Pb)/錫(Sn)合金あるい
はインジウム(In)/Pb合金等の、融点が低く且つ
軟らかい金属を用いたバンプである。これらのバンプ
は、非酸化性雰囲気中において融点以上の温度に加熱溶
融され受け手となる配線基板等のパッドに接続される
が、接続後のバンプの形状や体積の違いによってストレ
スに対する強度が異なる。そこで接続の信頼性を確保す
るためには、一基板上に配設されるバンプの体積を或る
範囲内に揃える必要があり、バンプの体積を短時間で容
易に且つ高精度で測定することが可能なバンプの検査方
法が要望されている。
In recent years, LSIs have been highly integrated and become faster,
Corresponding to the LSI chip mounting technology, a method capable of high-density mounting such as flip chip and MCM (Multi Chip Module) is required. Indispensable for these high-density mounting is a bump using a soft metal having a low melting point, such as a lead (Pb) / tin (Sn) alloy or an indium (In) / Pb alloy. These bumps are heated and melted to a temperature equal to or higher than the melting point in a non-oxidizing atmosphere and are connected to a pad such as a wiring board serving as a receiver. Therefore, in order to secure the reliability of the connection, it is necessary to make the volume of the bumps arranged on one substrate within a certain range, and to measure the volume of the bumps easily and with high accuracy in a short time. There is a demand for a bump inspection method capable of performing the above.

【0003】[0003]

【従来の技術】従来のバンプの体積を管理するためのバ
ンプ検査方法においては、段差測定装置やオートホーカ
ス装置によりバンプの高さのみの測定がなされていた。
2. Description of the Related Art In a conventional bump inspection method for controlling the volume of a bump, only the height of the bump is measured by a step measuring device or an auto-focusing device.

【0004】しかしバンプには、高さが等しくても、拡
がり寸法の相違により体積が異なるものがあるため、高
さの測定のみではバンプの体積の管理が不十分になる。
そのため、バンプの高さのみを測定する従来のバンプ検
査方法によってバンプの体積を管理した場合には、バン
プの体積のばらつき(分布)の幅が大きくなって、例え
ば半導体チップをチップに配設された前記Pb合金等の
バンプを介し配線基板等のパッド上に溶着接続した際、
バンプ材料の上記Pb合金等の量の不足によって接続の
耐ストレス強度の低下を生じたり、またバンプ材料の量
の過剰によって隣接電極間の短絡を生じたりして、接続
の信頼性や歩留りが低下するという問題があった。
However, even if the bumps have the same height, some bumps have different volumes due to the difference in the spread dimension, and therefore the volume control of the bumps becomes insufficient only by measuring the height.
Therefore, when the volume of the bump is managed by the conventional bump inspection method that measures only the height of the bump, the width of the variation (distribution) of the volume of the bump becomes large, and for example, a semiconductor chip is mounted on the chip. When it is welded and connected to a pad such as a wiring board through a bump of the Pb alloy or the like,
The reliability of the connection and the yield are deteriorated because the stress resistance strength of the connection is lowered due to the insufficient amount of the Pb alloy or the like of the bump material, and the short circuit between the adjacent electrodes is caused due to the excessive amount of the bump material. There was a problem of doing.

【0005】[0005]

【発明が解決しようとする課題】そこで本発明は、バン
プの体積を精度良く、且つ容易に測定することが可能な
バンプの検査方法及びこのバンプ検査方法を含む半導体
装置の製造方法を提供し、バンプの体積の管理精度を高
めて、バンプを介し半導体チップ等が高密度に実装され
るLSI等の製造歩留りや信頼性を向上せしめることを
目的とする。
SUMMARY OF THE INVENTION Therefore, the present invention provides a bump inspection method and a semiconductor device manufacturing method including the bump inspection method capable of accurately and easily measuring the volume of the bump. An object of the present invention is to improve the management accuracy of the volume of bumps and improve the manufacturing yield and reliability of LSIs and the like in which semiconductor chips and the like are mounted at high density via bumps.

【0006】[0006]

【課題を解決するための手段】上記課題の解決は、一基
板上に複数個分散配設されるバンプの体積を管理するバ
ンプの検査方法であって、例えばPb/Sn合金或いは
In/Pb合金等からなる複数のバンプを有する基板面
を該基板に平行な平板で、該複数のバンプを例えば常温
または該バンプ物質の融点未満の温度に加熱した状態で
押圧して該複数のバンプを均一な高さに押し潰した後、
該基板のバンプ配設面を真上から観察し、例えば該観察
像を2値化して該複数のバンプ各々のバンプの部分とバ
ンプ以外の部分とを区別し、各々のバンプ部分の画素数
を個々に計数する等によって該バンプの専有面積を測定
し、該専有面積に基づいてバンプの体積の検査を行う本
発明によるバンプの検査方法、若しくは、外部接続用バ
ンプを有する半導体装置の製造方法であって、複数のバ
ンプ配設用パッドの形成された半導体基板上に絶縁膜を
形成し、該絶縁膜に該複数のパッドを個々に表出する開
孔を形成し、該複数の開孔部にそれぞれのパッドに個々
に接続するバンプを形成した後、前記バンプの検査方法
により個々のバンプの体積を検査する工程を含む本発明
による半導体装置の製造方法よって達成される。
A solution to the above problem is a bump inspection method for controlling the volume of a plurality of bumps dispersedly arranged on one substrate. For example, a Pb / Sn alloy or an In / Pb alloy is used. The surface of the substrate having a plurality of bumps made of, for example, is a flat plate parallel to the substrate, and the plurality of bumps are pressed at a normal temperature or a temperature lower than the melting point of the bump material to press the plurality of bumps uniformly. After crushing to height,
The bump placement surface of the substrate is observed from directly above, and the observed image is binarized, for example, to distinguish the bump portion of each of the plurality of bumps from the portion other than the bump, and determine the number of pixels of each bump portion. A bump inspection method according to the present invention, in which the area occupied by the bumps is measured by individually counting, and the volume of the bumps is inspected based on the area occupied, or a method for manufacturing a semiconductor device having bumps for external connection And forming an insulating film on a semiconductor substrate on which a plurality of pads for arranging bumps are formed, and forming openings for individually exposing the plurality of pads in the insulating film, This is achieved by the method for manufacturing a semiconductor device according to the present invention, which includes the step of inspecting the volume of each bump by the above-mentioned bump inspection method after forming the bumps individually connected to the respective pads.

【0007】[0007]

【作用】以下に本発明の原理を説明する。図1は本発明
の原理説明図で、(a) 〜(c) は各工程の模式図である。
The principle of the present invention will be described below. FIG. 1 is a diagram illustrating the principle of the present invention, and (a) to (c) are schematic diagrams of each step.

【0008】バンプの体積を直接図ることは非常に難し
い。そこで本発明においては、図1(a) に示すように、
バンプ2の配設されている基板である例えば半導体チッ
プ1上に上記半導体チップ1に平行な平板即ち平行板3
を配置し、図1(b) に示すように、前記平行板3により
バンプ2上を半導体チップ1に垂直な力4によって押圧
し、バンプ2の高さh′を強制的に一定の高さに揃えて
しまう。その際、下地の半導体チップ1にダメージを与
えないように、基板加熱5によりバンプ2を融点近い温
度に加熱しバンプを軟らかくしてやることがバンプ材質
の種類によっては望ましい。
It is very difficult to directly measure the volume of the bump. Therefore, in the present invention, as shown in FIG.
On the semiconductor chip 1 which is the substrate on which the bumps 2 are arranged, for example, a flat plate parallel to the semiconductor chip 1, that is, a parallel plate 3
1b, the parallel plate 3 presses the bumps 2 on the bumps 2 with a force 4 perpendicular to the semiconductor chip 1 to force the height h'of the bumps 2 to a constant height. Will be aligned with. At this time, it is desirable to heat the bumps 2 to a temperature close to the melting point by the substrate heating 5 to soften the bumps so as not to damage the underlying semiconductor chip 1 depending on the type of bump material.

【0009】このように高さを一定にすることにより、
3次元的な体積の相違は、2次元的な平面積の相違に精
度良く置き換えられる。従ってこのバンプ平面積を顕微
鏡等を用い光学的に測定することによりバンプ体積の分
布を高精度で知ることが可能になる。
By keeping the height constant in this way,
The three-dimensional difference in volume can be accurately replaced with the two-dimensional difference in plane area. Therefore, the distribution of the bump volume can be known with high accuracy by optically measuring the plane area of the bump using a microscope or the like.

【0010】また本発明の方法においては、上記潰され
たバンプの平面積の測定を、図1(c) に示すように、バ
ンプの真上からの光学的観察像を画像処理で2値化して
バンプ2の部分102 とその他の部分101 とを区別し、バ
ンプの部分2の画素数を計数する方法を用いて、容易且
つ高速にできるようにした。
In the method of the present invention, the plane area of the crushed bump is measured by binarizing an optical observation image from directly above the bump by image processing as shown in FIG. 1 (c). The portion 102 of the bump 2 and the other portion 101 are distinguished from each other, and a method of counting the number of pixels of the portion 2 of the bump is used so that it can be performed easily and at high speed.

【0011】以上により本発明によれば、基板上に分散
配設される複数のバンプの体積の分布を容易に精度良く
管理することが可能になる。従って、バンプを有するチ
ップ構造の半導体装置の製造工程に上記バンプの検査方
法を含めた本発明の半導体装置の製造方法を適用するこ
とにより、バンプを介し半導体チップが高密度に実装さ
れるLSI等の製造歩留りや信頼性の向上が図れる。
As described above, according to the present invention, it is possible to easily and accurately manage the volume distribution of the plurality of bumps dispersedly arranged on the substrate. Therefore, by applying the semiconductor device manufacturing method of the present invention including the bump inspection method to the manufacturing process of a semiconductor device having a chip structure having bumps, an LSI or the like in which semiconductor chips are mounted at high density via the bumps, etc. The manufacturing yield and reliability of can be improved.

【0012】[0012]

【実施例】以下本発明のバンプの検査方法を、図2に示
す工程説明図を参照し、一実施例について具体的に説明
する。また、本発明の半導体装置の製造方法を図3及び
図2の工程説明図を参照し具体的に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the bump inspection method of the present invention will be specifically described below with reference to the process explanatory diagram shown in FIG. Further, a method of manufacturing a semiconductor device of the present invention will be specifically described with reference to the process explanatory diagrams of FIGS.

【0013】図2(a) 参照 本発明の方法により、例えば半導体基板(チップ)11上
に、直径 100μm、高さ50μm程度の設計寸法を有する
複数個のPb−5wt%Sn合金バンプ12A 、12B 等が
配設された試料17を、例えば〔窒素(N2)+水素(H2)〕か
らなる非酸化性雰囲気が維持されている処理室16内に挿
入する。なお、この処理室16の試料配置部上には、試料
基板即ち半導体基板の上面に平行な平面状の押圧用ガラ
ス板13が上下動可能に設けられ、処理室16の例えば天井
部には試料加熱用の赤外線ランプ15が配設されている。
Referring to FIG. 2 (a), a plurality of Pb-5 wt% Sn alloy bumps 12A, 12B having a design dimension of a diameter of 100 μm and a height of about 50 μm are formed on a semiconductor substrate (chip) 11 by the method of the present invention. The sample 17 provided with the above components is inserted into the processing chamber 16 in which a non-oxidizing atmosphere of, for example, [nitrogen (N 2 ) + hydrogen (H 2 )] is maintained. A flat pressing glass plate 13 parallel to the upper surface of the sample substrate, that is, the semiconductor substrate is provided on the sample placement portion of the processing chamber 16 so as to be vertically movable, and the sample is provided on the ceiling of the processing chamber 16, for example. An infrared lamp 15 for heating is provided.

【0014】図2(b) 参照 次いで、上記赤外線ランプ15により前記押圧用ガラス板
13を透してPb−5wt%Sn合金バンプ12を、その融
点(約 300℃)未満の融点に近い温度の例えば280℃に
加熱し、バンプ12の可塑性を増した状態で、前記押圧用
ガラス板13を試料の半導体基板(チップ)11面に平行に
降下させて、総てのバンプ12A 、12B 等に上部から押圧
を加え、総てのバンプ12A 、12B 等の高さが、例えばバ
ンプ設計寸法の高さ(h) の1/2の25μm程度の高さ(1
/2 h )になるように押し潰す。
Referring to FIG. 2 (b), the pressing glass plate is then driven by the infrared lamp 15.
The Pb-5 wt% Sn alloy bump 12 through 13 is heated to a temperature close to its melting point (about 300 ° C.), for example, 280 ° C. to increase the plasticity of the bump 12, and the pressing glass is used. The plate 13 is dropped in parallel to the semiconductor substrate (chip) 11 surface of the sample, and pressure is applied from above to all the bumps 12A, 12B, etc., so that the height of all the bumps 12A, 12B, etc. The height of about 25 μm, which is 1/2 of the dimension height (h) (1
/ 2 h).

【0015】ここで、押圧用の平行板は上記ガラス板に
限られるものではなく、バンプ材料が付着しない材質で
且つバンプ材料の付着しない表面状態を維持しているも
のであれば、金属でも絶縁物でも差支えない。
Here, the pressing parallel plate is not limited to the above glass plate, and may be made of metal as long as it is a material to which the bump material does not adhere and maintains a surface state where the bump material does not adhere. It doesn't matter if it's a thing.

【0016】図2(c) 参照 次いで、赤外線ランプ15を切断しバンプ12A 、12B 等の
加熱を停止し、次いで前記押圧用ガラス板13を上昇さ
せ、バンプ12A 、12B 等上から引き離した後、試料17を
処理室16から取り出す。
Next, referring to FIG. 2 (c), the infrared lamp 15 is cut to stop heating the bumps 12A, 12B, etc., and then the pressing glass plate 13 is raised to separate it from the bumps 12A, 12B, etc. The sample 17 is taken out of the processing chamber 16.

【0017】図2(d) 参照 次いで、この試料17の表面を半導体基板11に垂直な上部
から顕微鏡を用いて観察し、この観察像を画像処理して
2値化し、バンプ12A 〜12F の部分112A〜112Fとその他
の基板11の部分111 とを区別させる。
Next, referring to FIG. 2D, the surface of the sample 17 is observed with a microscope from the upper side perpendicular to the semiconductor substrate 11, and this observed image is image-processed and binarized to obtain the bumps 12A to 12F. A distinction is made between 112A-112F and the other portion 111 of the substrate 11.

【0018】そして、各々のバンプ12A 〜12F 等の画素
数を個々に数え、各々のバンプ12A〜12F 等の体積を算
出する。ここで、予めバンプ体積の管理値を所定の分布
幅に決めておき、管理値から外れるバンプは不良バンプ
として検出し、上記バンプを有する半導体チップの良否
の判断がなされる。この実施例においては、バンプ体積
が極度に小さくなっているバンプ12B が不良バンプとし
て容易に且つ精度良く判定される。
Then, the number of pixels of each of the bumps 12A to 12F etc. is individually counted, and the volume of each of the bumps 12A to 12F etc. is calculated. Here, the control value of the bump volume is set in advance to a predetermined distribution width, bumps that deviate from the control value are detected as defective bumps, and the quality of the semiconductor chip having the bumps is determined. In this embodiment, the bump 12B having an extremely small bump volume is easily and accurately determined as a defective bump.

【0019】上記実施例においては、本発明を最も多用
されているPb−5wt%Sn合金バンプを用いて説明
したが、本発明は上記Pb/Sn合金のバンプに限らず
In/Pb合金等の軟らかく且つ融点の低い金属による
バンプを用いる際にも勿論適用可能である。
In the above embodiments, the present invention has been described using the Pb-5 wt% Sn alloy bump which is most frequently used. However, the present invention is not limited to the above Pb / Sn alloy bump, but may be an In / Pb alloy or the like. It is of course applicable when using a bump made of a metal that is soft and has a low melting point.

【0020】また、上記バンプの検査方法を含む前記P
b/Sn合金バンプを有するチップ構造の半導体装置
は、例えば下記の方法により製造される。 図3(a) 参照 先ず、図示しない半導体回路が形成され、表面にアルミ
ニウム(Al)合金等からなる複数の外部接続用パッド
22A 、22B 等が形成された半導体基板21上に被覆絶縁膜
23を形成し、この被覆絶縁膜23に前記外部接続用パッド
22A 、22B 等を表出する開孔24A 、24B 等を形成した
後、この基板上に、通常通りスパッタ法により、バリア
メタルの下地になる厚さ1000〜3000Å程度のチタン(T
i)膜25を形成し、次いでバリアメタルとなる厚さ1000
〜5000Å程度のニッケル(Ni)膜26を形成する。
Further, the P including the above-mentioned bump inspection method
A semiconductor device having a chip structure having b / Sn alloy bumps is manufactured by the following method, for example. See FIG. 3 (a). First, a semiconductor circuit (not shown) is formed, and a plurality of external connection pads made of aluminum (Al) alloy or the like are formed on the surface.
A coating insulating film is formed on the semiconductor substrate 21 on which 22A, 22B, etc. are formed.
23, and the pad for external connection is formed on the covering insulating film 23.
After forming the openings 24A, 24B, etc. exposing the 22A, 22B, etc., titanium (T:
i) Forming the film 25 and then forming a barrier metal with a thickness of 1000
A nickel (Ni) film 26 of about 5000 Å is formed.

【0021】図3(b) 参照 次いで、通常のフォトリソグラフィ手段により前記Ni
膜26をパターニングし、前記開孔24A 、24B 等の上部に
バリアメタルとなるNi膜パターン26A 、26B等を形成
する。
Next, referring to FIG. 3 (b), the Ni is formed by a conventional photolithography means.
The film 26 is patterned to form Ni film patterns 26A, 26B and the like serving as barrier metal on the openings 24A, 24B and the like.

【0022】図3(c) 参照 次いで、通常通りこの基板上にレジスト膜27を形成し、
このレジスト膜27に前記Ni膜パターン26A 、26B 等を
表出するバンプ接続用開孔28A 、28B 等を形成し、次い
で、前記Ti膜25を陰極にし、通常の電気めっき手段に
より前記バンプ接続用開孔28A 、28B 等上に例えば高さ
50μm程度の前記Pb/Sn合金バンプ29A 、29B 等を
形成する。
Next, as shown in FIG. 3 (c), a resist film 27 is formed on this substrate as usual,
Bump connection holes 28A, 28B etc. for exposing the Ni film patterns 26A, 26B etc. are formed in the resist film 27, and then the Ti film 25 is used as a cathode and the bump connection by the usual electroplating means. Above the openings 28A, 28B, etc.
The Pb / Sn alloy bumps 29A, 29B having a thickness of about 50 μm are formed.

【0023】図3(d) 参照 次いで、レジスト膜27を除去した後、前記Ni膜パター
ン26A 、26B 等をマスクにしてTi膜25のパターニング
を行い、個々のバンプ29A 、29B 等を別々に分離する。
Next, after removing the resist film 27, the Ti film 25 is patterned by using the Ni film patterns 26A and 26B as a mask to separate the individual bumps 29A and 29B from each other. To do.

【0024】図3(e) 参照 次いで、前記バンプ検査方法の実施例と同様に、この基
板上に基板と平行な平板上の押圧用ガラス板13を圧接
し、前記バンプ29A 、29B 等を25μm程度の均一な厚さ
に押し潰す。
Next, as in the embodiment of the bump inspection method, a pressing glass plate 13 on a flat plate parallel to the substrate is pressed onto this substrate, and the bumps 29A, 29B and the like are 25 μm thick. Crush to a uniform thickness.

【0025】図3(f) 参照 次いで、押圧用ガラス板13を除去した後、前記バンプ検
査方法と同様に、この基板上面の直上部からの顕微鏡等
による観察像を例えば2値化し、潰されたバンプ29A 、
29B 等の平面積を測定することにより、基板上に配設さ
れている総てのバンプの体積の分布を検査し、本発明に
係るバンプを有する半導体装置の製造工程が完了する。
Next, as shown in FIG. 3 (f), after the pressing glass plate 13 is removed, the image observed from directly above the upper surface of the substrate by a microscope or the like is binarized and crushed as in the bump inspection method. Bump 29A,
By measuring the plane area of 29B or the like, the distribution of the volume of all bumps arranged on the substrate is inspected, and the manufacturing process of the semiconductor device having bumps according to the present invention is completed.

【0026】[0026]

【発明の効果】以上説明のように本発明によれば、基板
上に多数個分散配設されるバンプを一定の高さに押し潰
すことにより、3次元的なバンプの体積の変動をそのま
ま2次元的なバンプの平面積の変動に置き換え、その平
面積を測定することによって、個々のバンプの体積の変
動を容易に且つ高精度に検出することが可能となる。ま
た本発明によれば、上記平面積の測定をバンプの光学的
観察像を2値化しその画素数を計数することにより高速
で容易に且つ精度良く行うことができる。
As described above, according to the present invention, three-dimensional bump volume fluctuations can be directly maintained by crushing a large number of bumps dispersedly arranged on a substrate to a certain height. By replacing with the dimensional variation of the plane area of the bump and measuring the plane area, it becomes possible to easily and highly accurately detect the variation of the volume of each bump. Further, according to the present invention, the plane area can be measured at high speed easily and accurately by binarizing the optical observation image of the bump and counting the number of pixels.

【0027】以上により本発明によれば、基板上に多数
個分散配設されるバンプの体積の分布を容易に精度良く
管理することが可能になり、バンプを介し半導体チップ
が高密度に集積実装されるLSI等の製造歩留りや信頼
性の向上が図れる。
As described above, according to the present invention, it is possible to easily and accurately manage the volume distribution of the bumps that are dispersedly arranged on the substrate, and the semiconductor chips can be integrated and mounted at high density via the bumps. It is possible to improve the manufacturing yield and reliability of the manufactured LSI and the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.

【図2】 本発明に係るバンプ検査方法の一実施例の工
程説明図
FIG. 2 is a process explanatory view of an embodiment of a bump inspection method according to the present invention.

【図3】 本発明に係る半導体装置の製造方法の一実施
例の工程説明図
FIG. 3 is a process explanatory view of an embodiment of a method of manufacturing a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 バンプ 3 平行板 4 垂直な力 5 基板加熱 11 半導体基板(チップ) 12A 〜12F Pb−5wt%Sn合金バンプ 13 押圧用ガラス板 15 赤外線ランプ 16 処理室 17 試料 111 2値化画像の基板の部分 112A〜112F 2値化画像のバンプの部分 h バンプの高さ h′押し潰しにより強制的に揃えられたバンプの高さ 1 semiconductor chip 2 bumps 3 parallel plate 4 vertical force 5 substrate heating 11 semiconductor substrate (chip) 12A to 12F Pb-5wt% Sn alloy bump 13 glass plate for pressing 15 infrared lamp 16 processing chamber 17 sample 111 binarized image Substrate part 112A to 112F Bump part of binarized image h Bump height h'Bump height forcibly aligned by crushing

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 一基板上に複数個分散配設されるバンプ
の体積を管理するバンプの検査方法であって、 該複数のバンプを有する基板面を該基板に平行な平板で
押圧して該複数のバンプを均一な高さに押し潰した後、 該基板のバンプ配設面を真上から観察し、該観察像から
得られる当該バンプの専有面積に基づいて該バンプの体
積の検査を行うことを特徴とするバンプの検査方法。
1. A bump inspection method for controlling the volume of a plurality of bumps dispersedly arranged on one substrate, comprising: pressing a substrate surface having the plurality of bumps with a flat plate parallel to the substrate. After crushing the plurality of bumps to a uniform height, the bump-arranged surface of the substrate is observed from directly above, and the volume of the bump is inspected based on the area occupied by the bump obtained from the observed image. A bump inspection method characterized by the above.
【請求項2】 前記バンプの専有面積の測定が、前記観
察像を2値化して該複数のバンプ各々のバンプ部分とバ
ンプ以外の部分とを区別し、各々のバンプ部分の画素数
を個々に計数することによってなされることを特徴とす
る請求項1記載のバンプの検査方法。
2. The area occupied by the bumps is measured by binarizing the observed image to distinguish the bump portion of each of the plurality of bumps from the portion other than the bumps, and the number of pixels of each bump portion is individually measured. The bump inspection method according to claim 1, wherein the bump inspection method is performed by counting.
【請求項3】 前記バンプを均一な高さに押しつぶす押
圧に際して、該バンプを該バンプ物質の融点未満の温度
に加熱することを特徴とする請求項1または2記載のバ
ンプの検査方法。
3. The bump inspection method according to claim 1, wherein the bump is heated to a temperature lower than a melting point of the bump material when the bump is pressed to a uniform height.
【請求項4】 外部接続用バンプを有する半導体装置の
製造方法であって、 複数のバンプ配設用パッドの形成された半導体基板上に
絶縁膜を形成し、該絶縁膜に該複数のパッドを個々に表
出する開孔を形成し、該複数の開孔部にそれぞれのパッ
ドに個々に接続するバンプを形成した後、前記請求項1
または2または3記載のバンプの検査方法により個々の
バンプの体積を検査する工程を含むことを特徴とする半
導体装置の製造方法。
4. A method of manufacturing a semiconductor device having bumps for external connection, comprising forming an insulating film on a semiconductor substrate on which a plurality of pads for bump placement are formed, and forming the plurality of pads on the insulating film. The opening which is individually exposed is formed, and bumps which are individually connected to the respective pads are formed in the plurality of opening portions, and then the openings are formed.
Alternatively, a method of manufacturing a semiconductor device, including the step of inspecting the volume of each bump by the bump inspection method described in 2 or 3.
JP14242293A 1993-06-15 1993-06-15 Inspection of bump and manufacture of semiconductor device Withdrawn JPH0714842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14242293A JPH0714842A (en) 1993-06-15 1993-06-15 Inspection of bump and manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14242293A JPH0714842A (en) 1993-06-15 1993-06-15 Inspection of bump and manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0714842A true JPH0714842A (en) 1995-01-17

Family

ID=15314966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14242293A Withdrawn JPH0714842A (en) 1993-06-15 1993-06-15 Inspection of bump and manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0714842A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8918950B2 (en) 2005-09-05 2014-12-30 Samsung Electronics Co., Ltd. Mobile robot system having a plurality of exchangeable work modules and method of controlling the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8918950B2 (en) 2005-09-05 2014-12-30 Samsung Electronics Co., Ltd. Mobile robot system having a plurality of exchangeable work modules and method of controlling the same

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