JPH0444296A - Multi-layer substrate incorporating semiconductor chips - Google Patents
Multi-layer substrate incorporating semiconductor chipsInfo
- Publication number
- JPH0444296A JPH0444296A JP2149416A JP14941690A JPH0444296A JP H0444296 A JPH0444296 A JP H0444296A JP 2149416 A JP2149416 A JP 2149416A JP 14941690 A JP14941690 A JP 14941690A JP H0444296 A JPH0444296 A JP H0444296A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- semiconductor chips
- notch
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004806 packaging method and process Methods 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 238000007789 sealing Methods 0.000 abstract description 2
- 229920003002 synthetic resin Polymers 0.000 abstract description 2
- 239000000057 synthetic resin Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子部品等を高密度に実装し、各種電子機器
に使用される半導体チップ内蔵多層基板に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multilayer substrate with built-in semiconductor chips on which electronic components and the like are mounted at high density and used in various electronic devices.
従来の技術
一般に電子部品を基板に実装する場合、第２図に示すよ
うに、半導体チップ１ｏを始め、多くの電子部品１１が
一部の受動素子を除いて基板１２の表面に実装されてい
るのが一般的である。2. Description of the Related Art Generally, when electronic components are mounted on a board, as shown in FIG. 2, many electronic components 11, including a semiconductor chip 1o, are mounted on the surface of a board 12, excluding some passive elements. is common.
発明が解決しようとする課題
しかしながら、このような構造を有する基板１２では搭
載する半導体チップ１ｏの数に応じて基板１２の面積を
大きくして行く必要があり、実装密度が向上せず、製品
の小型化を著しく損ねるという課題があった。Problems to be Solved by the Invention However, in the substrate 12 having such a structure, it is necessary to increase the area of the substrate 12 according to the number of semiconductor chips 1o to be mounted, which does not improve the packaging density and reduces the product quality. There was a problem in that it significantly impeded miniaturization.
本発明はこのような従来の課題を解決するものであり、
搭載する半導体チップの数が増大しても基板面積を拡大
することなく高密度に実装できる優れた半導体チップ内
蔵多層基板を提供することを目的とするものである。The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent multilayer board with built-in semiconductor chips that can be mounted at high density without increasing the board area even when the number of mounted semiconductor chips increases.
課題を解決するための手段
本発明は上記目的を達成するために、少なくとも２枚の
両面基板または多層基板に半導体チップを７エイスアツ
プにて搭載し、かつその搭載部において半導体チップ表
面が基板表面と同一平面を構成できるような深さを有す
る切り欠き部を備え、かつ半導体チップおよび基板の表
面に接続用ノ（ンプを有する第一の基板と、その第一の
基板との接続続面の反対面に電子部品を搭載した第二の
基板とを前記接続用バンプを介して一体に積層したもの
である。Means for Solving the Problems In order to achieve the above object, the present invention mounts semiconductor chips on at least two double-sided substrates or multilayer substrates in a 7-eighth-up manner, and in the mounting portion, the surface of the semiconductor chip is the same as the surface of the substrate. A first substrate that has a notch with a depth that allows them to form the same plane and has a connection knob on the surface of the semiconductor chip and the substrate, and the opposite side of the connection connection surface between the first substrate and the first substrate. A second board having electronic components mounted on its surface is integrally laminated via the connection bumps.
作 用
したがって本発明によれば、基板に半導体チップをフェ
イスアップにて搭載し、かつその搭載部において半導体
チップ表面が基板表面と同一平面を構成できるような深
さを有する切り欠き部を備え、さらに半導体チップおよ
び基板の表面に接続用バンプを設けた第一の基板と、第
一の基板と接続する面の反対面に電子部品を搭載した第
二の基板とを接続用バンプを介して接続し、一体構造と
しているために、実装密度の向上に大きく作用し、した
がって電子機器製品の小型化にも大いに役立つものであ
る。また第三またはそれ以上の上記と同じ構造を有する
基板を積層して接続していくことにより、さらにその効
果は大きくなる。Therefore, according to the present invention, a semiconductor chip is mounted face-up on a substrate, and the mounting portion includes a cutout portion having a depth such that the surface of the semiconductor chip is flush with the surface of the substrate, Furthermore, the first board, which has connection bumps on the surface of the semiconductor chip and the board, is connected to the second board, which has electronic components mounted on the opposite side of the surface to be connected to the first board, via the connection bumps. However, since it has an integral structure, it greatly improves the packaging density, and is therefore very useful for downsizing electronic equipment products. Further, by stacking and connecting a third or more substrates having the same structure as above, the effect becomes even greater.
実施例
以下、本発明の一実施例につｂて図面ｔＳ照して説明す
る。EXAMPLE Hereinafter, an example of the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の構成を示すものであシ、図
において、１はその両面または内部に回路２が形成され
次第−の基板であシ、その一部に切シ欠き部３が設けら
れている。４は切シ欠き部３にフェイスアップで搭載さ
れた半導体チップ、６は同一平面を構成している第一の
基板１および半導体チップ、４０表面に形成されている
接続用バンプである。両面ま几は内部に回路６を有する
第二の基板７と第一の基板１は接続用バンプ５を介して
積層され、電気的に接続されている。８はエポキシ樹脂
等の合成樹脂よシなるコート材で、第一の基板１と第二
の基板７を接続する時にその接続画および切シ欠き部３
を封止することにより、さらに信頼性を向上することが
できるものである。FIG. 1 shows the structure of an embodiment of the present invention. In the figure, 1 is a substrate after a circuit 2 is formed on both sides or inside thereof, and a notch is formed in a part of the substrate. 3 is provided. 4 is a semiconductor chip mounted face-up in the notch 3; 6 is the first substrate 1 and the semiconductor chip forming the same plane; and connection bumps 40 formed on the surface. The second substrate 7, which has a circuit 6 inside, and the first substrate 1 are laminated and electrically connected via connection bumps 5. Reference numeral 8 is a coating material such as synthetic resin such as epoxy resin, which is used to coat the connection image and cutout portion 3 when connecting the first substrate 1 and the second substrate 7.
By sealing it, reliability can be further improved.
なお、図中の４ａけ第一の基板１の外表面に搭載された
半導体チップ、４ｂは第二の基板７の外表面に搭載され
た半導体チップであり、９はその他の電子部品である。In the figure, 4a is a semiconductor chip mounted on the outer surface of the first substrate 1, 4b is a semiconductor chip mounted on the outer surface of the second substrate 7, and 9 is other electronic components.
この実施例において、半導体チップ４は第一の基板１の
切シ欠き部３に搭載されている几めに第二の基板７を接
続用バンプ６を介して第一の基板１に接続したとき第一
の基板１と第二の基板７によって構成される多層基板の
内部に内蔵され几状態となる。さらに搭載する半導体チ
ップの数が増加した場合、上記し几実施例と同様の構成
とすることにより、多くの半導体チップを多層基板の内
部に内蔵することができる。In this embodiment, when the semiconductor chip 4 is mounted on the notch 3 of the first substrate 1 and the second substrate 7 is connected to the first substrate 1 via the connection bumps 6, It is built inside a multilayer substrate constituted by the first substrate 1 and the second substrate 7 and is kept in a closed state. Furthermore, when the number of semiconductor chips to be mounted increases, many semiconductor chips can be built inside the multilayer substrate by using the same configuration as in the above-mentioned embodiment.
このように上記実施例は、半導体チップ４を第一の基板
１に設けられ几切り欠き部３に搭載し、第一の基板１と
第二の基板７を接続用バンプ６を介して接続することに
よって半導体チップ内蔵多層基板を構成しており、半導
体チップの数が増加しても基板の面積を拡大することな
く実装密度を高めることができるという利点分有する。In this way, in the above embodiment, the semiconductor chip 4 is mounted on the first substrate 1 in the cutout 3, and the first substrate 1 and the second substrate 7 are connected via the connection bumps 6. This constitutes a multilayer substrate with built-in semiconductor chips, and has the advantage that even if the number of semiconductor chips increases, the packaging density can be increased without increasing the area of the substrate.
なお、半導体チップの実装密度を高める定めに第三の基
板、第四の基板にも同様の手段によシ切シ欠き部を設け
、そこに半導体チップと搭載し積層することも可能であ
り、さらに同一基板面に複数の切り欠き部を設は複数の
半導体チップを搭載することもできる。In addition, in order to increase the packaging density of semiconductor chips, it is also possible to provide cutouts in the third and fourth substrates by the same means and mount and stack the semiconductor chips therein. Furthermore, by providing a plurality of cutouts on the same substrate surface, a plurality of semiconductor chips can be mounted.
発明の効果
本発明は上記実施例より明らかなように、第一の基板の
一部に切シ欠き部と設け、その切り欠き部に半導体チッ
プと搭載し、かつ第一の基板と半導体チップの表面と同
一平面上に構成し、第一の基板と半導体チップの表面に
接続用バンプを形成させ、その接続用バンプを介して第
一の基板と第二の基板を接続して一体構造として半導体
チップ内蔵多層基板と構成し九ものであシ、半導体チッ
プの数が増加しても基板の面積を大きくする必要がなく
、実装密度を高めることができ、し九がって電子機器製
品を著しく小型化できるという効果を有するものである
。Effects of the Invention As is clear from the above embodiments, the present invention provides a notch in a part of a first substrate, a semiconductor chip is mounted in the notch, and a connection between the first substrate and the semiconductor chip is provided. Connecting bumps are formed on the surfaces of the first substrate and the semiconductor chip, and the first substrate and the second substrate are connected via the connecting bumps to form a semiconductor integrated structure. It is constructed with a multilayer board with built-in chips, so even if the number of semiconductor chips increases, there is no need to increase the area of the board, and the packaging density can be increased. This has the effect of being downsized.
第１図は本発明の一実施例における半導体チップ内蔵多
層基板の要部断面図、第２図は従来の電子部品実装用の
多層基板の要部断面図である。
１・・・・・・第一の基板、３・・・・・・切シ欠き部
（搭載部）、４・・・・・・半導体チップ、６・・・・
・・接続用バンプ、７・・・・・・第二の基板、９・・
・・・・電子部品。
代理人の氏名 弁理士 粟 野 重 孝 ほか１名１−
劉＾基犠
１−−一牙りＩＸ墨１亙
９− 貧）評品FIG. 1 is a sectional view of a main part of a multilayer board with a built-in semiconductor chip according to an embodiment of the present invention, and FIG. 2 is a sectional view of a main part of a conventional multilayer board for mounting electronic components. DESCRIPTION OF SYMBOLS 1...First board, 3...Notch part (mounting part), 4...Semiconductor chip, 6...
...Connection bump, 7...Second board, 9...
...Electronic parts. Name of agent: Patent attorney Shigetaka Awano and 1 other person1-
Liu Ji Sacrifice 1--Ichigari IX Sumi 1-9- Poor) Recommended item
Claims (1)
ップとフェイスアップにて搭載し、かつその搭載部にお
いて前記半導体チップ表面が前記基板表面と同一平面を
構成できるような深さを有する切り欠き部を備え、かつ
前記半導体チップおよび前記基板の表面に接続用バンプ
を有する第一の基板と、その第一の基板との接続画の反
対面に電子部品を搭載した第二の基板とを前記接続用バ
ンプを介して一体に積層した半導体チップ内蔵多層基板
。The semiconductor chip is mounted face-up on at least two double-sided substrates or multilayer substrates, and the mounting portion includes a notch portion having a depth such that the surface of the semiconductor chip is flush with the surface of the substrate. , and a first substrate having connection bumps on the surface of the semiconductor chip and the substrate, and a second substrate having electronic components mounted on the opposite surface of the connection image with the first substrate, and the connection bumps A multilayer board with built-in semiconductor chips that are laminated together via a multilayer substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149416A JPH0444296A (en) | 1990-06-07 | 1990-06-07 | Multi-layer substrate incorporating semiconductor chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149416A JPH0444296A (en) | 1990-06-07 | 1990-06-07 | Multi-layer substrate incorporating semiconductor chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0444296A true JPH0444296A (en) | 1992-02-14 |
Family
ID=15474641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2149416A Pending JPH0444296A (en) | 1990-06-07 | 1990-06-07 | Multi-layer substrate incorporating semiconductor chips |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0444296A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05192519A (en) * | 1992-01-18 | 1993-08-03 | Ngk Insulators Ltd | Solid-liquid separator |
| JP2003234439A (en) * | 2002-02-07 | 2003-08-22 | Sony Chem Corp | Insulative resin composite |
| JP2005142178A (en) * | 2003-11-04 | 2005-06-02 | Cmk Corp | Multilayer printed wiring board with built-in electronic component |
| JP2009224616A (en) * | 2008-03-17 | 2009-10-01 | Shinko Electric Ind Co Ltd | Electronic component built-in board and method of manufacturing the same, and semiconductor device |
| KR101274460B1 (en) * | 2011-11-22 | 2013-06-18 | 삼성전기주식회사 | Semiconductor package and manufacturing method threrof |
| US8892258B2 (en) | 2011-04-29 | 2014-11-18 | Raytheon Company | Variable strength magnetic end effector for lift systems |
| US8942846B2 (en) | 2011-04-29 | 2015-01-27 | Raytheon Company | System and method for controlling a teleoperated robotic agile lift system |
| US8977388B2 (en) | 2011-04-29 | 2015-03-10 | Sarcos Lc | Platform perturbation compensation |
| US9314921B2 (en) | 2011-03-17 | 2016-04-19 | Sarcos Lc | Robotic lift device with human interface operation |
| US9616580B2 (en) | 2012-05-14 | 2017-04-11 | Sarcos Lc | End effector for a robotic arm |
| US9789603B2 (en) | 2011-04-29 | 2017-10-17 | Sarcos Lc | Teleoperated robotic system |
-
1990
- 1990-06-07 JP JP2149416A patent/JPH0444296A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05192519A (en) * | 1992-01-18 | 1993-08-03 | Ngk Insulators Ltd | Solid-liquid separator |
| JPH0817899B2 (en) * | 1992-01-18 | 1996-02-28 | 日本碍子株式会社 | Solid-liquid separator |
| JP2003234439A (en) * | 2002-02-07 | 2003-08-22 | Sony Chem Corp | Insulative resin composite |
| JP2005142178A (en) * | 2003-11-04 | 2005-06-02 | Cmk Corp | Multilayer printed wiring board with built-in electronic component |
| JP2009224616A (en) * | 2008-03-17 | 2009-10-01 | Shinko Electric Ind Co Ltd | Electronic component built-in board and method of manufacturing the same, and semiconductor device |
| US9314921B2 (en) | 2011-03-17 | 2016-04-19 | Sarcos Lc | Robotic lift device with human interface operation |
| US8892258B2 (en) | 2011-04-29 | 2014-11-18 | Raytheon Company | Variable strength magnetic end effector for lift systems |
| US8942846B2 (en) | 2011-04-29 | 2015-01-27 | Raytheon Company | System and method for controlling a teleoperated robotic agile lift system |
| US8977398B2 (en) | 2011-04-29 | 2015-03-10 | Sarcos Lc | Multi-degree of freedom torso support for a robotic agile lift system |
| US8977388B2 (en) | 2011-04-29 | 2015-03-10 | Sarcos Lc | Platform perturbation compensation |
| US9533411B2 (en) | 2011-04-29 | 2017-01-03 | Sarcos Lc | System and method for controlling a teleoperated robotic agile lift system |
| US9789603B2 (en) | 2011-04-29 | 2017-10-17 | Sarcos Lc | Teleoperated robotic system |
| US8901718B2 (en) | 2011-11-22 | 2014-12-02 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor package and manufacturing method thereof |
| US9070693B2 (en) | 2011-11-22 | 2015-06-30 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor package and manufacturing method thereof |
| KR101274460B1 (en) * | 2011-11-22 | 2013-06-18 | 삼성전기주식회사 | Semiconductor package and manufacturing method threrof |
| US9616580B2 (en) | 2012-05-14 | 2017-04-11 | Sarcos Lc | End effector for a robotic arm |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6777787B2 (en) | Semiconductor device with warp preventing board joined thereto | |
| KR100535181B1 (en) | Semiconductor chip package having decoupling capacitor and manufacturing method thereof | |
| KR960002762A (en) | Low Noise Multilayer Chip Package | |
| JPH0444296A (en) | Multi-layer substrate incorporating semiconductor chips | |
| US5406230A (en) | Chip type oscillator and oscillation circuit using this oscillator | |
| JP2006339277A (en) | Substrate for connection and manufacturing method thereof | |
| JP3081786B2 (en) | High frequency semiconductor device | |
| JPS6175558A (en) | Hybrid integrated circuit device | |
| KR100833184B1 (en) | Stacked semiconductor package | |
| JP7131933B2 (en) | Packages for semiconductor devices and semiconductor devices | |
| KR20110091186A (en) | Semiconductor chip and stacked semiconductor package having the same | |
| JPH02146792A (en) | Semiconductor device package structure | |
| KR20040057492A (en) | Multi chip package and method for manufacturing the same | |
| JPH05335695A (en) | Single in-line module | |
| KR20010018945A (en) | Semiconductor package | |
| JPH08250650A (en) | Semiconductor device | |
| JP2001085597A (en) | Semiconductor package | |
| JPH0613535A (en) | Electronic part mounting apparatus | |
| JPH02199859A (en) | Electronic component device and manufacture thereof | |
| KR0173931B1 (en) | Substrate for stack chip package having center bonding pad | |
| JPH05259376A (en) | Semiconductor device | |
| JPH02210858A (en) | Semiconductor device | |
| JP2002368186A (en) | Semiconductor device | |
| JPH04124867A (en) | Semiconductor package | |
| JPH05226518A (en) | Hybrid integrated circuit device |