JP4261921B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit for facilitating a test in a test using a built-in logic self-test mechanism.
[0002]
[Prior art]
Details of the technique of the scan-based built-in self-test method (hereinafter referred to as logic BIST (Built-in-self-Test)) using random numbers as test data is disclosed in Japanese Patent Laid-Open No. Hei 5-241882 (Patent Document 1). Reference is made to Japanese Patent No. 2711492 (Patent Document 2).
[0003]
US Pat. No. 6,070,261 (Patent Document 3) describes a technique in which a test period of a logic BIST is divided into several phases, and a test circuit embedded in the circuit is switched in each phase. As a result, it is possible to disperse the bias of the branch processing in the circuit.
[0004]
Japanese Patent No. 3052937 (Patent Document 4) devises a technique relating to the deletion of the number of signal lines for transmitting a mode signal and a test signal transmitted by an encoder.
[0005]
[Patent Document 1]
JP-A-5-241882 [Patent Document 2]
Japanese Patent No. 2711492 [Patent Document 3]
US Pat. No. 6,070,261 [Patent Document 4]
Japanese Patent No. 3052937 [0006]
[Problems to be solved by the invention]
In the logic BIST, there is a case where a sufficient failure detection rate cannot be obtained because the test data is a pseudo random number. In particular, encoders and circuits with nested conditional branch processing have a problem in that the activation frequency of conditional branch destinations is biased in tests using pseudorandom numbers, resulting in inactive branch processing and untested circuits remaining. is there.
[0007]
As a result of the technique of USP 6,070,261, in order to improve the test efficiency and test quality with respect to the specific logic in the circuit, the bias of the activation frequency is distributed, but here the test point insertion (Test Point Insertion) , TPI) technology. TPI is a technique in which a gate level netlist is once subjected to a failure simulation to analyze controllability and observability, and a test circuit is inserted at a location where controllability and observability are poor. However, in such a case, the circuit speed is deteriorated due to TPI, and in some cases, logical compression is required again.
[0008]
Japanese Patent No. 3052937 devises a technique for deleting the number of signal lines for transmitting a mode signal and a test signal transmitted by an encoder, but it is not a technique for facilitating a test using logic BIST pseudo-random test data.
[0009]
An object of the present invention is to improve test efficiency in a semiconductor integrated circuit based on logic BIST by narrowing down random number candidates applied to the encoding conditions or decoding conditions of an encoder or decoder when pseudo-random numbers are given to test data. And to improve test quality.
[0010]
[Means for Solving the Problems]
To achieve the above object, according to the present invention, a semiconductor integrated circuit having a test arrangement according to scan-based built-in self-test method has at least one output and a plurality of inputs, the outputs of said plurality of input A one-hot encoder determined by the combination, a logic for supplying data to the input of the one-hot encoder to realize the function of the semiconductor integrated circuit, at least one sequential circuit composed of a scan flip-flop, sending data of the sequential circuit, or select the data to the logic sends, and a selector to be outputted to the one-hot encoder, the selector, the test by scan-based built-in self-test method, the sequential circuit select the transmission data is output to the one-hot encoder, the sequential circuit, liked During testing with built-in self-test method of Nbesu is characterized by generating only one hot data corresponding to the branch condition of the one-hot encoder.
[0011]
In the semiconductor integrated circuit, a pseudo-random number is given to test data for a conditional branch processing circuit having a description in which if-else conditions expressed by an encoder or decoder or a register transfer level, which is an original function of the circuit, are nested and connected. When activated, a sequential circuit for limiting the combination of input signals to be applied to the encoder or decoder or the nested conditional branch processing is provided as an auxiliary circuit, which is activated by a pseudo-random number applied when the logic BIST is performed. This makes it easy to activate the encoder or decoder, or the nested conditional branch processing, which has been difficult to achieve, and improves the test efficiency.
[0012]
Also, according to the present invention, a semiconductor integrated circuit having a test arrangement according to scan-based built-in self-test method has at least one output and a plurality of inputs, the output is determined by a combination of said plurality of input In order to realize the functions of the encoder and the semiconductor integrated circuit, the logic for supplying data to the input of the encoder and the output of the scan flip-flop are used as inputs, and the scan-based incorporation for the cascade type conditional branch processing during testing by self-test method, the test decoder for data output as none of the conditional branch is activated, sending data of the test decoder, or select the data to the logic sends the and a selector for outputting to the encoder, the selector, the scan-based built-in self-test method The test is characterized in that selects and outputs the transmission data of the test decoder to the encoder.
[0013]
In the semiconductor integrated circuit, a pseudo-random number is given to test data for a conditional branch processing circuit having a description in which if-else conditions expressed by an encoder or decoder or a register transfer level, which is an original function of the circuit, are nested and connected. When this is done, data narrowed down to a combination of input signals to be applied to the encoder or decoder or nested conditional branch processing is supplied, and activation is difficult due to the pseudo-random number applied when the logic BIST is performed. The encoder or the decoder or the nested conditional branch processing can be activated easily, and the test efficiency can be improved.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment of a semiconductor integrated circuit according to claim 1.
Here, a sequential circuit for generating 16-state encoding conditions of the one-hot encoder is added to a one-hot encoder that performs 4-bit output from 16-bit input even when a logic BIST pseudo-random number is applied. Yes.
[0015]
Reference numeral 101 denotes a sequential circuit provided for testing, which is composed of a 4-bit status register and has 16 states. Reference numeral 102 denotes a one-hot encoder to be tested, which generates a 4-bit output signal after inputting 16 bits. Reference numeral 103 denotes a selector for switching the input of the encoder 102 to the output signal from the sequential circuit 101 during the test, and lbisten 105 is a test enable signal of the logic BIST. Reference numeral 104 denotes logic for realizing an original circuit function for controlling the input of the encoder 102.
[0016]
FIG. 2 shows an example in which the one-hot encoder 102 in FIG. 1 is described in Verilog HDL (Verilog Hardware Description Language).
[0017]
In this example, the combinations of inputs of the one-hot encoder 102 are 2 <16> in the case of 16-bit data, 65536, and if the test data of the logic BIST is a true random number, The establishment that matches the encoding condition is 16/65536, and it falls into a case that does not satisfy any of the conditions even under the pseudo random number by the actual logic BIST, and only the circuit activated by the default condition of the Verilog HDL description shown in FIG. Tested, others are almost inactive and difficult to test. If the “ENC_OUT” signal is a control signal for the peripheral circuit, it will have a significant adverse effect on the testability of the peripheral circuit.
[0018]
FIG. 3 is an example in which the sequential circuit 101 of FIG. 1 is described in Verilog HDL. In this example, only one-hot data corresponding to the branch condition of the one-hot encoder in FIG. 2 is generated. Since this one-hot data is used as a branch condition of the one-hot encoder 102 during the test, the probability of matching the encoding condition is governed by the 16 states sent from the 4-bit register constituting the sequential circuit 101. Even when the hot encoder 102 always matches one of the 16 encoding conditions and the pseudo-random test data is applied, the bias of the activation frequency of the encoding condition is suppressed, and the test efficiency and test quality are improved. improves. Here, the status register of the sequential circuit 101 is configured by a scan register, and in the logic BIST test, pseudo-random test data is transmitted through the scan mechanism.
[0019]
FIG. 4 shows an embodiment of the semiconductor integrated circuit according to claim 2.
Here, a test decoder for generating 16-state encoding conditions of the one-hot encoder is added even if a logic BIST pseudo-random number is applied to a one-hot encoder that performs 4-bit output from 16-bit input. Yes.
[0020]
Reference numeral 401 denotes a scan register, and reference numeral 402 denotes a test decoder provided for testing, which outputs 16-bit one-hot data from the 4-bit scan register 401. Reference numeral 403 denotes an encoder to be tested, which generates a 4-bit output signal after inputting 16 bits. Reference numeral 404 denotes a selector for switching the input of the encoder 403 to the output of the decoder 402 during a test, and lbisten 406 is a test enable signal of the logic BIST. Reference numeral 405 denotes logic for realizing an original circuit function for controlling the input of the encoder 403. Since the branch condition of the encoder 403 is uniquely determined by the output of the decoder 402 during the logic BIST test, testability is greatly improved. The scan register 401 transmits pseudo-random test data via a scan mechanism in the logic BIST test.
[0021]
FIG. 5 shows a conditional expression for providing a test decoder for cascade-type conditional branch processing such as if-else so that any conditional branch is activated even when a pseudo-random number of logic BIST is applied. This is an example in which a test decoder output is arranged. FIG. 5A shows the Verilog HDL code before arranging the test decoder output of claim 2, and FIG. 5B shows the Verilog HDL code after arranging the test decoder in the conditional expression. Here, the test decoder is determined by the lower 2 bits of the existing register “q”. This is a test enable signal of the “lbisten” logic BIST in the figure.
[0022]
The conditional branching process in FIG. 5A is performed when the signals “condition0”, “condition2”, and “condition3” of the branching condition are generated by a logic circuit as shown in FIG. If the test data is assumed to be a true random number, it is extremely difficult to make the condition true by applying the pseudo-random number.
[0023]
The register “q” is composed of scan cells in the gate-level netlist after logic synthesis, and pseudo-random test data is output from the logic BIST pseudo-random number generator through the scan mechanism. Even if the test data is assumed to be a true random number, the conditional branch can be determined by a 2-bit signal of “q”, so the testability is greatly improved.
[0024]
The present invention relates to a test function (BIST) incorporated in an IC, and provides a semiconductor integrated circuit in which a test circuit is surely tested while reducing a test time.
[0025]
Previously, this test used random numbers to test circuits such as encoders, but there was a part that left all the circuits to be tested by randomness. was there. That is, there are too many random number candidates and there is a circuit under test that has a high probability of not satisfying the condition.
[0026]
In the present invention, in order to solve the above problems, the test is performed by narrowing down to the random number candidates necessary for the circuit under test, so that the test time can be shortened and all the circuits under test are connected. Now you can test for sure.
[0027]
【The invention's effect】
As described above in detail, the semiconductor integrated circuit according to claim 1 is a conditional branching process based on a description in which if-else conditions expressed at an encoder or decoder or register transfer level that are inherent in the circuit are nested and connected. When the logic BIST is tested, the circuit is tested by the output signal of the sequential circuit that generates data that matches the encoding condition, the decoding condition, or the activation condition of the conditional branch processing of the encoder or decoder or the conditional branch processing circuit. Therefore, even for pseudo-random test data, the bias of activation frequency of the encoder or decoder or conditional branch processing circuit is suppressed, and activation is easy for any conditional branch, and the test efficiency and test quality To improve.
[0028]
Further, in the semiconductor integrated circuit according to the second aspect, the conditional branch processing circuit according to the description in which the if-else condition expressed at the register transfer level is nested and concatenated is included in the logic BIST. At the time of the test, since the test is performed by the output signal of the test decoder that generates data that matches the encoding condition, the decoding condition, or the activation condition of the conditional branch processing of the encoder or decoder or the conditional branch processing circuit, Even for test data, the bias of the activation frequency of the encoder or decoder or the conditional branch processing circuit is suppressed, the activation is easy for any conditional branch, and the test efficiency and test quality are improved. Further, since the input of the test decoder is supplied from a register provided for realizing the original function of the semiconductor integrated circuit, the overhead of the area due to the design for testability can be suppressed.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention.
FIG. 2 is an example diagram in which a one-hot encoder is described in Verilog HDL.
FIG. 3 is an example diagram in which a sequential circuit is described in Verilog HDL.
FIG. 4 is a second embodiment of a semiconductor integrated circuit according to the present invention.
FIG. 5 provides a test decoder for cascade-type conditional branch processing such as if-else, and tests the conditional expression so that the conditional branch is activated even when a pseudo-random number of logic BIST is applied. It is the example figure which has arrange | positioned the decoder output for.
FIG. 6 is an example diagram of a logic circuit.
[Explanation of symbols]
101 Sequential circuit 102 provided for testing One-hot encoder 103 to be tested 103 Selector 104 Logic 105 lbisten
401 Scan register 402 Decoder for test 403 Encoder to be tested 404 Selector 405 Logic 406 lbisten

Claims (2)

In a semiconductor integrated circuit equipped with a scan-based built-in self-test test mechanism,
At least one output and several inputs and one-hot encoder the output is determined by a combination of the plurality of inputs,
In order to realize the function of the semiconductor integrated circuit, logic for supplying data to the input of the one-hot encoder ;
At least one sequential circuit composed of scan flip-flops;
Sending data of the sequential circuit, or select the data to the logic sends, and a selector to be outputted to the one-hot encoder,
The selector during the test by scan-based built-in self-test method is to select the transmission data of the sequential circuit to output to the one-hot encoder,
The sequential circuit during the test by scan-based built-in self-test method, the semiconductor integrated circuit and generates only one hot data corresponding to the branch condition of the one-hot encoder. In a semiconductor integrated circuit equipped with a scan-based built-in self-test test mechanism,
At least one output and a plurality of input, and an encoder to which the output is determined by a combination of the plurality of inputs,
Logic for supplying data to the input of the encoder to realize the function of the semiconductor integrated circuit;
For test that uses the output of the scan flip-flop as an input and outputs data so that all of the conditional branches are activated during the test based on the scan-based built-in self-test for the cascade-type conditional branch processing A decoder;
Sending data of the test decoder, or select the data to the logic sends, and a selector to be outputted to the encoder,
The selector during the test by scan-based built-in self-test method, a semiconductor integrated circuit, characterized in that selects and outputs the transmission data of the test decoder to the encoder.

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