JP2000305743A - Controller and picture outputting device and power source/clock control method for controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a controller in a waiting state. SOLUTION: Memories 33 and 34 in a controller 30 are provided with supply control circuits 37 and 38 for memories which control the supply of a power source PW and a clock signal CLK. When any access to the memories 33 and 34 is not performed in a fixed time or more, the supply control circuits 37 and 38 for the memories interrupt the supply of the power source PW and the clock signal CLK to the memories 33 and 34 while leaving one part. Also, a picture processing circuit 36 in the controller 30 is provided with a supply control circuit 39 for a processing circuit which controls the supply of the power source PW and the clock signal CLK. When any access to the picture processing circuit 36 is not performed in a fixed time or more, this supply control circuit 39 for the processing circuit interrupts the supply of the power source PW and the clock signal CLK to the picture processing circuit 36 while leaving one part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a controller, an image output device, and a power / clock control method for a controller, and more particularly, to a controller and an image output device for reducing power consumption, and to reducing power consumption. The present invention relates to a controller power / clock control method for achieving the above.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a schematic configuration of a conventional page printer. As shown in FIG. 6, the printer 110 includes a printing mechanism (printer engine) 120 and a controller 130.

The controller 130 has a CPU (Central
Processing Unit) 131, memory management circuit 132, memories 133 and 134, and interface management circuit 135
And an image processing circuit 136. CP
U131 is connected to the memory management circuit 132 via the CPU bus.
It is connected to the. The memory management circuit 132 controls the memory 1
33, 134, an interface management circuit 135, and an image processing circuit 136.

The memories 133 and 134 store data and read out the stored data based on instructions from the memory management circuit 132. Image processing circuit 1
36 generates output data for the printing mechanism 120 to perform printing based on the data input from the memory management circuit 132, and outputs the output data to the printing mechanism 120. Memory 133,
The power source PW and the clock signal CLK are always supplied to the printer 134 and the image processing circuit 136 when the power of the printer 10 is on.

[0005] A host computer 140 such as a personal computer is connected to the interface management circuit 135. The interface management circuit 135 receives input data from the host computer 140 and
33 and 133. The input data includes, in addition to the data for printing, a status confirmation command for confirming various states of the printer 10.

[0006] When the controller 130 receives input data for printing from the host computer 140 via the interface management circuit 135, the controller 130 converts the input data for printing into output data that can be printed by the printing mechanism 120. Convert. The printing mechanism 120 includes the controller 1
Printing is performed on printing paper based on the output data from 30.

[0007]

As can be seen from the above description, the memories 133 and 134 and the image processing circuit 13
The power supply PW and the clock signal CLK are always supplied to 6. However, the image processing circuit 136 actually performs processing only for a limited time immediately before the printer 10 performs printing, and does not perform processing during other times.

However, for the image processing circuit 136,
Regardless of whether this processing is performed or not, the power supply PW and the clock signal CLK are constantly supplied, and the image processing circuit 136 consumes a large amount of power even though the processing is not performed.

The same applies to the memories 133 and 134. The time when the CPU 131 accesses the memories 133 and 134 is limited to immediately before printing or when returning job data for a status confirmation command to the host computer 140. At other times, no access is received.

However, the memories 133 and 134 are constantly supplied with the power supply PW and the clock signal CLK irrespective of whether or not such accesses are received. Memory 1
33 and 134 consume a lot of power.

The present invention has been made in view of the above problems, and has as its object to provide a controller that suppresses power consumption in a memory and an image processing circuit. Another object of the present invention is to provide a printer in which power consumption is suppressed by using such a controller.

[0012]

In order to solve the above-mentioned problems, a controller according to the present invention controls at least a part of supply of a power supply and a clock signal to at least one of a storage device and an image processing circuit for a predetermined time. It is characterized by having a supply stop control circuit that stops when it does not operate. That is, if the storage device does not operate for a certain period of time,
At least a part of the supply of the power supply and the clock signal to the storage device is stopped. If the image processing circuit does not operate for a certain period of time, at least a part of the supply of the power and the clock signal to the image processing circuit is stopped. Such supply stop control may be performed only for the storage device, may be performed only for the image processing circuit, or may be performed for both. This makes it possible to reduce the power consumption of the controller.

Further, such a supply stop control circuit may be provided inside a storage device or an image processing device for performing such supply stop control, or may be provided separately from the storage device and the image processing device. Good.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention is to provide a supply stop control circuit for controlling supply and stop of a power supply and a clock signal inside a memory and an image processing circuit. When these memories and image processing circuits do not operate for a certain period of time or more, the supply of the power supply and the clock signal is stopped except for a part.
This will be described in more detail below.

FIG. 1 is a block diagram showing a schematic configuration of a printer according to a first embodiment of the present invention. As shown in FIG. 1, the printer 10 includes a printing mechanism (printer engine) 20 and a controller 30. The printer 10 is a page printer, and constitutes an image output device in the present embodiment. Printing mechanism 20
Constitute a drawing mechanism in the present embodiment.

The main function of the controller 30 is to receive input data for printing from a host computer 15 such as a personal computer and to convert the input data into output data that can be printed by the printing mechanism 20. The printing mechanism 20 prints on printing paper based on output data from the controller 30.

The controller 30 includes a CPU 31, a memory management circuit 32, memories 33 and 34, an interface management circuit 35, and an image processing circuit 36. The CPU 31 constitutes a central processing unit that performs various processes in the present embodiment. This CPU 31
It is connected to the memory management circuit 32 via the PU bus. The memory management circuit 32 is connected to the memories 33 and 34, the interface management circuit 35, and the image processing circuit 36. In the present embodiment, the memory management circuit 32 and the interface management circuit 35 are ASIC (Application Sp
ecific IC).

The memories 33 and 34 include a memory management circuit 32
Based on the access from, data is stored and the stored data is read. This memory 33,
Reference numeral 34 denotes a storage device according to the present embodiment. The memories 33 and 34 are provided with a power supply PW and a clock signal CL.
Memory supply stop control circuits 37, 3 for controlling the supply of K
8 is provided. This memory supply stop control circuit 37,
38 independently manages the time, and when the time during which the memories 33 and 34 are not operating exceeds a certain value, the power supply PW and the operation clock signal CLK supplied to the memories 33 and 34 are partially left unremoved. Cut off. That is, the memories 33 and 34
If no access has been made for a certain period of time, the memories 33 and 34 enter the sleep mode.

When the memory management circuit 32 makes some access and the memories 33 and 34 need to operate, the power supply PW and the operation clock signal CL are renewed.
The operation is started by fetching K. That is, the memory 3
Release the sleep mode of 3, 34.

In the present embodiment, the power supply PW of the memories 33 and 34 performed by the memory supply stop control circuits 33 and 34
And the clock signal CLK are controlled by the memories 33 and 3
4 are performed independently. That is, only the memory 33 is set to the sleep mode,
Sleep mode is canceled. Also, the memory 34
Only for the case, the sleep mode is set or the sleep mode is canceled. However, the memory 33 and the memory 34 are integrated, and the power supply PW and the clock signal CLK
May be controlled.

The image processing circuit 36 includes a memory management circuit 32
The print mechanism 20 generates output data for performing printing based on the data input from the printer, and outputs the output data to the print mechanism 20. Further, the image processing circuit 36 includes a processing circuit supply stop control circuit 39. The processing circuit supply stop control circuit 39 independently manages the time and controls the image processing circuit 3.
When the non-operating time of step 6 exceeds a certain value, the power supply PW and the operation clock signal CLK supplied to the image processing circuit 36 are cut off by themselves, except for a part. In other words, when the treatment in the image processing circuit 36 has not been performed for a certain time or more,
The image processing circuit 36 enters a sleep mode.

Then, when data is sent from the memory management circuit 32 and the image processing circuit 36 needs to operate, the power supply PW and the operation clock signal CLK are fetched again and the operation is started. That is, the image processing circuit 3
6 is released from the sleep mode.

The host computer 15 is connected to the interface management circuit 35. The interface management circuit 35 receives input data for printing from the host computer 15 and stores it in the memories 33, 33. The interface management circuit 35 also receives a status confirmation command from the host computer 15. This status confirmation command is a command for transmitting the status of the printer 10 to the host computer 15. For example, the status confirmation command includes the printer 10
There is a command for inquiring about the amount of paper, the amount of toner, etc. Upon receiving these instructions, the CPU 31 accesses the memory 33 or the memory 34 and checks the amount of paper and the amount of toner.
The result job data is transmitted to the host computer 15.

FIG. 2 is a flowchart showing the processing of the memory supply stop control circuit 37 provided in the memory 33 and the processing of the memory supply stop control circuit 38 provided in the memory 34. This processing is independently performed by each of the memory supply stop control circuit 37 and the memory supply stop control circuit 38.

As shown in FIG. 2, when the power of the printer 10 is turned on, the memory supply stop control circuits 37, 3
8 starts a system check and performs necessary initialization (step S10).

Next, it is determined whether or not data has been received from the host computer 15 by the interface management circuit 35 (step S11). If the data has not been received, it is determined whether or not a predetermined time has elapsed since the last access to the memories 33 and 34 (step S12). If the predetermined time has not elapsed, the process returns to step S11 described above.

In the process of step S12, if it is determined that a predetermined time has passed since the last access, the supply of the power supply PW and the clock signal CLK to the memories 33 and 34 is cut off except for a part (step S1).
3). That is, the memories 33 and 34 are set to the sleep mode. Subsequently, a mode for waiting for data reception from the host computer 15 is entered (step S14). And
The process returns to step S11 described above.

If it is determined in step S11 that the interface management circuit 35 has received data from the host computer 15, it is determined whether the received data is data that requires access to the memories 33 and 34. (Step S15). Memory 3
If the data does not accompany the access in steps 3 and 34, it is determined whether or not the apparatus is in the sleep mode (step S16). If the current mode is the sleep mode, the process returns to the data reception determination processing in step S11 described above.
The process returns to the process of determining whether or not a predetermined time has elapsed since the last access to the memories 33 and 34 in Step 12.

On the other hand, if it is determined in step S15 that the data requires access to the memories 33 and 34, it is determined which of the memories 33 and 34 is to be accessed. Memory supply stop control circuit 3 provided in the memory to be used
It is determined whether 7 or 38 is currently in the sleep mode (step S17). When the memory supply stop control circuit 37 or 38 provided in the memory to be accessed among the memories 33 and 34 determines that the memory is in the sleep mode, the power supply PW for the memory is determined.
And the clock signal CLK is started (step S18). That is, the sleep mode of the memory to be accessed is released.

After the release of the sleep mode is completed in step S18, or when it is determined in step S17 that the sleep mode is not currently set, the memory 33 or 34 is used.
The necessary access to is performed (step S19). For example, when the data from the host computer 15 is a status confirmation command, the CPU 31
Or, it reads necessary information from 34 and returns it as job data to the host computer 15. If the data from the host computer 15 is input data for printing, the CPU 31 converts the input data into output data printable by the printing mechanism 20 using the memory 33 or 34.

The memory 33 in this step S19,
When the necessary access to 34 has been completed, the process returns to step S11 described above.

FIG. 3 is a flowchart showing the processing of the processing circuit supply stop control circuit 39 provided in the image processing circuit 36.

As shown in FIG. 3, when the power of the printer 10 is turned on, the supply stop control circuit 39 for the processing circuit is turned on.
Starts a system check and performs necessary initialization (step S30).

Next, it is determined whether or not data has been received from the host computer 15 by the interface management circuit 35 (step S31). If the data has not been received, it is determined whether or not a predetermined time has elapsed since the last processing of the image processing circuit 36 (step S3).
2). If the predetermined time has not elapsed, the process returns to step S31 described above.

If it is determined in step S32 that a predetermined time has elapsed since the last processing, the power supply PW and the clock signal CLK for the image processing circuit 36 are determined.
Is shut off except for a part (step 33). That is, the image processing circuit 36 is set to the sleep mode. Subsequently, a mode for waiting for data reception from the host computer 15 is entered (step S34). Then, the process returns to step S31.

If it is determined in step S31 that the interface management circuit 35 has received data from the host computer 15, it is determined whether the received data is data accompanied by printing (step S35). . That is, it is determined whether the data needs to be processed by the image processing circuit 36. If the data does not involve printing, it is determined whether or not the printer is currently in the sleep mode (step S36). If the current mode is the sleep mode, the process returns to the data reception determination processing in step S31 described above. If the current mode is not the sleep mode, whether or not a predetermined time has elapsed since the last processing in the image processing circuit 36 in step S32 described above is determined. It returns to the judgment processing.

On the other hand, if it is determined in step S35 that the data is data accompanied by printing, the image processing circuit 36 determines whether or not the current mode is the sleep mode (step S37). If it is determined that the image processing circuit 36 is currently in the sleep mode, the image processing circuit 36
Of the power supply PW and the clock signal CLK is started (step S38). That is, the sleep mode of the image processing circuit 36 is released.

After the release of the sleep mode is completed in step S38, and when it is determined in step S37 that the current mode is not the sleep mode, the image processing circuit 36 performs necessary processing and performs printing by the printing mechanism 20. (Step S39). More specifically, the CPU 31 uses the image processing circuit 36 to convert input data for printing from the host computer 15 into output data that can be printed by the printing mechanism 20, and outputs the output data to the printing mechanism 20.

When the necessary processing of the image processing circuit 36 in step S39 is completed, the process returns to step S31.

As described above, according to the controller 30 of this embodiment, the memories 33 and 34 are provided with the memory supply stop control circuits 37 and 38 for controlling the supply of the power supply PW and the clock signal CLK, and the image processing circuit Power supply PW to 36
And a memory supply stop control circuit for controlling the supply of the clock signal CLK and the supply stop control circuit 39 for the processing circuit, so that the power consumption of the printer 10 can be reduced.

That is, when there is no access to the memory 33 for a certain period of time, the memory supply stop control circuit 37 cuts off the power supply PW and the clock signal CLK supplied to the memory 33 except for a part. If the memory 34 has not been accessed for a certain period of time, the memory supply stop control circuit 3
8 is a power supply PW and a clock signal C supplied to the memory 34.
LK is cut off except for a part. Since the printer 10 generally occupies most of the non-operation time, the memory 33,
The time to access 34 is also only a small part of the power-on time. Therefore, by providing the memory supply stop control circuits 37 and 38 as in the present embodiment, the power consumed by the memories 33 and 34 can be reduced.

If the processing of the image processing circuit 36 has not been performed for a certain period of time, the supply stop control circuit 39 for the processing circuit supplies the power supply PW and the clock signal C supplied to the image processing circuit 36.
LK is cut off except for a part. Since the printer 10 generally occupies most of the time during which no printing operation is performed, the time during which the image processing circuit 36 is actually performing processing is only a part of the time during which the power is turned on. Therefore, by providing the processing circuit supply stop control circuit 39 as in the present embodiment, the power consumed by the image processing circuit 36 can be reduced.

Further, when data without processing by the image processing circuit 36, that is, data such as a status confirmation command without printing is received, the image processing circuit 36
Without starting the supply of the power supply PW or the clock signal CLK to the memories 33 and 34 only.
Since the supply of LK is started, power consumption can be efficiently suppressed. Further, at this time, since the supply of the power supply PW and the clock signal CLK is started only to the memory to be accessed among the memories 33 and 34, the power consumption of the memory not to be accessed can be suppressed.

[Second Embodiment] A second embodiment of the present invention is a modification of the first embodiment described above, and is a supply stop control for centrally managing the supply of a power supply and a clock signal to a memory and an image processing circuit. The circuit is provided separately.
This will be described in more detail below.

FIG. 4 is a block diagram showing a schematic configuration of a page printer according to a second embodiment of the present invention. The same parts as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The controller 30 according to the second embodiment is provided with a supply stop control circuit 40. The supply stop control circuit 40 outputs control signals CTL1 and CTL2 to the memories 41 and 42. Then, the control signal CTL
1. The power supply PW and the supply of the clock signal CLK in the memories 41 and 42 are controlled using the CTL2. That is, when the access to the memory 41 is not performed for a certain period of time, the supply stop control circuit 40 cuts off the power supply PW and the clock signal CLK supplied to the memory 41 except for a part. Then, when data for accessing the memory 41 is received by the interface management circuit 35, the memory 41 starts to take in the power supply PW and the clock signal CLK. In addition, the supply stop control circuit 40
If the access to the memory 2 is not performed for a certain period of time, the power supply PW and the clock signal CLK supplied to the memory 42 are cut off except for a part. When data for accessing the memory 42 is received by the interface management circuit 35, the power supply PW and the clock signal CLK are stored in the memory 42.
Start importing.

As described above, in the present embodiment, the supply stop control circuit 40 controls the memories 41 and 42 independently, but the two memories may be controlled integrally.

Further, the supply stop control circuit 40 outputs a control signal CTL3 to the image processing circuit 43. The control signal CTL3 is used to control the supply of the power supply PW and the clock signal CLK in the image processing circuit 43. That is, when the processing of the image control circuit 43 is not performed for a certain period of time, the supply stop control circuit 40
The power supply PW and the clock signal CLK supplied to the power supply are cut off except for a part. When data to be processed by the image processing circuit 43 is received by the interface management circuit 35, the power supply PW and the clock signal C are transmitted to the image control circuit 43.
Initiate LK uptake.

The memories 41 and 42 are not provided with the memory supply stop control circuit shown in the first embodiment. Further, the image control processing circuit 43 includes the first
The supply stop control circuit for the processing circuit shown in the embodiment is not provided.

FIG. 5 is a flowchart showing the processing of the supply stop control circuit 40.

As shown in FIG. 5, when the power of the printer 10 is turned on, the supply stop control circuit 40 starts a system check and performs necessary initialization (step S50).

Next, it is determined whether or not data has been received from the host computer 15 by the interface management circuit 35 (step S51). If the data has not been received, it is determined whether or not a predetermined time has elapsed since the last access to the memories 41 and 42 and whether or not a predetermined time has elapsed since the last processing of the image processing circuit 43 (step). S52). If the predetermined time has not elapsed, the process returns to step S51 described above.

In the process of step S52, the memory 4
If it is determined that the predetermined time has passed since the last access of the first access, the supply of the power supply PW and the clock signal CLK to the memory 41 is cut off except for a part (step S).
53). That is, the memory 41 is set to the sleep mode. Further, in the process of step S52, the memory 42
If it is determined that a predetermined time has passed since the last access, the supply of the power supply PW and the clock signal CLK to the memory 42 is cut off except for a part (step S5).
3). That is, the memory 42 is set to the sleep mode. Further, in the process of step S52, when it is determined that a certain period of time has elapsed since the last process of the image processing circuit 43, the supply of the power supply PW and the clock signal CLK to the image processing circuit 43 is cut off except for a part. (Step S53). That is, the image processing circuit 43 is set to the sleep mode.

Subsequently, a mode is entered for waiting for data reception from the host computer 15 (step S54). Then, the process returns to step S51.

If it is determined in step S51 that the interface management circuit 35 has received data from the host computer 15, it is determined whether the received data is data accompanied by printing (step S55). . If the data does not involve printing, it is determined whether the memory to be accessed among the memories 41 and 42 is currently in the sleep mode (step S56). If the memory to be accessed is currently in the sleep mode, the supply stop control circuit 40 starts taking in the power supply PW and the clock signal CLK of the memory (step S57).
That is, the sleep mode of the memory 41 or 42 is released.

After the release of the sleep mode is completed in step S57, and when it is determined in step S56 that the current mode is not the sleep mode, necessary accesses to the memories 41 and 42 are performed (step S58).

The memory 41 in this step S58,
If the necessary access to 42 has been completed, the process returns to step S51 described above.

On the other hand, when it is determined in step S55 that the data is data accompanied by printing, the memories 41 and 42 and the image processing circuit 43 determine whether the apparatus is in the sleep mode (step S55). S59).
At present, when the memories 41 and 42 and the image processing circuit 43 are in the sleep mode, the supply stop control circuit 40
Is the power supply PW of the memories 41 and 42 and the image processing circuit 43.
And the capture of the clock signal CLK is started (step S60). That is, the sleep modes of the memories 41 and 42 and the image processing circuit 43 are released. When releasing the sleep mode, it is also possible to release the sleep mode of only the memory to be accessed among the memories 41 and 42.

After the release of the sleep mode is completed in step S60, and in the process of step S59, the memory 4
If it is determined that both of the image processing circuits 1 and 42 and the image processing circuit 43 are not in the sleep mode, the CPU 31
Image processing is performed using the image processing circuit 43 and the image processing circuit 43, and printing is performed (step S61).

When the printing in step S61 is completed, the process returns to step S51 described above.

As described above, according to the controller 30 according to the present embodiment, the supply stop control circuit 40 is used to control the supply of the power supply PW and the clock signal CLK to the memories 41 and 42 and the image processing circuit 43. Because it was
As in the first embodiment, the power consumption of the printer 10 can be reduced.

When data without processing by the image processing circuit 43, that is, data such as a status confirmation command without printing, is received, the power supply PW and the supply of the clock signal CLK are supplied to the image processing circuit 43. Without starting
The power supply PW and the clock signal CLK are stored only in the memories 40 and 41.
, The power consumption can be suppressed efficiently.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in the first embodiment shown in FIG. 1, a supply stop control circuit may be provided in only one of the memories 33 and 34 and the image processing circuit 36.

In each of the above embodiments, the memories 33, 34, 41, 42 and the image processing circuits 36, 43
Is in the sleep mode, when releasing the sleep mode, the contents of the data input from the host computer 15 are determined and the necessary memories 33, 3
The sleep mode of only the image processing circuits 4, 41, 42 and the image processing circuits 36, 43 is released. However, when the data is input to the interface management circuit 35 without judging the contents of the input data, the memories 33, 3
The sleep mode of the image processing circuits 36 and 43 and the image processing circuits 36 and 43 may be canceled.

If a memory area is provided in the memory management circuit 32 and necessary processing can be performed in this memory area,
The sleep modes of the memories 33, 34, 41 and 42 may not be canceled.

[0066]

As described above, according to the present invention,
A supply stop control circuit is provided for stopping at least part of the supply of the power supply and the clock signal to at least one of the storage device and the image processing circuit if the supply of the power supply and the clock signal is not performed for a certain period of time, thereby reducing power consumption. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an internal structure of a page printer according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a processing flow of a memory supply stop control circuit provided inside the memory;

FIG. 3 is a view showing a processing flow of a supply stop control circuit for a processing circuit provided in the image processing circuit.

FIG. 4 is a block diagram showing an internal structure of a page printer according to a second embodiment of the present invention.

FIG. 5 is a view showing a processing flow of a separately provided supply stop control circuit.

FIG. 6 is a block diagram showing the internal structure of a conventional page printer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Printer 15 Host computer 20 Printing mechanism 30 Controller 31 CPU 32 Memory management circuit 33, 34 Memory 35 Interface management circuit 36 Image processing circuit 37, 38 Memory supply stop control circuit 39 Processing circuit supply stop control circuit 40 Supply stop control circuit 41, 42 memory 43 image processing circuit

Claims (11)

[Claims] 1. A controller for converting input data input from a computer into output data for creating an image and outputting the output data, wherein the controller performs various processes necessary for generating the output data from the input data. A processing device; a storage device that stores information necessary for processing performed by the central processing device; an image processing circuit that generates the output data at a stage before output of the output data; a storage device and the image processing circuit And a supply stop control circuit that stops at least a part of the supply of the power supply and the clock signal to at least one of the first and second power supplies when the operation is not performed for a certain period of time. 2. The image processing apparatus according to claim 1, wherein said supply stop control circuit is provided inside said storage device for controlling supply of at least one of a power supply and a clock signal, and said image processing device. Controller described. 3. The controller according to claim 1, wherein the supply stop control circuit is provided separately from the storage device and the image processing device. 4. A controller for converting input data input from a computer into output data for image creation and outputting the output data, wherein the controller performs various processes necessary for generating the output data from the input data. A processing device, a storage device that stores information necessary for processing performed by the central processing unit, when a predetermined time has elapsed from the last access, cut off at least a part of the supply of power and a clock signal, A controller comprising: a storage device having a supply stop control circuit that sets a sleep mode; and an image processing circuit that generates the output data before output of the output data. 5. An interface management circuit for managing input / output of data to / from a computer, wherein the supply stop control circuit controls the interface management circuit when the storage device is set to the sleep mode. 5. The controller according to claim 4, wherein when a data is input from a computer, a power supply of the storage device and a clock signal are started, and a sleep mode is released. 6. 6. An interface management circuit for managing input / output of data to / from a computer, wherein the supply stop control circuit controls the interface management circuit when the storage device is set to the sleep mode. If there is data input from the computer, it is determined whether the input data is data that needs to access the storage device, and if the input data is data that needs to access the storage device, 5. The controller according to claim 4, wherein the controller starts fetching a power supply and a clock signal of the storage device to release a sleep mode. 6. 7. A controller for converting input data input from a computer into output data for image creation and outputting the output data, wherein the controller performs various processes necessary for generating the output data from the input data. A processing device, a storage device for storing information necessary for processing performed by the central processing unit, and an image processing circuit for generating the output data at a stage before the output of the output data, wherein And an image processing circuit having a supply stop control circuit for setting at least part of supply of a power supply and a clock signal to a sleep mode when a lapse of time has elapsed. 8. An interface management circuit for managing input / output of data to / from a computer, wherein the supply stop control circuit is configured to control the interface management circuit when the image processing circuit is set to the sleep mode. 8. The controller according to claim 7, wherein when a data is input from a computer, the power supply of the image processing circuit and a clock signal are started to release a sleep mode. 9. An interface management circuit for managing data input / output with a computer, wherein the supply stop control circuit is configured to control the interface management circuit when the image processing circuit is set to the sleep mode. If there is data input from a computer, it is determined whether or not the input data is data accompanied by printing, and if the input data is data accompanied by printing, the power and clock signal of the image processing circuit are fetched. 8. The controller according to claim 7, further comprising: starting the sleep mode and releasing the sleep mode. 10. An image output apparatus comprising: a controller for converting input data input from a computer into output data for image creation and outputting the output data; and a drawing mechanism for creating an image based on the output data from the controller. A controller configured to perform various processes required to generate the output data from the input data; a storage device configured to store information necessary for the processes performed by the central processor; An image processing circuit that generates the output data at a stage before output of the output data; and at least a part of supply of a power supply and a clock signal to at least one of the storage device and the image processing circuit does not operate for a predetermined time. An image output device, comprising: a supply stop control circuit that stops in a case. 11. A power / clock control method for a controller which converts input data input from a computer into output data for image creation and outputs the converted data, wherein the storage stores information necessary for processing performed by a central processing unit. A power supply / clock for at least part of the supply of a power supply and a clock signal to at least one of the device and the image processing circuit for generating the output data, if the operation is not performed for a certain period of time, Control method.