JP2000235423A - Reference voltage generating circuit - Google Patents

Reference voltage generating circuit

Info

Publication number
JP2000235423A
JP2000235423A JP3558199A JP3558199A JP2000235423A JP 2000235423 A JP2000235423 A JP 2000235423A JP 3558199 A JP3558199 A JP 3558199A JP 3558199 A JP3558199 A JP 3558199A JP 2000235423 A JP2000235423 A JP 2000235423A
Authority
JP
Japan
Prior art keywords
voltage
circuit
generating
temperature
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3558199A
Other languages
Japanese (ja)
Other versions
JP3508831B2 (en
Inventor
Satoru Tada
哲 多田
Taketoshi Ikegami
武敏 池上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP3558199A priority Critical patent/JP3508831B2/en
Publication of JP2000235423A publication Critical patent/JP2000235423A/en
Application granted granted Critical
Publication of JP3508831B2 publication Critical patent/JP3508831B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit for generating a reference voltage which is not affected by the change of a surrounding temperature by using a band gap voltage having a low temperature coefficient as a reference. SOLUTION: This circuit is provided with a VT generating circuit 10 in which the emitters of a pair of transistors whose current density is different are commonly connected for generating a voltage being a difference between the base and emitter in proportion to a temperature T, a non-linear ΔVbe generating circuit 20 for receiving the output of the VT generating circuit 10, and for generating a ΔVbe having a current density rate in proportion to the temperature, and for multiplying this by m and outputting it, and a Vref outputting circuit 30 for allowing constant currents Ic to flow in a transistor, and for adding a voltage Vbe between the base and emitter of the transistor to the output of the non-linear ΔVbe generating circuit 20 and outputting it. Then, an output voltage equal to a band gap voltage can be obtained from this Vref outputting circuit 30.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、直流の基準電圧を
発生する基準電圧発生回路に関し、更に詳しくは、負の
温度係数を持つトランジスタのベース・エミッタ間電圧
Vbeと正の温度係数を持つ電圧(2つのトランジスタの
ベース・エミッタ間電圧の差ΔVbe)を重み付け加算す
ることにより、低い温度係数を持つバンドギャップ電圧
を基準としたバイアス回路の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit for generating a DC reference voltage, and more particularly to a base-emitter voltage Vbe of a transistor having a negative temperature coefficient and a voltage having a positive temperature coefficient. The present invention relates to an improvement of a bias circuit based on a bandgap voltage having a low temperature coefficient by weighting and adding (difference ΔVbe between base-emitter voltages of two transistors).

【0002】[0002]

【従来の技術】従来よりこの種の電圧発生回路はよく知
られており、例えば米国特許第3,887,863号に
は図4に示すような電圧発生回路が示されている。この
回路は抵抗RL1,RL2を介して正の電源ライン1に
接続されたペアトランジスタQ01,Q02を有し、そ
の一方のトランジスタQ02のエミッタは直列接続され
た抵抗RE2,RE1を介して負の電圧ライン2に接続
され、他方のトランジスタQ1のエミッタは抵抗R2,
R1の共通接続点に接続されている。
2. Description of the Related Art Conventionally, a voltage generating circuit of this type is well known. For example, US Pat. No. 3,887,863 shows a voltage generating circuit as shown in FIG. This circuit has a pair of transistors Q01 and Q02 connected to a positive power supply line 1 via resistors RL1 and RL2, and the emitter of one of the transistors Q02 has a negative voltage via resistors RE2 and RE1 connected in series. Connected to line 2 and the emitter of the other transistor Q1 is connected to a resistor R2
It is connected to the common connection point of R1.

【0003】また、トランジスタQ02,Q01のコレ
クタ電圧は高ゲインの演算増幅器3の入力端に接続さ
れ、演算増幅器3の出力は出力端子4に接続されると共
にトランジスタQ02,Q01のベースに接続されてい
る。
The collector voltages of the transistors Q02 and Q01 are connected to the input terminal of a high gain operational amplifier 3, and the output of the operational amplifier 3 is connected to the output terminal 4 and to the bases of the transistors Q02 and Q01. I have.

【0004】2つのトランジスタQ01,Q02のベー
ス・エミッタ間電圧の差ΔVbeは正の温度係数を持ち、
トランジスタQ01のベース・エミッタ間電圧Vbeは負
の温度係数を持つが、図4の構成においてはこれらが互
いに打ち消し合うように作用する。温度係数(TC)を
零に近づけるために出力電圧Voutはほぼエネルギーバ
ンドギャップ電圧Vgoにセットされる。Vgoは、シリコ
ンの場合1.205Vであるが、出力電圧Voutをこれ
よりわずかに高い電圧にすると優れた結果が得られる。
The difference ΔVbe between the base-emitter voltages of the two transistors Q01 and Q02 has a positive temperature coefficient,
Although the base-emitter voltage Vbe of the transistor Q01 has a negative temperature coefficient, they act so as to cancel each other in the configuration of FIG. The output voltage Vout is set to approximately the energy bandgap voltage Vgo to bring the temperature coefficient (TC) closer to zero. Although Vgo is 1.205 V in the case of silicon, excellent results can be obtained by setting the output voltage Vout to a slightly higher voltage.

【0005】例えば、TCを零にするために出力電圧
を、 Vout=Vgo+(m−1)kT0/q にセットする。ここに、mは定数であり、ほぼ1.5、
kはボルツマン定数、T0は動作温度、qは電子の電荷
である。
For example, the output voltage is set to Vout = Vgo + (m−1) kT 0 / q in order to make TC zero. Where m is a constant, approximately 1.5,
k is the Boltzmann constant, T 0 is the operating temperature, and q is the charge of the electrons.

【0006】この出力電圧Voutは抵抗RE1の適宜の
選択により所望の値に調節することができる。そして、
出力Voutが予め設定された最適レベルより下がった場
合は、トランジスタQ02,Q01の電流比I2/I1
抵抗比RL1/RL2よりも大きくなり、増幅器3の出
力が増加し、出力電圧Voutを最適レベルまで引き上げ
る。出力Voutが最適レベルより高くなった場合は、増
幅器3の出力が減少し出力電圧Voutを最適レベルに下
げる。
The output voltage Vout can be adjusted to a desired value by appropriately selecting the resistor RE1. And
If the output Vout falls below a preset optimum level, the transistor Q02, the current ratio I 2 / I 1 of Q01 becomes greater than the resistance ratio RL1 / RL2, the output of the amplifier 3 is increased, the output voltage Vout Raise to optimal level. When the output Vout becomes higher than the optimum level, the output of the amplifier 3 decreases, and the output voltage Vout is lowered to the optimum level.

【0007】以上のように動作する図4に示す回路は、
低い温度係数で出力電圧を所望のレベルに連続的に保持
することができる。
[0007] The circuit shown in FIG.
The output voltage can be continuously maintained at a desired level with a low temperature coefficient.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の回路では次のような課題があった。 抵抗による最適な重み付けをするために、レーザトリ
ミング等の高精度なトリミングが必要である。 かりに適切な重み付けを行ったとしても、ΔVbeの温
度特性が線形であるのに対してVbeの温度特性は非線形
であるため、±25ppm/゜C程度の温度依存性が残
る。
However, such a conventional circuit has the following problems. High-precision trimming, such as laser trimming, is required to perform optimum weighting using resistors. Even if appropriate weighting is performed, the temperature dependence of ΔVbe is linear, whereas the temperature characteristic of Vbe is nonlinear, so that the temperature dependence of about ± 25 ppm / ° C remains.

【0009】本発明は、このような課題を解決するもの
で、低い温度係数を持つバンドギャップ電圧を基準と
し、周囲温度変化の影響を受けない基準電圧を発生する
基準電圧発生回路を提供することを目的とするものであ
る。
The present invention has been made to solve the above problem, and provides a reference voltage generating circuit for generating a reference voltage which is not affected by a change in ambient temperature, based on a bandgap voltage having a low temperature coefficient. It is intended for.

【0010】[0010]

【課題を解決するための手段】このような目的を達成す
るために、請求項1の発明では、電流密度が異なる一対
のトランジスタのエミッタ同士を共通接続し、温度Tに
比例したベース・エミッタ間電圧の差の電圧を発生する
T発生回路と、このVT発生回路の出力を受け温度に比
例した電流密度比を持つΔVbeを発生しこれをm倍して
出力する非線形ΔVbe発生回路と、定電流Icをトラン
ジスタに流しこのトランジスタのベース・エミッタ間電
圧Vbeと前記非線形ΔVbe発生回路の出力とを加算して
出力するVref出力回路を備え、このVref出力回路より
バンドキャップ電圧に等しい出力電圧が得られるように
構成したことを特徴とする。
In order to achieve the above object, according to the first aspect of the present invention, the emitters of a pair of transistors having different current densities are commonly connected to each other, and the base-emitter is proportional to the temperature T. A V T generation circuit for generating a voltage having a voltage difference, a non-linear ΔV be generation circuit for receiving the output of the V T generation circuit, generating ΔV be having a current density ratio proportional to temperature, multiplying the output by m, and outputting the result; A Vref output circuit that supplies a constant current Ic to the transistor and adds the base-emitter voltage Vbe of the transistor to the output of the non-linear ΔVbe generation circuit to output the same; It is characterized in that it is configured to be obtained.

【0011】VT発生回路と非線形ΔVbe発生回路によ
りm×ΔVbeを得、Vref出力回路において前記m×Δ
VbeにVbeを加えた電圧Vrefを出力する。このときの
電圧Vrefは、次の通りである。 電圧Vref=Vbe+m×ΔVbe =Vgo−(kT/q)ln{(KTr)/(IcNm)} ただし、Vgoは絶対温度0度におけるSiのバンドギャ
ップ電圧、kはボルツマン定数、Tは絶対温度、qは素
電荷、Kは温度に無関係な定数、rはプロセスに異存す
る定数、Icは定電流、NはVT発生回路での電流密度
比、mは非線形ΔVbe発生回路の倍率
[0011] to give the m × .DELTA.Vbe by V T generator and a nonlinear .DELTA.Vbe generating circuit, the m × delta at Vref output circuit
A voltage Vref obtained by adding Vbe to Vbe is output. The voltage Vref at this time is as follows. Voltage Vref = Vbe + m × ΔVbe = Vgo- (kT / q) ln {(KT r) / (IcN m)} However, Vgo the bandgap voltage of Si at an absolute temperature of 0 degree, k is Boltzmann's constant, T is the absolute temperature , q is the elementary charge, K is a constant independent of the temperature, r is constant objection to the process, Ic is a constant current, N is the current density ratio in the V T generation circuit, m is the magnification of the non-linear ΔVbe generating circuit

【0012】このとき、Nm=KTr/Ic=ATr(Aは
温度を含まない項)とすることによりVref=Vgoとす
ることができ、温度に依存しないバンドギャップ基準電
圧発生回路を実現することができる。
[0012] In this case, N m = KT r / Ic = AT r (A Section without the temperature) can be a Vref = Vgo With, achieve a bandgap reference voltage generating circuit which does not depend on temperature can do.

【0013】この場合、非線形ΔVbe発生回路として、
例えば請求項2のように、VT発生回路から抵抗を介し
て出力される温度に比例した電流と調整電圧源からの定
電圧を前記抵抗に等しい温度係数を有する抵抗を通すこ
とにより得られた電流とを一対のトランジスタにそれぞ
れ流入させ、温度に比例した電流密度比を持つΔVbeを
発生させるように構成することができる。
In this case, the nonlinear ΔVbe generating circuit is
For example, as in claim 2, obtained by passing the resistor having a temperature coefficient equal to the resistance of constant voltage from the current proportional to the temperature output through a resistor from V T generating circuit regulated voltage source And a current can flow into each of the pair of transistors to generate ΔVbe having a current density ratio proportional to temperature.

【0014】また、非線形ΔVbe発生回路として、例え
ば請求項3のように、VT発生回路からの温度Tに比例
したベース・エミッタ間電圧の差の電圧に対応した電流
の対数値を得る第1の対数増幅器と、調整電圧源からの
定電圧に対応した電流の対数値を得る第2の対数増幅器
との出力の差を出力する対数変換回路と、前記2つの対
数増幅器の出力の差の電圧をm倍するm倍回路から構成
することができる。
Further, as the non-linear ΔVbe generating circuit, for example as in claim 3, the first to obtain the logarithm of current corresponding to the voltage difference between the base and emitter voltage proportional to the temperature T from V T generator A logarithmic amplifier, a second logarithmic amplifier that obtains a logarithmic value of a current corresponding to a constant voltage from the regulated voltage source, and a logarithmic conversion circuit that outputs a difference between the outputs of the two logarithmic amplifiers. Can be configured by an m-fold circuit that multiplies m by m.

【0015】また、請求項4のように、VT発生回路お
よび非線形ΔVbe発生回路の一対のトランジスタを、そ
れぞれトランジスタを3段直列に接続した構成とするこ
とができる。このような構成にすれば、本発明の回路が
IC化された場合パッケージ応力による影響が低減され
るという効果がある。
Furthermore, as according to claim 4, the pair of transistors of V T generation circuit and nonlinear ΔVbe generating circuit, each can be configured whereby a transistor in three stages in series. With such a configuration, when the circuit of the present invention is formed into an IC, the effect of the package stress is reduced.

【0016】[0016]

【発明の実施の形態】以下本発明を詳しく説明する。本
発明はバンドギャップ電圧を基準にした基準電圧発生回
路である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail. The present invention is a reference voltage generation circuit based on a band gap voltage.

【0017】本発明の回路における出力電圧(バンドギ
ャップ基準電圧Vref)は、次のモデル式で表わすこと
ができる。 Vref=Vbe+m×ΔVbe={Vgo−(kT/q)ln(KTr/Ic)} +{m×(kT/q)ln(N)} =Vgo−(kT/q)ln(KTr/(IcNm)} ……(1) ここに、mは倍率を表わす係数、Vgoは絶対温度の零度
におけるシリコン(Si)のバンドギャップ電圧、Tは
絶対温度、lnは自然対数記号、Nは電流密度比、rは
プロセスに依存する定数、Icは電流値、kはボルツマ
ン定数、Kは温度に無関係な定数である。
The output voltage (bandgap reference voltage Vref) in the circuit of the present invention can be represented by the following model equation. Vref = Vbe + m × ΔVbe = {Vgo- (kT / q) ln (KT r / Ic)} + {m × (kT / q) ln (N)} = Vgo- (kT / q) ln (KT r / ( IcN m )} (1) where m is a coefficient representing a magnification, Vgo is a band gap voltage of silicon (Si) at zero degree of absolute temperature, T is absolute temperature, ln is a natural logarithmic symbol, and N is a current density. The ratio, r is a process-dependent constant, Ic is a current value, k is a Boltzmann constant, and K is a constant independent of temperature.

【0018】ここで、(1)式におけるVbeの展開式に
ついて述べる。まず、Vbeの一般式は次の通りである。 Vbe=(kT/q)ln(Ic/Is) ……(2) ここに、Isは逆飽和電流であり、次の関係がある。
Here, the expansion equation of Vbe in equation (1) will be described. First, the general formula of Vbe is as follows. Vbe = (kT / q) ln (Ic / Is) (2) where Is is a reverse saturation current and has the following relationship.

【0019】Is=qDAn2/Q ただし、Dは拡散係数、Aはエミッタ・ベースの接合面
積、nは真性キャリア密度、Qはベース中の単位面積当
たりの不純物量である。このうち、q、A、Qは温度に
対して不変であり、これを定数Bとおくと上式は、 Is=BDn2 ……(3) となる。
Is = qDAn 2 / Q where D is the diffusion coefficient, A is the junction area between the emitter and base, n is the intrinsic carrier density, and Q is the amount of impurities per unit area in the base. Of these, q, A, and Q are invariant with respect to the temperature, and when this is set as a constant B, the above equation becomes: Is = BDn 2 (3)

【0020】また、アインシュタインの関係式D=kT
μ/q(μはキャリアの移動度)を代入すると、 Is=kTμBn2/q ……(4) となる。更に、k、qは温度に不変であるため、これを
Bに含めて新たに定数Cとすると、 Is=CTμn2 ……(5) となる。
The Einstein relation D = kT
When μ / q (μ is the carrier mobility) is substituted, Is = kTμBn 2 / q (4) Further, since k and q are invariant to the temperature, if these are included in B and newly set as a constant C, then Is = CTμn 2 (5).

【0021】キャリアの移動度μは、μ=ETxと表わ
せる。ここに、Eは温度に不変な項であり、Tの乗数x
はベース領域の不純物濃度で変化する値である。また、
真性キャリア密度は周知のように、 n2=(FT3)exp(−Vgo/Vt) ……(6) である。ここで、Fは温度に不変な値である。またVt
=kT/qである。
[0021] The mobility μ of carriers, μ = ET x and expressed. Here, E is a temperature-invariant term, and a multiplier x of T x
Is a value that changes with the impurity concentration of the base region. Also,
As is well known, the intrinsic carrier density is n 2 = (FT 3 ) exp (−Vgo / Vt) (6) Here, F is a value that does not change with temperature. Vt
= KT / q.

【0022】上記μとn2を(2)式に代入し展開する
と、(1)式における関係式、 Vbe=Vgo−(kT/q)ln(kTγ/Ic) が得られる。
[0022] When substituted into the μ and n 2 (2) wherein deployment, relational expression of (1), Vbe = Vgo- (kT / q ) ln (kT γ / Ic) is obtained.

【0023】さて、(1)式において、Nm=KTr/I
c=AT(Aは温度に依存しない係数)とすることによ
り、つまりVT発生回路での電流密度比Nを温度に比例
させ、m=rとすることにより、(1) 式の第2項を
零にすることができるため、素子のバラツキを含む項を
キャンセルでき、かつ温度に依存しないバンドギャップ
リファレンス電圧を得ることができる。本発明はこのよ
うな原理に基づいて周囲温度変化の影響を受けない基準
電圧発生回路を実現したものである。
Now, in the equation (1), N m = KT r / I
By setting c = AT (A is a coefficient independent of temperature), that is, by making the current density ratio N in the VT generation circuit proportional to temperature and by setting m = r, the second term of the equation (1) is obtained. Can be reduced to zero, so that terms including variations in elements can be canceled, and a bandgap reference voltage independent of temperature can be obtained. The present invention realizes a reference voltage generating circuit which is not affected by a change in ambient temperature based on such a principle.

【0024】図1は本発明に係る基準電圧発生回路の一
実施例を示す構成図である。この基準電圧発生回路は、
電流密度の異なる一対のトランジスタのエミッタを共通
接続し温度に比例したベース・エミッタ間電圧の差を発
生するVT発生回路10と、このVT発生回路10の出力
から温度に比例した電流密度比を持つΔVbeを発生させ
m倍する非線形ΔVbe発生回路20と、定電流Icをト
ランジスタに流しVbeを発生し前記非線形ΔVbe発生回
路20の出力と加算し基準電圧Vrefを発生するVref出
力回路30より構成される。
FIG. 1 is a block diagram showing one embodiment of a reference voltage generating circuit according to the present invention. This reference voltage generation circuit
And V T generation circuit 10 for generating a difference in base-emitter voltage of the emitter proportional to the common connection and the temperature of the different pair of transistors the current density, the current density ratio in proportion to the temperature from the output of the V T generation circuit 10 And a Vref output circuit 30 for generating a reference voltage Vref by generating a Vbe by applying a constant current Ic to a transistor, adding the output to the nonlinear ΔVbe generation circuit 20, and generating a reference voltage Vref. Is done.

【0025】以下各部について更に詳しく説明する。V
T発生回路10は、エミッタが共通接続されたペアトラ
ンジスタQ0,Q3と、一端が高圧側電源(電圧Vc
c)に接続され他端がそれぞれトランジスタQ0,Q3
のコレクタに接続された抵抗R0,R1(抵抗比がN対
1)と、一端がトランジスタQ0,Q3のエミッタに接
続され他端が低電圧源(電圧Vee)に接続された定電
流源17と、トランジスタQ0,Q3のコレクタ電圧を
差動で受けると共にその出力がトランジスタQ3のベー
スに接続される演算増幅器OP10と、トランジスタQ
0,Q3のベース間に接続された抵抗R2から構成され
ている。
Hereinafter, each part will be described in more detail. V
The T generating circuit 10 includes a pair of transistors Q0 and Q3 whose emitters are connected in common, and a high-side power supply (voltage Vc
c) and the other end is connected to each of the transistors Q0 and Q3.
And a constant current source 17 having one end connected to the emitters of the transistors Q0 and Q3 and the other end connected to a low voltage source (voltage Vee). An operational amplifier OP10 having differentially received the collector voltages of transistors Q0 and Q3 and having its output connected to the base of transistor Q3;
A resistor R2 is connected between the bases of 0 and Q3.

【0026】このような接続によれば、トランジスタQ
0,Q3のベース間には、 VT=(kT/q)lnN なる電圧VTが生じ、したがって抵抗R2(抵抗値は
2)には、 I1=(kT/qR2)lnN なる電流I1が流れる。
According to such a connection, the transistor Q
0, between Q3 based, V T = (kT / q ) lnN voltage V T generated composed, hence the resistor R2 (the resistance value R 2), I 1 = ( kT / qR 2) lnN becomes current I 1 flows.

【0027】非線形ΔVbe発生回路20は、一対の対数
増幅器Q6,Q9と、演算増幅器OP11と、抵抗R3
と、バッファアンプとしての演算増幅器OP12と、抵
抗R4,R5を直列接続してなる直列接続回路より構成
される。
The nonlinear ΔVbe generation circuit 20 includes a pair of logarithmic amplifiers Q6 and Q9, an operational amplifier OP11, and a resistor R3.
, An operational amplifier OP12 as a buffer amplifier, and a series connection circuit formed by connecting resistors R4 and R5 in series.

【0028】対数増幅器Q6,Q9(Q6を第1の対数
増幅器、Q9を第2の対数増幅器と呼ぶ)としてここで
はトランジスタが使用される。Q6のコレクタにはVT
発生回路10で生じた電流I1が流入し、他方、Q9の
コレクタには抵抗R3に流れる電流I2が流入する。こ
の電流I2は、抵抗R3(抵抗値がR3)に印加する基準
電圧VAJにより調整可能となっている。なお、トランジ
スタQ9のベースはコモンラインgndに接続されてい
る。
Here, transistors are used as the logarithmic amplifiers Q6 and Q9 (Q6 is called a first logarithmic amplifier and Q9 is called a second logarithmic amplifier). V T to the collector of Q6
Current I 1 flows generated in the generator 10, while the collector of Q9 current I 2 flowing through the resistor R3 flows. This current I 2 can be adjusted by the reference voltage V AJ applied to the resistor R 3 (the resistance value is R 3 ). Note that the base of the transistor Q9 is connected to the common line gnd.

【0029】演算増幅器OP11は、その非反転入力端
子がコモンラインに接続され、反転入力端子がトランジ
スタQ9のコレクタに接続され、出力端子がトランジス
タQ6,Q9のエミッタに共通接続されている。この場
合、演算増幅器OP11の反転入力端子は等価的にコモ
ンライン電位となり、抵抗R3の一端はコモンラインの
電位になる。
The operational amplifier OP11 has a non-inverting input terminal connected to the common line, an inverting input terminal connected to the collector of the transistor Q9, and an output terminal commonly connected to the emitters of the transistors Q6 and Q9. In this case, the inverting input terminal of the operational amplifier OP11 is equivalently at the common line potential, and one end of the resistor R3 is at the common line potential.

【0030】演算増幅器OP12は、その非反転入力端
子がトランジスタQ6のコレクタと接続され、また反転
入力端子に接続された出力端子が抵抗R4とR5を直列
接続回路に接続されている。この抵抗R4とR5の共通
接続点はトランジスタQ6のベースに接続されている。
The operational amplifier OP12 has a non-inverting input terminal connected to the collector of the transistor Q6, and an output terminal connected to the inverting input terminal connected to resistors R4 and R5 connected in series. The common connection point of the resistors R4 and R5 is connected to the base of the transistor Q6.

【0031】抵抗R4と抵抗R5とが、m=(R4+R
5)/R5であると、演算増幅器OP12の出力端には
直列接続回路の中点の電圧ΔVbeのm倍の電圧m×ΔV
beが発生するため、演算増幅器OP12と直列接続回路
からなる部分をここではm倍回路と呼ぶ。なお、直列接
続回路の中点の電圧ΔVbeはトランジスタQ6とトラン
ジスタQ9の各ベース・エミッタ間電圧の差である。
When the resistance R4 and the resistance R5 are m = (R4 + R
5) If / R5, the output terminal of the operational amplifier OP12 has a voltage m × ΔV that is m times the voltage ΔVbe at the middle point of the series connection circuit.
Since be occurs, a portion including the operational amplifier OP12 and the series connection circuit is referred to as an m-fold circuit here. The voltage ΔVbe at the midpoint of the series connection circuit is the difference between the base-emitter voltages of the transistor Q6 and the transistor Q9.

【0032】Vref出力回路30は、定電流源18と、
バッファ16と、トランジスタQ12より構成される。
定電流源18は一端が高圧側電源に接続され他端がトラ
ンジスタQ12のコレクタに接続されている。トランジ
スタQ12のエミッタは前記非線形ΔVbe発生回路20
の演算増幅器OP12の出力端に接続されている。
The Vref output circuit 30 includes: a constant current source 18;
It comprises a buffer 16 and a transistor Q12.
The constant current source 18 has one end connected to the high voltage side power supply and the other end connected to the collector of the transistor Q12. The emitter of the transistor Q12 is connected to the nonlinear ΔVbe generation circuit 20.
Of the operational amplifier OP12.

【0033】バッファ16の入力端はトランジスタQ1
2のコレクタと接続され、出力端はトランジスタQ12
のベースおよび出力端VrefOUTに接続されている。
The input terminal of the buffer 16 is connected to the transistor Q1
2 and the output terminal is connected to the transistor Q12.
And the output terminal VrefOUT.

【0034】このような構成における動作を次に説明す
る。VT発生回路10の抵抗R2に流れる電流I2は、 I2=(kT/qR2)lnN であり、この電流がトランジスタQ6に流れる。このと
きのトランジスタQ6のベース・エミッタ間電圧Vbe1
は次のようになる。 Vbe1=(kT/q)ln(I1/Is) =(kT/q)ln{(kT/(q・Is・R2))lnN}
The operation in such a configuration will now be described. Current I 2 flowing through the resistor R2 of the V T generation circuit 10 is I 2 = (kT / qR2) lnN, flows the current to the transistor Q6. At this time, the base-emitter voltage Vbe1 of the transistor Q6
Is as follows. Vbe1 = (kT / q) ln (I 1 / I s) = (kT / q) ln {(kT / (q · Is · R2)) lnN}

【0035】他方、トランジスタQ9には、抵抗R3に
流れる電流I2=VAJ/R3が入力され、そのベース・
エミッタ間電圧Vbe2は次のようになる。 Vbe2==(kT/q)ln(I2/Is) =(kT/q)ln(VAJ/(Is・R3)
On the other hand, the current I 2 = V AJ / R3 flowing through the resistor R3 is input to the transistor Q9,
The emitter-to-emitter voltage Vbe2 is as follows. Vbe2 == (kT / q) ln (I 2 / I s) = (kT / q) ln (V AJ / (Is · R3)

【0036】したがって、分圧回路の中点の電圧ΔVbe
は、 ΔVbe=Vbe1−Vbe2=(kT/q)ln(CT/
AJ) ただし、C={kR3/(qR2)}lnNとなり、演
算増幅器OP12の出力端の電圧m×ΔVbeは、 m×ΔVbe=m×(kT/q)ln(CT/VAJ) =(kT/q)ln(CT/VAJm ただし、m=(R4+R5)/R5となる。
Therefore, the voltage ΔVbe at the middle point of the voltage dividing circuit
ΔVbe = Vbe1−Vbe2 = (kT / q) ln (CT /
V AJ ) where C = {kR3 / (qR2)} lnN, and the voltage m × ΔVbe at the output terminal of the operational amplifier OP12 is m × ΔVbe = m × (kT / q) ln (CT / V AJ ) = ( kT / q) ln (CT / V AJ ) m where m = (R4 + R5) / R5.

【0037】そのため、Vref出力回路30の出力端Vr
efOUTの電圧Vrefは、 Vref=Vbe+m×ΔVbe =Vgo−(kT/q)ln{(VAJ mKTr)/(Icmm)} となる。ここで、r=m,VAJ mK=Icmとすると、 Vref=Vgo となり、周囲温度変化の影響を受けない基準電圧が得ら
れる。
Therefore, the output terminal Vr of the Vref output circuit 30
voltage Vref efOUT becomes Vref = Vbe + m × ΔVbe = Vgo- (kT / q) ln {(V AJ m KT r) / (I c C m T m)}. Here, if r = m, V AJ m K = I c C m , then Vref = Vgo, and a reference voltage which is not affected by changes in the ambient temperature can be obtained.

【0038】本発明によればこのように既知の一定電圧
Vgoに出力を調整することでバラツキをキャンセルする
ことができ、かつ温度係数±0ppm/゜Cを実現するこ
とができる。しかしながら、この回路をICで実現する
場合、パッケージ応力によって個々のトランジスタにお
けるバンドギャップ電圧が変化し、上記の論理式に何ら
かの定数項が加算された形となるため、一点調整は実現
困難となる。
According to the present invention, the output can be adjusted to the known constant voltage Vgo in this way, the variation can be canceled, and the temperature coefficient ± 0 ppm / ° C can be realized. However, when this circuit is implemented by an IC, the bandgap voltage of each transistor changes due to the package stress, and a certain constant term is added to the above logical expression, so that it is difficult to achieve one-point adjustment.

【0039】図2の実施例構成図はそのようなパッケー
ジ応力の影響を低減することのできる回路構成の一例で
ある。すなわち、VT発生回路10および非線形ΔVbe
発生回路20の一対のトランジスタをそれぞれ数段(図
では3段)積み重ねたもので、これにより応力による影
響は容易に低減される。
FIG. 2 is an example of a circuit configuration capable of reducing the influence of such package stress. That, V T generation circuit 10 and nonlinear ΔVbe
The pair of transistors of the generation circuit 20 are each stacked in several stages (three stages in the figure), thereby easily reducing the influence of stress.

【0040】また、図2の回路構成では、非線形ΔVbe
発生回路20のm倍回路の倍率を落すことができる(m
/3に落すことができる)ため、誤差が大きく増幅され
ることもなく、実用上極めて有効である。
In the circuit configuration of FIG. 2, the nonlinear ΔVbe
The magnification of the m-times circuit of the generation circuit 20 can be reduced (m
/ 3), and the error is not greatly amplified, which is extremely effective in practice.

【0041】図3は出力電圧の温度特性を従来例と比較
して示したものである。丸印プロットが本発明の基準電
圧発生回路の特性、四角プロットが従来回路の特性であ
る。本発明の温度特性が従来よりも格段に優れ、温度に
よる変動が極めて少ないことが分かる。なお、参照的に
示した斜めの直線は+25ppm/゜Cと−25ppm/゜C
の温度変化を表わしている。
FIG. 3 shows the temperature characteristics of the output voltage in comparison with the conventional example. Circle plots indicate the characteristics of the reference voltage generating circuit of the present invention, and square plots indicate the characteristics of the conventional circuit. It can be seen that the temperature characteristics of the present invention are much better than those of the prior art, and the fluctuations due to temperature are extremely small. The oblique straight lines shown for reference are +25 ppm / ppmC and -25 ppm / ゜ C.
Represents the temperature change.

【0042】[0042]

【発明の効果】以上説明したように本発明によれば次の
ような効果がある。請求項1に記載の発明によれば、温
度に依存しないバンドギャップ基準電圧を容易に発生さ
せることができる。
As described above, according to the present invention, the following effects can be obtained. According to the first aspect of the present invention, it is possible to easily generate a bandgap reference voltage independent of temperature.

【0043】また、請求項4のように構成することによ
り、パッケージ応力の影響を低減させる回路を容易に実
現することができる。
According to the fourth aspect of the present invention, a circuit for reducing the influence of package stress can be easily realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る基準電圧発生回路の一実施例を示
す構成図である。
FIG. 1 is a configuration diagram showing one embodiment of a reference voltage generation circuit according to the present invention.

【図2】本発明の他の実施例を示す構成図である。FIG. 2 is a configuration diagram showing another embodiment of the present invention.

【図3】本発明の基準電圧発生回路と従来の回路との温
度特性比較図である。
FIG. 3 is a temperature characteristic comparison diagram between a reference voltage generation circuit of the present invention and a conventional circuit.

【図4】従来の基準電圧発生回路の一例を示す構成図で
ある。
FIG. 4 is a configuration diagram illustrating an example of a conventional reference voltage generation circuit.

【符号の説明】[Explanation of symbols]

10 VT発生回路 16 バッファ 17,18 定電流源 20 非線形ΔVbe発生回路 30 Vref出力回路 Q0,Q3,Q6,Q9,Q12 トランジスタ R0,R1,R2,R3,R4,R5 抵抗 OP10,OP11,OP12 演算増幅器10 V T generating circuit 16 Buffer 17, 18 Constant current source 20 Nonlinear ΔVbe generating circuit 30 Vref output circuit Q0, Q3, Q6, Q9, Q12 Transistors R0, R1, R2, R3, R4, R5 Resistance OP10, OP11, OP12 Operation amplifier

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】電流密度が異なる一対のトランジスタのエ
ミッタ同士を共通接続し、温度Tに比例したベース・エ
ミッタ間電圧の差の電圧を発生するVT発生回路と、 このVT発生回路の出力を受け温度に比例した電流密度
比を持つΔVbeを発生しこれをm倍して出力する非線形
ΔVbe発生回路と、 定電流Icをトランジスタに流しこのトランジスタのベ
ース・エミッタ間電圧Vbeと前記非線形ΔVbe発生回路
の出力とを加算して出力するVref出力回路を備え、こ
のVref出力回路よりバンドキャップ電圧に等しい出力
電圧が得られるように構成したことを特徴とする基準電
圧発生回路。
1. A The emitters of the current density is different pair of transistors commonly connected, and V T generating circuit for generating a voltage difference proportional to the base-emitter voltage of the temperature T, the output of the V T generator And a non-linear .DELTA.Vbe generating circuit for generating a .DELTA.Vbe having a current density ratio proportional to the temperature and multiplying the multiplied by m and outputting a constant current Ic to the transistor, generating a base-emitter voltage Vbe of the transistor and generating the non-linear .DELTA.Vbe. A reference voltage generating circuit, comprising: a Vref output circuit for adding the output of the circuit and outputting the sum, and configured to obtain an output voltage equal to the band cap voltage from the Vref output circuit.
【請求項2】前記非線形ΔVbe発生回路は、前記VT
生回路から抵抗を介して出力される温度に比例した電流
と調整電圧源からの定電圧を前記抵抗に等しい温度係数
を有する抵抗を通すことにより得られた電流とを一対の
トランジスタにそれぞれ流入させ、温度に比例した電流
密度比を持つΔVbeを発生させるように構成したことを
特徴とする請求項1記載の基準電圧発生回路。
Wherein said non-linear ΔVbe generating circuit, through a resistor having a temperature coefficient equal to the resistance of constant voltage from the current and the regulated voltage source proportional to the temperature to be output through the resistor from the V T generating circuit 2. The reference voltage generation circuit according to claim 1, wherein the currents obtained as described above are respectively supplied to a pair of transistors to generate ΔVbe having a current density ratio proportional to temperature.
【請求項3】前記非線形ΔVbe発生回路は、前記VT
生回路からの温度Tに比例したベース・エミッタ間電圧
の差の電圧に対応した電流の対数値を得る第1の対数増
幅器と、調整電圧源からの定電圧に対応した電流の対数
値を得る第2の対数増幅器との出力の差を出力する対数
変換回路と、 前記2つの対数増幅器の出力の差の電圧をm倍するm倍
回路を備えたことを特徴とする請求項1記載の基準電圧
発生回路。
Wherein said non-linear ΔVbe generating circuit includes a first logarithmic amplifier obtaining a logarithmic value of the current corresponding to the voltage difference between the base and emitter voltage proportional to the temperature T from the V T generation circuit, adjusting A logarithmic conversion circuit for outputting a difference between an output of the second logarithmic amplifier and a logarithmic value of a current corresponding to a constant voltage from the voltage source; 2. The reference voltage generating circuit according to claim 1, further comprising a circuit.
【請求項4】前記VT発生回路および非線形ΔVbe発生
回路は、一対のトランジスタのそれぞれがトランジスタ
を3段直列に接続した構成であることを特徴とする請求
項1記載の基準電圧発生回路。
Wherein said V T generation circuit and nonlinear ΔVbe generating circuit includes a reference voltage generating circuit according to claim 1, wherein the each of the pair of transistors is configured whereby a transistor in three stages in series.
JP3558199A 1999-02-15 1999-02-15 Reference voltage generation circuit Expired - Fee Related JP3508831B2 (en)

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