DE3022497A1 - COUPLE AREA - Google Patents

Description

PHILIPS PATENTVERVALTUNG GMBH - PHD 80-073

Switching matrix

The invention relates to a switching matrix for selective connection a number of channel modules, each with one of a larger number of subscriber modules via an internal Time division multiplex line, which includes all channel modules and all subscriber modules connects with each other, especially for use as a concentrator.

Such a switching network is used in switching systems, in particular in telephone switching systems Establish connections between different participants. Since it is usually assumed that only one certain fraction of the connected participants is occupied at the same time, is between the participants and the actual switching a concentrator switched, which also contains a switching matrix.

A space switching matrix contains a number of switches constructed like a matrix at the crossover points of row and column lines, which are connected to the inputs or outputs, and to establish a desired connection the relevant crosspoint switch is closed. Such a switching network only needs low-frequency signals / however, it is quite complex to build. With a time switch the inputs are queried cyclically and read out at other times via a time division multiplex line. In general there is only a single time multiplex output available.

In a concentrator in particular, there are a number of subscriber lines Concentrated on a significantly smaller number of output lines, which then only start with the actual Switching arrangement connected to the latter

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to use it as optimally as possible. The concentrator should be constructed as simply as possible in order to actually be Save effort.

The object of the present invention is therefore to specify a switching network that can produce a lot with the least possible effort number of input lines can connect to a variety of output lines, with a modular structure is to be achieved, which requires little basic effort and which can easily be expanded to include additional lines is, whereby the total expenditure increases approximately linearly with the number of lines.

According to the invention, this object is achieved in that a memory is provided which has at least a number of memory locations equal to the number of channel modules, each channel module being assigned a single memory location, that an addressing device addresses all memory locations cyclically one after the other and in parallel therewith the respectively assigned channel module with the internal time division multiplex line connects, the address cycle being equal to the sampling period of the signals from the subscriber modules that the output of the memory in parallel with one number decoder each for each subscriber module is connected, which decode different numbers for different subscriber modules, a number decoder decoding its number the associated subscriber module with the internal time multiplex line connects, and that a control arrangement for establishing a connection between a subscriber module and the number of the subscriber module associated with a channel module in the memory location assigned to this channel module Number decoder writes.

When these measures according to the invention are used, only a small amount of effort is required, namely as a basic effort the memory and the addressing device, while each connected line is a channel module or a subscriber module requires, which essentially only contains switches,

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each controlled by a decoder.

In order to be able to easily recognize the call of a subscriber who has not yet been assigned and to establish a connection depending on this it is advisable that the number of storage locations is at least 1 greater than the number of channel modules that each subscriber module has a call signal output connected by the associated number decoder shows that all call signal outputs via the internal Zeitig multiplex lines are connected to one another and to the control arrangement, and that the control arrangement is in the memory location, which is not assigned to any channel module, the numbers at least one after the other in different address cycles of the unoccupied subscriber modules and the internal time division multiplex line when reading out this memory location checks for a ringing signal.

For a simple control it is expedient that the control arrangement is in the memory locations which are not assigned to any connection writes a number that is not decoded by any existing number decoder. This creates a nonexistent connection treated as a connection with a nonexistent subscriber line, so that the Control in this case runs in exactly the same way like a switched connection.

In a particularly simple embodiment, the addressing device is a cyclic binary counter. Such counters have a simple structure and their outputs can be general can be connected directly to the address inputs of conventional memories.

By using the internal time division multiplex line, each subscriber module or channel module in each Address cycle only transmit one sample of the signal to be transmitted. These samples become general not analog, but digitally transmitted by an analog-digital-

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Converter, each a multi-bit code word to the parallel or serial transmission generated, or a delta modulator arranged / whose output signals are always transmitted serially will. It is useful that the addressing device sends a clock signal via a clock line with each address cycle at least all subscriber modules to synchronize their sampling. That way is the Synchronization of the analog-digital conversion and sampling in the subscriber modules with the internal clock of the switching network accessible.

If a binary counter is used as the addressing device, the clock rate can particularly easily reach the highest output Valence or derived from the carry signal.

The addresses within the address cycle appear with a very high frequency. Since the clock signal accordingly the length of an address cycle is lower, slower switching can be used in the channel modules and subscriber modules.

2Q can be used. So that these circuits after a Clock signal have settled safely before the first address of a cycle is applied, it is advisable that the Addressing device, the addressing of the channel modules and for each clock signal during a predetermined period of time the participant module interrupts. The implementation of such an interruption is in the further subclaims marked.

Embodiments of the invention are explained in more detail below with reference to the drawing. Show it:

1 shows an exchange for decentralized switching for connection to a high-speed time division multiplex line,

Fig. 2 is used therein, constructed according to the invention Switching matrix,

3 shows the schematic structure of a subscriber module.

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In Fig. 1, the subscriber station shown is a Receiving-side time division multiplex line-1 and connected to a transmitting-side time division multiplex line 11, which these Connect subscriber station with other subscriber stations.

Each time division multiplex line carries a signal with a given large number of individual time-interleaved channels. To synchronize the subscriber station with these channels, both time division multiplex lines 1 and 11 are connected a time slot counter 2 or 4 connected, their position indicates the channel from which the signals are present on the time division multiplex lines 1 or 11 · at a given moment.

A call detector is also connected to the time division multiplex line 1, which signal combination is defined as a call is detected in a channel and the channel number sent by the time slot counter via output 3 is stored. One Control 14, which can be designed as a computer, for example, asks the call detector via bus 15 or the channel number stored therein and then takes over the information via the adaptation circuit 12 in this channel to evaluate the call and to establish the associated connection.

The connection between the time division multiplex line 1 or and the subscriber devices 18-1, 18-2 to 18-N take place via the so-called service modules 10-1 to 10-n, which are controlled by a channel control arrangement 8. This channel control 8 contains, for example, a memory that is derived from the channel numbers on the output line 3 of the time slot counter 2 or, on the transmission side, is controlled by the channel numbers on the output line 5 of the time slot counter 4 and the in a memory location which belongs to a channel of the time division multiplex signal on the time division multiplex line 1, which with a Subscriber of this subscriber station is to be connected, the address of a service module contains, all in parallel is supplied via line 7 or on the transmission side via line 9, with each service module on the transmission side and em-

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on the receiving side each contains a decoder for its number.

If a decoder responds », the time in this channel is

about matching circuits

multiplex line 1 or 11 / with the corresponding subscriber line tied together.

An outgoing call from a subscriber is made in a service module 10-1 to 10-n connected to this subscriber received and received therein from the central control arrangement 14 via the line 15 by periodically polling all service

! 0 modules recognized and evaluated. The controller 14 then initiates the transmission of the call code with the address of the calling and called subscriber via the relevant person Service module. The precise functions are not essential to the present invention and so will be not further described.

Since the service modules 10-1 to 10-n represent a certain effort and, on the other hand, the subscribers only to one Fraction of the total time are occupied, a concentrator 16 is provided in a manner known per se, which is here between the individual subscribers 18-1, 18-1 to 18-N and the service modules 10-1 to 10-n is switched. This concentrator 16 is controlled by the controller 14. controlled via the multiple line 15, this control and the structure of the concentrator 16 according to the invention is explained in more detail below with reference to FIG.

The individual subscribers are connected to an internal time division multiplex line via subscriber modules 48-1, 48-2 to 48-255 so 41 connected. It is assumed that any signal conversion and formatting have already taken place beforehand has, so that the subscriber module only has to transmit serial data and thus from switches or switched Amplifiers can be constructed.

A possible structure of a subscriber module 48 is shown in FIG shown. In this embodiment, 5 lines leading to the subscriber are shown, and the internal time

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multiplex line 41 therefore also contains 5 lines here. The two lines 5-1 include the data lines separated for both directions, the two lines 53 represent the signaling lines, and the output 59 is activated when a call is requested, i.e. when the subscriber's receiver has been lifted.

is

With the data lines 51 / in from the subscriber to the inter-

leading .line, A time division multiplex line 41 / a switched amplifier 50 provided, which is switched or blocked through a signal at the input 57. In the from the internal time division multiplex line 41 leading to the subscriber line is a D-flip-flop, which is the from the internal time division multiplex line 41 receives incoming information with a signal at input 57 and forwards it to the subscriber. In the same In this way, the elements 54 and 56 work in the signaling lines 53. There is only one switched in the call line Amplifier 58 is provided since there is no return line for this. The internal time division multiplex line 41 thus contains 5 individual lines.

The example described here represents only one possibility, as the data and the signaling characters, for example can also be transmitted over a pair of lines or just one line for both directions. the The line for the call outputs 59 can also be routed separately, as it is not connected to the channel modules, as will be explained later.

The input 57 of each subscriber module 48 is controlled by an associated number decoder 46, i.e. the subscriber module 48-1 is controlled by the number decoder 46-1, etc. The number decoders 46-1 to 46-255 are parallel connected to the data output 37 of a memory 32, which here also actually consists of several individual parallel Data lines for transmitting a code word containing several bits each. With 8 parallel data

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line, 256 different code combinations or numbers are possible, and each number is assigned to only one the number decoder 46-1 to 46-255 decodes, so that each participant is assigned a number or vice versa.

The internal time division multiplex line 41 is also connected to a number of channel modules 44-5 to 44-28. These are also constructed according to the in Fig. Manner shown in Figure 3, only the calling line with the zugehöri-S ^s switched amplifier 58 is missing. Each channel module 44 is connected to an address decoder 42 in the same way as with the subscriber modules, ie the channel module 44-5 is connected to the address decoder 42-5, etc. The inputs of the address decoders 42 are all parallel via the multiple line 35 with the output of a binary counter 34 _r connected wherein responsive to each counting position another address decoder. However, an address decoder is not provided for some addresses, as will be explained later.

Furthermore, a module 40 is also provided, which is only connected to the call line connecting the outputs 59 of the subscriber modules 48 the internal time division multiplex line 41 is connected and the signal of a control arrangement 30 feeds when the Module 40 driving address decoder 38, which is also connected to the address line 45, its assigned Address received and decoded. The outputs of the channel modules 44 are with the corresponding multiple input one permanently assigned service module 10-1 to 10-n, where η has the value 24 here.

The memory 32 is also connected with its address inputs to the address line 35, which with the output of the counter 34 is connected. This counter receives a clock signal with the frequency via a 1: 2 scaler 36 of the word clock on the external multiplex lines 1 or 11 in Fig. 1. Since this clock signal is constantly present,

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the counter 34 runs continuously through all its positions, and "the same memory location in memory 32 is read out for each position, and in the case of a part of the positions, namely positions 5-28 in decimal notation, each becomes a channel module 44 switched through, which connects the internal time division multiplex line with a service module 10 assigned to the channel module in Fig. 1 connects.

Each storage location of the memory 32 contains 8 bits, each of which represents a number. As for the number 0 no number decoder 46 is provided, this number is contained in the memory locations whose addresses do not contain Channel module is assigned or whose channel module is not assigned to a connection. However, if there is a other number is, when this address is reached by the counter 34 is assigned to this address Channel module 44 of the service module in question is connected to the internal time division multiplex line 41, which at the same time has connected to the subscriber module assigned to the number contained in the address with the relevant subscriber will. In this way, a subscriber with a specific service module 10 in FIG. 1 becomes with each address cycle tied together. The numbers are written into the memory 32 by the control arrangement 30, which is part of the central Controller 14 in Fig. 1 can be or is controlled by this. For this purpose, the control arrangement 30 over the line 31 the bit combination corresponding to the number of the desired subscriber to be written to the data input of the memory 32 is applied, and via the line 33, the memory 32 is temporarily changed from reading to writing switched. This happens with the address that is assigned to the channel module 44 or the service module 10, over which the connection should run. For this, the control arrangement 30 is also provided with the address multiple line tied together. Instead, if the memory 32 can write and read out at different addresses at the same time

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can be supplied via the line 33, the write address.

The writing of a number in the memory 32 represents

_{c represents} part of a connection setup. An incoming call is evaluated by the central controller 14, as has been described with reference to the explanation of FIG. The address of the called subscriber thus determines the number to be written in, while the address in which this number is written is given by any free channel module and service module. In the case of an outgoing call from a connected subscriber, this must first be evaluated. For this purpose, the control arrangement 30 writes the number of an unoccupied subscriber to an address of the memory 32 which is not assigned to a channel module 44 but to the module 40, for which the address 0 is preferably used. As soon as this address is read out, the call request of this subscriber is fed to the control arrangement 30 via the output 59 of the associated subscriber module 48, the internal time division multiplex line 41 and the module 40. If there is a call request, the control arrangement 30 then writes this number into an address of the memory 32 which is assigned to an unoccupied channel module, and the further connection is set up via the associated service module under the control of the central control arrangement 14.

If, on the other hand, there is no call request, the next or in one of the next address cycles a different number is written into address 0 and the one belonging to this number Subscriber queried for his call request, etc. With a prescribed minimum reaction time of, for example 70ms, there can be many address cycles between each query of a participant in which no query is made to relieve the internal control.

A connected participant receives a signal bit with each address cycle and at the same time emits a signal bit,

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if separate lines are used for both directions. To the processing of these bits in the other subscriber circuits to synchronize with the internal connection, all participants and simplicity for the sake of all service modules a clock signal derived from the address cycle is also supplied. This is done by the binary counter 34 is generated on the output line 39, for which the simplest is the output of the highest value or the carry output is used so that the clock signal on line 39 at address 0 is generated. Since this clock signal several Can trigger processes in the subscriber circuits, the subscriber modules cannot be switched through immediately thereafter 48 take place. For this reason, a channel module is only assigned to decimal address 5, namely the Channel module 44-5, and a subscriber who is connected to this channel module by setting up a connection accordingly thus at the earliest not scanned until a time corresponding to 5 addresses after the clock signal on the line 39. At a A binary counter generates the word clock on the external time division multiplex line 1 or 11 with a frequency of 4.096 MHz 34 with 5 bits, i.e. with 32 positions, taking into account the divider 36, a clock signal on the line 39 with a Frequency of 64KHz. The time between this clock signal and the earliest sampling is thus approx. 2.5us, which is the same should be sufficient. For safety reasons against clock fluctuations, the last three addresses of the address cycle are also included no channel modules assigned, but the last channel module is assigned to address 28.

The switching matrix shown in FIG. 2, like the subscriber station shown in FIG. 1, can have a modular structure i.e. not all service modules 10 in Fig. 1 and the corresponding channel modules in Fig. 2 and also not all subscriber modules 48 in Fig. 2 are present. This allows the plant to grow Traffic volume can be easily adjusted.

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Claims (9)

PHILIPS PATENTVERWALTUNG GMBH PHD 80-073 PATENT CLAIMS Ml switching matrix for optionally connecting a number of Channel modules each with one of a larger number of subscriber modules via an internal time division multiplex line, which connects all channel modules and all subscriber modules with one another, in particular for use as a concentrator, characterized in that a memory (32) is provided which has a number of memory locations at least equal to the number of channel modules (44-5 to 44-28), each channel module having one only memory space is permanently assigned that an addressing device (34) cyclically successive all memory locations are repeatedly addressed and, in parallel, the respectively assigned channel module with the internal Time division multiplex line (41) connects, the address cycle being equal to the sampling period of the signals the subscriber modules (48-1 to 48-255) is that the output (37) of the memory (32) in parallel with one each Number decoder (46-1 to 46-255) for each subscriber module (48-1 to 48-255) connected for different Subscriber modules decode different numbers, with a number decoder that decodes its number the associated subscriber module connects to the internal time division multiplex line (41), and that a control arrangement (30) for establishing a connection between a subscriber module and a channel module in the memory location assigned to this channel module, the number of the number decoder belonging to the subscriber module enrolls. 2. Switching matrix according to claim 1, characterized in that the number of storage locations is at least 1 greater is than the number of channel modules (44-5 to 44-28), 130052/0277 * PHD 80-073 that each participant module (48-1 to 48-255) has one of the associated number decoder "(46-1 to 46-255) switched call signal output (59) has that all Call signal outputs via the internal time division multiplex line (41) with each other and with the control arrangement (30) are connected, and that the control arrangement in the memory location which is not assigned to any channel module, in different Address cycles one after the other writes the numbers of at least the unused subscriber modules and when reading out this memory location, the internal time division multiplex line checks for a ringing signal. 3. Switching matrix according to claim 1 or 2, characterized in that the control arrangement (30) in the no connection assigned memory locations writes a number that is not used by any existing number decoder (46-1 to 46-255) is decoded. 4. Switching matrix according to claim 1 or one of the following, characterized in that the addressing device (34) is a cyclic binary counter. 5. Switching matrix according to claim 1 or one of the following, characterized in that the addressing device (34) for each address cycle, a clock signal via a clock line (39) to at least all subscriber modules (48-1 to 48-255) to synchronize their sampling. 6. switching matrix according to claim 4 and 5, characterized in that that the clock signal is the signal of the most significant output or a carry signal of the binary counter (32) is. 7. Switching matrix according to claim 5 or 6, characterized in that the addressing device (34) for each clock signal the address 130052/0277 3? HD 80-073 the channel modules (42-5 to 42-28) and the subscriber modules (48-1 to 48-255) are interrupted. 8. Switching matrix according to claim 7, characterized in that at least with continuously generated address sequence the addresses immediately following the clock signal are not assigned to any channel module (44-5 to 44-28) are. 9. switching matrix according to claim 8, characterized in that the immediately preceding the clock signal Addresses are not assigned to any channel module (44-5 to 44-28). 130052/0277