CN115297089B - Full-automatic address allocation system and method - Google Patents
Full-automatic address allocation system and method Download PDFInfo
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- CN115297089B CN115297089B CN202210916682.5A CN202210916682A CN115297089B CN 115297089 B CN115297089 B CN 115297089B CN 202210916682 A CN202210916682 A CN 202210916682A CN 115297089 B CN115297089 B CN 115297089B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The invention provides a full-automatic address allocation system and method, comprising the following steps: the programmer sends the comparison number to each decoder when the address allocation is carried out; each decoder feeds back a response signal when the comparison number is larger than the random number of the decoder; the programmer reduces the comparison number when receiving the response signal, and sends the reduced comparison number to each decoder after each reduction, and increases the comparison number when not receiving the response signal, and sends the increased comparison number to each decoder after each increase until the comparison number cannot be increased or decreased, and sends the current comparison number to each decoder; when the response signal is received later and the time sequence is wrong, the programmer controls each decoder feeding back the response signal to regenerate random numbers for comparison, and when the response signal is correct in time sequence, address allocation is carried out on the decoders feeding back the response signal until all the decoders finish the address allocation. The full-automatic address allocation method has the advantages that full-automatic address allocation can be carried out on all decoders on the DMX signal line, and manual operation is not needed.
Description
Technical Field
The invention relates to the technical field of decoder address allocation, in particular to a full-automatic address allocation system and method.
Background
The LED (light-emitting diode) dynamic control system is widely used in the decoration of stage, street, bridge, building, etc., and most of the LED dynamic control system adopts the DMX512 (Digital Multiple X) protocol, one of the key points in the DMX512 protocol is the address setting of the decoder, and the address setting method of the decoder currently on the market includes a physical setting method, a decoder serial connection method, a new address line method and a programmer method, although the address setting of the decoder can be realized, the address setting of the decoder needs to be performed by additionally setting a dial switch, or the address setting needs to be performed by serially connecting the decoders, or the address setting of other decoders needs to be affected by the damage of a single decoder due to the fact that an operator writes the address one by using the programmer, which not only slows down the efficiency and increases the cost.
Disclosure of Invention
In order to solve the problems in the prior art, the present invention provides a full-automatic address allocation system, including:
two data dimming protocol signal lines, wherein a plurality of decoders are connected in parallel on the two data dimming protocol signal lines;
the programmer is connected in parallel with the two data dimming protocol signal lines and communicated with the decoders through the data dimming protocol signal lines, and is used for sending a preset comparison number to each decoder when any decoder is subjected to address allocation;
each decoder is used for comparing the comparison number with a random number generated by the decoder and feeding back a response signal to the programmer when the comparison number is larger than the random number;
the programmer is further configured to reduce the comparison number and send the reduced comparison number to each of the decoders after each reduction when any one of the response signals is received, and to increase the comparison number and send the increased comparison number to each of the decoders after each increase when the response signal is not received until the comparison number cannot be reduced or increased;
the programmer is further configured to control each decoder feeding back the response signal to regenerate the random number and compare with the preset comparison number when the response signal corresponding to the current comparison number is received and the timing sequence of the response signal is wrong, and perform address allocation on the decoder feeding back the response signal when the response signal corresponding to the current comparison number is received and the timing sequence of the response signal is correct, until all the decoders complete address allocation.
Preferably, the programmer includes:
a comparison number adjustment module for reducing the comparison number by a dichotomy and transmitting the reduced comparison number to each of the decoders after each reduction when any one of the response signals is received, and increasing the comparison number by a dichotomy and transmitting the increased comparison number to each of the decoders after each increase when the response signal is not received until the comparison number cannot be reduced or increased, and transmitting the current comparison number to each of the programmers;
the random number verification module is connected with the comparison number adjustment module and is used for verifying the response signal when receiving the response signal corresponding to the current comparison number, and generating a control signal when the verification result shows that the time sequence of the response signal is wrong; generating an address allocation signal when the verification result indicates that the time sequence of the response signal is correct;
the random number generation module is connected with the random number verification module and used for controlling each decoder feeding back the response signal according to the control signal to regenerate the random number and compare the random number with the preset comparison number;
the address storage module is used for sequentially storing a plurality of addresses to be allocated in an address set;
and the address distribution module is respectively connected with the random number verification module and the address storage module and is used for distributing the last address ordered in the address set to the decoder associated with the address distribution signal according to the address distribution signal and deleting the last address ordered in the address set.
Preferably, the programmer includes:
the data dimming communication circuit is respectively connected with the decoders, the comparison number adjustment module, the random number verification module and the address allocation module and is used for receiving the response signals sent by the decoders and allocating addresses for the decoders;
the interface communication circuit is respectively connected with the data dimming communication circuit and the comparison number adjusting module and is used for receiving an address allocation instruction input from the outside to control the comparison number adjusting module to send the preset comparison number to each decoder.
Preferably, the programmer is connected with an upper computer, and the upper computer outputs the address allocation instruction to the interface communication circuit to control the comparator adjustment module to send the preset comparison number to each decoder.
Preferably, the data dimming communication circuit includes:
the data dimming chip is characterized in that a first pin of the data dimming chip is connected with one data dimming protocol signal wire, a fourth pin of the data dimming chip is connected with the other data dimming protocol signal wire, a second pin of the data dimming chip is connected with a third pin, a fifth pin of the data dimming chip is grounded, and an eighth pin of the data dimming chip is connected with an external power supply;
one end of the first resistor is connected with a sixth pin of the data dimming chip, and the other end of the first resistor is connected with the external power supply;
one end of the second resistor is connected with the sixth pin, and the other end of the second resistor is grounded;
one end of the third resistor is connected with a seventh pin of the data dimming chip, and the other end of the third resistor is connected with the external power supply;
one end of the fourth resistor is connected with one end of the third resistor, and the other end of the fourth resistor is grounded;
one end of the fifth resistor is connected with one end of the second resistor, and the other end of the fifth resistor is connected with one end of the fourth resistor;
the data dimming chip receives the response signals sent by the decoders through the first pin, and sends the address with the last comparison number or sorting to the decoders through the fourth pin.
Preferably, the fourth pin is a data sending pin, and the first pin is a general input/output pin.
The invention also provides a full-automatic address allocation method which is applied to the full-automatic address allocation system and comprises the following steps:
step S1, when address allocation is carried out on each decoder, the programmer sends a preset comparison number to each decoder;
step S2, each decoder compares the comparison number with a random number generated by the decoder, and judges whether the comparison number is larger than the random number or not:
if yes, feeding back a response signal to the programmer, and then turning to step S3;
if not, not replying;
step S3, the programmer judges whether the response signal is received or not:
if not, the comparison number is increased, the increased comparison number is sent to each decoder after each increase, then the step S2 is returned until the comparison number cannot be increased, the current comparison number is sent to each decoder, and then the step S4 is turned to;
if yes, reducing the comparison number, sending the reduced comparison number to each decoder after each reduction, returning to the step S2, sending the current comparison number to each decoder until the comparison number cannot be reduced, and then turning to the step S4;
step S4, the programmer judges whether the received response signal time sequence corresponding to the current comparison number is correct or not:
if yes, address allocation is carried out on the decoder feeding back the response signal, the decoder carrying out address allocation is configured to quit receiving the comparison number, and then the step S5 is carried out;
if not, controlling each decoder feeding back the response signals to regenerate the random number, and then returning to the step S1;
step S5, the programmer sends a preset maximum value to each decoder as the comparison number, and determines whether the corresponding response signal is received or not:
if yes, returning to the step S1;
if not, characterizing that all the programmers complete address allocation, and then exiting.
Preferably, in the step S3, the programmer decreases the comparison number or increases the comparison number by a dichotomy.
The technical scheme has the following advantages or beneficial effects:
1) The full-automatic address distribution system and the full-automatic address distribution method can carry out full-automatic address distribution on all decoders on the DMX signal line without manual operation, thereby realizing high-efficiency address coding, saving the hardware cost of a decoder dial switch and avoiding the complicated operation of setting the dial switch by the decoder;
2) The full-automatic address allocation system and the method of the invention connect the decoders in parallel on the DMX signal line, and the normal use of other decoders can not be influenced by the damage of one decoder.
Drawings
FIG. 1 is a schematic diagram of the system according to the preferred embodiment of the present invention;
FIG. 2 is an electrical schematic diagram of a data dimming communication circuit according to a preferred embodiment of the present invention;
FIG. 3 is a flow chart showing the steps of the method according to the preferred embodiment of the present invention.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples. The present invention is not limited to the embodiment, and other embodiments may fall within the scope of the present invention as long as they conform to the gist of the present invention.
In accordance with the foregoing and other problems of the prior art, the present invention provides a fully automatic address allocation system, as shown in fig. 1, comprising:
two data dimming protocol signal lines 1, wherein a plurality of decoders 2 are connected in parallel on the two data dimming protocol signal lines 1;
the programmer 3 is connected in parallel to the two data dimming protocol signal lines 1 and is communicated with each decoder 2 through the data dimming protocol signal lines 1, and is used for sending a preset comparison number to each decoder 2 when any decoder 2 is subjected to address allocation;
each decoder 2 is used for comparing the comparison number with a random number generated by the decoder itself, and feeding back a response signal to the programmer 3 when the comparison number is larger than the random number;
the programmer 3 is further configured to reduce the comparison number when any response signal is received, and send the reduced comparison number to each decoder 2 after each reduction, and increase the comparison number and send the increased comparison number to each decoder 2 after each increase when no response signal is received, until the comparison number cannot be reduced or increased, and send the current comparison number to each decoder 2;
the programmer 3 is further configured to control each decoder 2 feeding back the response signal to regenerate the random number to compare with the preset comparison number when receiving the response signal corresponding to the current comparison number and the timing error of the response signal, and perform address allocation on the decoders 2 feeding back the response signal when receiving the response signal corresponding to the current comparison number and the timing error of the response signal is correct until all the decoders 2 complete address allocation.
In particular, in this embodiment, considering that the address setting method for the decoder 2 currently on the market includes a physical setting method, a decoder serial connection method, a newly added address line method and a programmer method, where the physical setting method adopts a dial switch to set the address of the decoder 2, or the decoder 2 uses a nixie tube to display and press keys to set the address, the former needs to use a 9-bit dial switch to represent 512 addresses, and a corresponding table of a dial switch code (2 system) and an equipment address (10 system) is needed, the latter uses a nixie tube to intuitively display the addresses, so that the complicated operation of table lookup is omitted, but compared with the former, the hardware cost of the latter decoder 2 is higher, the obvious disadvantage of this physical setting method is that an operator is required to set the addresses on site of one decoder 2, the efficiency is low, and the sequence of the decoder 2 with the set address cannot be misplaced when being installed, while the fully automatic address allocation system in this embodiment can fully automatically complete the address allocation of all decoders 2, so that the manual operation is more convenient and the error rate is low.
Preferably, the decoder serial connection method corresponds the addresses of the decoders 2 to serial positions one by one, when the 1 st decoder 2 receives the DMX512 data, the 1 st data is intercepted, the rest other data is forwarded unchanged, the 2 nd decoder 2 is identical to the 1 st decoder 2, the method changes the original parallel connection mode of the decoders 2, the method has obvious and fatal defects, firstly, the decoders 2 increase the hardware cost of a DMX signal transmitting module, then the response speed of the decoders 2 is slow, the decoders 2 cannot simultaneously realize dynamic effects because the signals are transmitted in series, when one of the decoders 2 is damaged, the later decoders 2 cannot receive the DMX signals, and the full-automatic address distribution system in the embodiment connects the decoders 2 in parallel on the DMX signal line, so that the normal use of the other decoders 2 cannot be influenced due to the damage of one of the decoders 2.
Preferably, the new address line method connects the decoders 2 in series by adding an additional address line, similar to the serial connection method of the decoders 2 in concept, but separately processes the address allocation and the data communication, so that the method solves the problem that the response speed of the decoders 2 is slow, but the decoders 2 also newly increase the hardware cost of a group of address transceiving circuits, and the addition of an address line increases the workload for the wiring of the system, and meanwhile, the problem that when one of the decoders 2 is damaged, the following decoders 2 cannot receive the address signals cannot be solved, and the full-automatic address allocation system in the embodiment only uses two data dimming protocol signal lines 1, has lower cost and does not have the problem of receiving the address signals.
Preferably, the programmer method uses the programmer 3 to write the addresses of the decoders 2, so that the hardware cost of a physical setting method is saved, and the hardware cost of the whole decoding system of a newly added address line method is also saved.
In particular, in this embodiment, the full-automatic address allocation system utilizes the original data dimming protocol signal line 1 to perform full-automatic address allocation on all decoders 2 connected in parallel, so that not only is efficient address coding realized, but also hardware cost of a dial switch of the decoders 2 is saved, especially tedious operation (address checking table) of setting the dial switch by the decoders 2 is avoided, and because the decoders 2 are connected in parallel on the data dimming protocol signal line 1, no address allocation or signal control will affect use of other decoders 2 due to damage of one of the decoders 2, and when the decoders 2 are installed, the decoders 2 are not addressed from factory, so that random installation can be performed, and after the installation is completed, operators can sit on the decoders 2 on a construction site to perform very visual address allocation and modification by a computer.
Preferably, the decoder 2 that completes the address allocation will exit the comparison of the comparison numbers.
Specifically, in this embodiment, the programmer 3 may send an address scan instruction to query the decoder 2 corresponding to the address, where the address scan instruction is the start code (=1) +sub-instruction (01) +address, for example, the programmer 3 sends 0x010x010x02 to query the decoder 2 with the address 2.
Preferably, the programmer 3 may send an address modification instruction to modify the decoder 2 of the corresponding address, the address modification instruction being the start code (=1) +sub-instruction (02) +address, e.g. the programmer 3 sends 0x010x020x0203 may modify the decoder 2 of address 2 to address 3.
Preferably, the programmer 3 may send an address deletion instruction to delete the address of the corresponding decoder 2, where the address deletion instruction is a start code (=1) +sub-instruction (03) +address, and for example, the programmer 3 sends 0x010x030x03 to delete the address of the decoder 2 with the address 3.
Preferably, the address allocation instruction sent by the programmer 3 is a start code (=1) +sub-instruction (04); all address allocation instructions are start code (=1) +sub-instruction (04) +sub-instruction (01); the extended address allocation instruction is a start code (=1) +sub-instruction (04) +sub-instruction (02); the start allocation command is a start code (=1) +sub-command (04) +sub-command (03), and after receiving the start address allocation command, the decoder enters an address allocation mode, automatically exits the address allocation mode after 10 minutes, and returns to the DMX normal command mode. Upon receiving the exit compare instruction, the address allocation mode is immediately exited. The exit comparison instruction is a start code (=1) +sub-instruction (04), the programmer finds a decoder with the unique minimum random number, and after an address which is not allocated to the decoder is allocated to the decoder, the exit comparison instruction is sent, and the current decoder does not respond to the comparison instruction of the programmer any more. The address programming instruction is the start code (=1) +sub-instruction (04) +sub-instruction (05) +address, and the programmer assigns an address to the current decoder according to the address programming instruction. The random number checking instruction is the start code (=1) +sub-instruction (04) +sub-instruction (06) +address, and the decoder random value is judged to be equal to the programmer comparison value, equal to the reply YES, and unequal and non-reply. The send random number instruction is the start code (=1) +sub-instruction (04) +sub-instruction (07) +random number, and the programmer sends 24-bit random numbers to the decoder as programmer random numbers through the send random number instruction. The random number instruction is the start code (=1) +sub-instruction (04) +sub-instruction (08), after the decoder receives the instruction, the decoder generates 24-bit random number (0 < random number <0 xFFFFF), when the random numbers generated by a plurality of decoders are the same, i.e. the replies received by the programmer are always in error in time sequence, at the moment, the programmer sends the instruction once again, and the decoder regenerates the random number once again. The random number comparison instruction is a start code (=1) +sub-instruction (04) +sub-instruction (09), after the decoder receives the instruction, the random number of the decoder is compared with the random number of the programmer, when the random number of the decoder < = the comparison number of the programmer, YES is recovered, and otherwise, no information is recovered.
Preferably, the maximum value of the comparison number is 0xFFFFFF, the minimum value is 0, and the value range of the random number is 0 to 0xFFFFF.
In a preferred embodiment of the present invention, the programmer 3 comprises:
a comparison number adjustment module 31 for reducing the comparison number by a dichotomy and transmitting the reduced comparison number to each decoder 2 after each reduction when any response signal is received, and for increasing the comparison number by a dichotomy and transmitting the increased comparison number to each decoder 2 after each increase when no response signal is received until the comparison number cannot be reduced or increased, and transmitting the current comparison number to each decoder;
a random number checking module 32, connected to the comparison number adjusting module 31, for checking the response signal when receiving the response signal corresponding to the current comparison number, and generating a control signal when the checking result indicates that the time sequence of the response signal is wrong; generating an address allocation signal when the verification result indicates that the time sequence of the response signal is correct;
a random number generation module 33, connected to the random number verification module 32, for controlling each decoder 2 feeding back the response signal according to the control signal to regenerate a random number for comparison with a preset comparison number;
an address storage module 34 for sequentially storing a plurality of addresses to be allocated in an address set;
an address allocation module 35, respectively connected to the comparison number adjustment module 31 and the address storage module 34, is configured to allocate the last address ordered in the address set to the decoder 2 associated with the address allocation signal according to the address allocation signal, and delete the last address ordered in the address set.
In a preferred embodiment of the present invention, the programmer 3 comprises:
the data dimming communication circuit 36 is respectively connected with each decoder 2, the comparison number adjustment module 31, the random number verification module 32 and the address allocation module 35, and is used for receiving response signals sent by each decoder 2 and allocating addresses to each decoder 2;
an interface communication circuit 37, the interface communication circuit 37 is respectively connected to the data dimming communication circuit 36 and the comparison number adjusting module 31, and is configured to receive an address allocation command input from the outside to control the comparison number adjusting module 31 to send a preset comparison number to each decoder 2.
In the preferred embodiment of the present invention, the programmer 3 is connected to a host computer 4, and the host computer 4 outputs address allocation instructions to the interface communication circuit 37 to control the comparison number adjustment module 31 to send preset comparison numbers to each decoder 2.
Specifically, in the present embodiment, the data dimming communication circuit 36 is responsible for communication with the decoder 2, and the main function is to complete address allocation and collection, and the interface communication circuit 37 is responsible for communication with the host computer 4, and the main function is to upload the collected information to the host computer 4 and receive parameters of the host computer 4 to complete address modification.
Preferably, the address of the decoder 2 can be customized by the upper computer 4.
In a preferred embodiment of the present invention, as shown in FIG. 2, the data dimming communication circuit 36 comprises:
the data dimming chip U1, a first pin of the data dimming chip U1 is connected with one data dimming protocol signal line 1, a fourth pin of the data dimming chip U1 is connected with the other data dimming protocol signal line 1, a second pin of the data dimming chip U1 is connected with a third pin, a fifth pin of the data dimming chip U1 is grounded, and an eighth pin of the data dimming chip U1 is connected with an external power supply;
one end of the first resistor R1 is connected with a sixth pin of the data dimming chip U1, and the other end of the first resistor R1 is connected with an external power supply;
one end of the second resistor R2 is connected with the sixth pin, and the other end of the second resistor R2 is grounded;
one end of the third resistor R3 is connected with a seventh pin of the data dimming chip U1, and the other end of the third resistor R3 is connected with an external power supply;
one end of the fourth resistor R4 is connected with one end of the third resistor R3, and the other end of the fourth resistor R4 is grounded;
one end of the fifth resistor R5 is connected with one end of the second resistor R2, and the other end of the fifth resistor R5 is connected with one end of the fourth resistor R4;
the data dimming chip U1 receives the response signal sent by each decoder 2 through the first pin, and sends the comparison number or the last address of the order to each decoder 2 through the fourth pin.
Specifically, in the present embodiment, the external power supply may employ a 5V power supply.
In a preferred embodiment of the present invention, the fourth pin is a transmit data pin, and the first pin is a general purpose input/output pin.
Specifically, in the present embodiment, the fourth pin uses only the data transmission function, the first pin must be used as a general purpose input output pin, and the function of enabling interrupt and the function of timer timing are provided.
In a preferred embodiment of the present invention, a full-automatic address allocation method is further provided, which is applied to the full-automatic address allocation system, as shown in fig. 3, and includes the following steps:
step S1, when address allocation is carried out on each decoder, a programmer sends a preset comparison number to each decoder;
step S2, each decoder compares the comparison number with a random number generated by itself, and judges whether the comparison number is larger than the random number or not:
if yes, a response signal is fed back to the programmer, and then the step S3 is performed;
if not, not replying;
step S3, the programmer judges whether a response signal is received:
if not, the comparison number is increased, the increased comparison number is sent to each decoder after each increase, then the step S2 is returned until the comparison number cannot be increased or decreased, the current comparison number is sent to each decoder, and then the step S4 is returned;
if so, reducing the comparison number, transmitting the reduced comparison number to each decoder after each reduction, returning to the step S2 until the comparison number cannot be increased or decreased, transmitting the current comparison number to each decoder, and then turning to the step S4;
step S4, the programmer judges whether the time sequence of the received response signal corresponding to the current comparison number is correct or not:
if yes, address allocation is carried out on the decoder feeding back the response signal, the decoder carrying out the address allocation is configured to exit the receiving comparison number, and then the step S5 is carried out;
if not, controlling each decoder of the feedback response signal to regenerate the random number, and then returning to the step S1;
step S5, the programmer sends a preset maximum value to each decoder as a comparison number, and judges whether a corresponding response signal is received or not:
if yes, returning to the step S1;
if not, characterizing that all programmers complete address allocation, and then exiting.
In a preferred embodiment of the present invention, in step S5, the programmer uses a dichotomy to decrease the comparison number or increase the comparison number.
Specifically, in this embodiment, the maximum value of the comparison number is 0xFFFFFF, the minimum value is 0, the preset comparison number is the intermediate value of the data interval formed by 0xFFFFFF and 0, and in step S3, when the answer signal is received, the comparison number is increased, and the previous intermediate value and the intermediate value of the data interval formed by 0xFFFFFF are taken, and the like until the difference between the maximum value and the minimum value of the formed data interval is less than or equal to one, the comparison number is considered to be unable to be increased or decreased. The case of decreasing the comparison number and so on will not be described in detail here.
As a preferred embodiment, the specific process of the full-automatic address allocation method in the present technical solution is as follows:
step 1: the programmer sends a 2-way comparison value of 0x800000 to be compared with the random number of the decoder, the random number of the decoder ranges from 0 to 0xFFFFF, if the random number of the decoder on the DMX bus is smaller than or equal to the comparison value of 0x800000, the data YES is replied, otherwise, the data YES is not replied.
Step 2: if no reply is made, the comparison value is indicated to be small, and the 2-way method increases the comparison value to 0xC00000. If there is a reply, the comparison value is further reduced by 2 minutes to 0x400000.
Step 3: the step 2 is repeated until the magnitude of the comparison value cannot be changed using the 2-way method, indicating that the smallest random number has been found.
Step 4: after the device with the smallest random number is found, the current decoder replies the response data YES by using a random number checking instruction, analyzes the time sequence of the reply data, and if the device is in the 3 rd state, the current decoder regenerates the random number and returns to the 1 st step. If it is the 2 nd state, it indicates that the current decoder is unique, and go to the 5 th step.
Step 5: an address is assigned to this device using an address assignment instruction.
Step 6: after the address allocation is completed, the device with the allocated address is logged out of the comparison command by using the log-out comparison instruction.
Step 7: repeating the above steps, comparing to find other decoders. Until no device reply is sent to the 0xFFFFF.
The absence of the reply refers to that the decoder does not reply any data on the DMX bus, and the level of the RXD pin is always high level and no data reply is received by the programmer in a receiving period. The reply, i.e. reply YES, means that the decoder replies data 0xAA on the DMX bus, the programmer can analyze the signal of the RXD pin in one receiving period, if the data 0xAA can be analyzed, the reply is represented, otherwise, because the decoders reply data on the DMX bus at the same time, each reply signal is superimposed, and a time sequence error will occur on the signal of the RXD pin.
The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and drawings, and are intended to be included within the scope of the present invention.
Claims (8)
1. A fully automatic address assignment system, comprising:
two data dimming protocol signal lines, wherein a plurality of decoders are connected in parallel on the two data dimming protocol signal lines;
the programmer is connected in parallel with the two data dimming protocol signal lines and communicated with the decoders through the data dimming protocol signal lines, and is used for sending a preset comparison number to each decoder when any decoder is subjected to address allocation;
each decoder compares the comparison number with a random number generated by the decoder and feeds back a response signal to the programmer when the comparison number is larger than the random number;
the programmer is further configured to reduce the comparison number and send the reduced comparison number to each of the decoders after each reduction when any one of the response signals is received, and to increase the comparison number and send the increased comparison number to each of the decoders after each increase when the response signal is not received until the comparison number cannot be increased or reduced;
the programmer is further configured to control each decoder feeding back the response signal to regenerate the random number and compare with the preset comparison number when the response signal corresponding to the current comparison number is received and the timing sequence of the response signal is wrong, and perform address allocation on the decoder feeding back the response signal when the response signal corresponding to the current comparison number is received and the timing sequence of the response signal is correct, until all the decoders complete address allocation.
2. The fully automatic address assignment system as recited in claim 1, wherein the programmer comprises:
a comparison number adjustment module for reducing the comparison number by a dichotomy and transmitting the reduced comparison number to each of the decoders after each reduction when any one of the response signals is received, and increasing the comparison number by a dichotomy and transmitting the increased comparison number to each of the decoders after each increase when the response signal is not received until the comparison number cannot be reduced or increased, and transmitting the current comparison number to each of the decoders;
the random number verification module is connected with the comparison number adjustment module and is used for verifying the response signal when receiving the response signal corresponding to the current comparison number, and generating a control signal when the verification result shows that the time sequence of the response signal is wrong; generating an address allocation signal when the verification result indicates that the time sequence of the response signal is correct;
the random number generation module is connected with the random number verification module and used for controlling each decoder feeding back the response signal according to the control signal to regenerate the random number and compare the random number with the preset comparison number;
the address storage module is used for sequentially storing a plurality of addresses to be allocated in an address set;
and the address distribution module is respectively connected with the random number verification module and the address storage module and is used for distributing the last address ordered in the address set to the decoder associated with the address distribution signal according to the address distribution signal and deleting the last address ordered in the address set.
3. The fully automatic address assignment system as recited in claim 2, wherein said programmer comprises:
the data dimming communication circuit is respectively connected with the decoders, the comparison number adjustment module, the random number verification module and the address allocation module and is used for receiving the response signals sent by the decoders and allocating addresses for the decoders;
the interface communication circuit is respectively connected with the data dimming communication circuit and the comparison number adjusting module and is used for receiving an address allocation instruction input from the outside to control the comparison number adjusting module to send the preset comparison number to each decoder.
4. The system of claim 3, wherein the programmer is connected to a host computer, and the host computer outputs the address assignment command to the interface communication circuit to control the comparison number adjustment module to send the preset comparison number to each decoder.
5. The fully automatic address assignment system as recited in claim 4, wherein the data dimming communication circuit comprises:
the data dimming chip is characterized in that a first pin of the data dimming chip is connected with one data dimming protocol signal wire, a fourth pin of the data dimming chip is connected with the other data dimming protocol signal wire, a second pin of the data dimming chip is connected with a third pin, a fifth pin of the data dimming chip is grounded, and an eighth pin of the data dimming chip is connected with an external power supply;
one end of the first resistor is connected with a sixth pin of the data dimming chip, and the other end of the first resistor is connected with the external power supply;
one end of the second resistor is connected with the sixth pin, and the other end of the second resistor is grounded;
one end of the third resistor is connected with a seventh pin of the data dimming chip, and the other end of the third resistor is connected with the external power supply;
one end of the fourth resistor is connected with one end of the third resistor, and the other end of the fourth resistor is grounded;
one end of the fifth resistor is connected with one end of the second resistor, and the other end of the fifth resistor is connected with one end of the fourth resistor;
the data dimming chip receives the response signals sent by the decoders through the first pin, and sends the address with the last comparison number or sorting to the decoders through the fourth pin.
6. The fully automatic address assignment system as recited in claim 5, wherein the fourth pin is a transmit data pin and the first pin is a general purpose input output pin.
7. A fully automatic address allocation method, characterized in that it is applied to a fully automatic address allocation system according to any one of claims 1-6, comprising the steps of:
step S1, when address allocation is carried out on each decoder, the programmer sends a preset comparison number to each decoder;
step S2, each decoder compares the comparison number with a random number generated by the decoder, and judges whether the comparison number is larger than the random number or not:
if yes, feeding back a response signal to the programmer, and then turning to step S3;
if not, not replying;
step S3, the programmer judges whether the response signal is received or not:
if not, the comparison number is increased, the increased comparison number is sent to each decoder after each increase, then the step S2 is returned until the comparison number cannot be increased or decreased, the current comparison number is sent to each decoder, and then the step S4 is turned to;
if yes, reducing the comparison number, sending the reduced comparison number to each decoder after each reduction, returning to the step S2 until the comparison number cannot be increased or decreased, sending the current comparison number to each decoder, and then turning to the step S4;
step S4, the programmer judges whether the received response signal time sequence corresponding to the current comparison number is correct or not:
if yes, address allocation is carried out on the decoder feeding back the response signal, the decoder carrying out address allocation is configured to quit receiving the comparison number, and then the step S5 is carried out;
if not, controlling each decoder feeding back the response signals to regenerate the random number, and then returning to the step S1;
step S5, the programmer sends a preset maximum value to each decoder as the comparison number, and determines whether the corresponding response signal is received or not:
if yes, returning to the step S1;
if not, characterizing that all the programmers complete address allocation, and then exiting.
8. The method according to claim 7, wherein in the step S3, the programmer decreases the comparison number or increases the comparison number by a dichotomy.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109041349A (en) * | 2018-09-03 | 2018-12-18 | 深圳市汇德科技有限公司 | It is a kind of that address device and system are write based on LED decoding circuit automatically |
| CN110072322A (en) * | 2019-04-29 | 2019-07-30 | 广州市浩洋电子股份有限公司 | A kind of method of the quick address setting lamps and lanterns DMX |
| CN111147619A (en) * | 2019-12-20 | 2020-05-12 | 海丰通航科技有限公司 | Method and system for realizing automatic address allocation of RS485 slave equipment locally |
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| JP2010212989A (en) * | 2009-03-10 | 2010-09-24 | Freescale Semiconductor Inc | Address decoder and address setting method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109041349A (en) * | 2018-09-03 | 2018-12-18 | 深圳市汇德科技有限公司 | It is a kind of that address device and system are write based on LED decoding circuit automatically |
| CN110072322A (en) * | 2019-04-29 | 2019-07-30 | 广州市浩洋电子股份有限公司 | A kind of method of the quick address setting lamps and lanterns DMX |
| CN111147619A (en) * | 2019-12-20 | 2020-05-12 | 海丰通航科技有限公司 | Method and system for realizing automatic address allocation of RS485 slave equipment locally |
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