WO2024087152A1

WO2024087152A1 - Image processing for partial frame updates

Info

Publication number: WO2024087152A1
Application number: PCT/CN2022/128180
Authority: WO
Inventors: Nan Zhang; Yongjun XU; Xinchao YANG
Original assignee: Qualcomm Incorporated
Priority date: 2022-10-28
Filing date: 2022-10-28
Publication date: 2024-05-02

Abstract

Aspects presented herein relate to methods and devices for display processing including an apparatus, e.g., a CPU. The apparatus may detect at least one condition associated with a partial update of at least one current frame including a set of layers, wherein each of the set of layers includes a plurality of pixels. The apparatus may switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition. Further, the apparatus may configure a DPU to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.

Description

IMAGE PROCESSING FOR PARTIAL FRAME UPDATES

TECHNICAL FIELD

The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display processing.

INTRODUCTION

Computing devices often perform graphics and/or display processing (e.g., utilizing a graphics processing unit (GPU) , a central processing unit (CPU) , a display processor, etc. ) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs are configured to execute a graphics processing pipeline that includes one or more processing stages, which operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize the GPU during execution. A display processor is configured to convert digital information received from a CPU to analog values and may issue commands to a display panel for displaying the visual content. A device that provides content for visual presentation on a display may utilize a GPU and/or a display processor.

A GPU of a device may be configured to perform the processes in a graphics processing pipeline. Further, a display processor or display processing unit (DPU) may be configured to perform the processes of display processing. However, with the advent of wireless communication and smaller, handheld devices, there has developed an increased need for improved graphics or display processing.

BRIEF SUMMARY

The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a central processing unit (CPU) , a display processing unit (DPU) , a graphics processing unit (GPU) , or any apparatus that may perform display processing. The apparatus may configure a DPU to process each of a set of layers of at least one previous frame based on full frame image processing, where at least one current frame is subsequent to the at least one previous frame. The apparatus may also perform a layer parameter run-time analysis for each of a set of layers of the at least one current frame, where at least one condition associated with a partial update of the at least one current frame is detected based on the layer parameter run-time analysis. Additionally, the apparatus may receive at least one signal from an application associated with the at least one current frame, where the at least one condition associated with the partial update of the at least one current frame is detected based on the at least one signal from the application. The apparatus may also detect at least one condition associated with a partial update of at least one current frame including a set of layers, where each of the set of layers includes a plurality of pixels. Moreover, the apparatus may switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition. The apparatus may also configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing. The apparatus may also detect at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, where the at least one subsequent frame is subsequent to the at least one current frame. Further, the apparatus may switch from the per-layer image processing to the full frame image processing for the at least one subsequent frame. The apparatus may also configure the DPU to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing.

The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram that illustrates an example content generation system.

FIG. 2 illustrates an example graphics processing unit (GPU) .

FIG. 3 illustrates an example display framework including a display processor and a display.

FIG. 4 is a diagram illustrating an example mask layer for display processing.

FIG. 5 is a diagram illustrating an example layer composition scheme for display processing.

FIG. 6 is a diagram illustrating an example of a frame enhancement procedure and a frame update procedure.

FIG. 7 is a diagram illustrating an example of a frame enhancement procedure and a frame update procedure.

FIG. 8 is a diagram illustrating example of a composition scheme for display processing.

FIG. 9 is a diagram illustrating an example of a flowchart for display processing associated with partial frame updates.

FIG. 10 is a communication flow diagram illustrating example communications between a CPU, an application, and a DPU.

FIG. 11 is a flowchart of an example method of display processing.

FIG. 12 is a flowchart of an example method of display processing.

DETAILED DESCRIPTION

Some aspects of display processing may utilize a number of different frame enhancement procedures, such as detail enhancement procedures. Detail enhancement (DE) procedures or detail sharpening procedures may be used to increase the quality of images or frames, such as by enhancing the details of the frame. For instance, detail enhancement procedures may increase the high frequency gain and/or high frequency details of images or frames. In display devices (e.g., mobile devices or user equipments (UEs) ) , this function may be used in many different scenarios with adaptive detail enhancement strength. Moreover, detail enhancement procedures may be used as a particular manner in which to optimize the visual quality of the image or frame. Other types of frame enhancement procedures are frame update procedures or partial frame update procedures, which may be used for saving power at display devices. For instance, as different portions of an image or frame change, there may be a need to refresh or update the changing areas of the frame (i.e., pixel-changing areas) , while maintaining other frame areas constant. Accordingly, non-updating portions of a frame may not need to be updated, while the updating portion may be updated. Further, as the display panel size and resolution of display devices (e.g., mobile devices or UEs) continue to increase, the contents of certain portions of images or frames may increasingly change. In some aspects, detail enhancement procedures and partial frame update procedures may be utilized concurrently. For instance, detail enhancement procedures may be utilized with local region processing or convolution-based processing. In these instances, each filtered pixel value may be determined from its neighbor region pixels (e.g., a region of 4x6 pixels, 6x12 pixels, or 8x8 pixels) . Also, partial frame update procedures may be performed on a layer basis. That is, pixels of a same layer in the frame may be updated at the same time. For non-refreshing layer boundary region pixels, their current pixel value may be calculated using a previous frame neighbor layer pixel value convolution. If a neighbor layer pixel has already changed (e.g., changed from a detail enhancement algorithm) , those particular pixels may be refreshed as well. However, a partial frame update procedure may solely update or refresh dirty layer regions. By doing so, the processed neighbor pixels corresponding to the detail enhancement procedure may be ignored. In some instances, detail enhancement procedures and partial frame update procedures may conflict with each other. Indeed, detail enhancement procedures and partial frame update procedures may cause side effects if they are concurrently run on a display device. For instance, when a partial frame update procedure and a detail enhancement procedure are concurrently running, the partially updated region may experience visual displays issues. For example, when a partial frame update procedure and a detail enhancement procedure are concurrently running, the partially updated region may experience edge flickering (i.e., the edges of the region appear to flicker) . These issues may also be associated with frame convolution processing concurrently conflicting with layer basis partial frame update. As indicated herein, when a partial frame update procedure and a detail enhancement procedure are concurrently running, the partially updated region may experience visual displays issues around the region (e.g., edge flickering) . In some aspects, in order to overcome such visual issues, when a partial frame update is used, a detail enhancement procedure may be stopped or closed. However, by doing so, just one of these procedures may be run at a time. Aspects of the present disclosure may simultaneously perform certain types of frame enhancement procedures. In some instances, aspects of the present disclosure may simultaneously perform partial frame update procedures and detail enhancement procedures. For instance, aspects presented herein may concurrently run a partial frame update procedure and a detail enhancement procedure for a display frame without experiencing any visual issues. By doing so, aspects presented herein may solve detail enhancement and partial frame update concurrency issues. Accordingly, aspects presented herein may reduce the amount of visual issues experienced during frame enhancement procedures. That is, aspects presented herein may increase the visual quality and/or user experience of a display device.

Various aspects of systems, apparatuses, computer program products, and methods are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.

Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description. The detailed description and drawings are merely illustrative of this disclosure rather than limiting, the scope of this disclosure being defined by the appended claims and equivalents thereof.

Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, and the like (collectively referred to as “elements” ) . These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors (which may also be referred to as processing units) . Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs) , general purpose GPUs (GPGPUs) , central processing units (CPUs) , application processors, digital signal processors (DSPs) , reduced instruction set computing (RISC) processors, systems-on-chip (SOC) , baseband processors, application specific integrated circuits (ASICs) , field programmable gate arrays (FPGAs) , programmable logic devices (PLDs) , state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system may execute software. Software may be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The term application may refer to software. As described herein, one or more techniques may refer to an application, i.e., software, being configured to perform one or more functions. In such examples, the application may be stored on a memory, e.g., on-chip memory of a processor, system memory, or any other memory. Hardware described herein, such as a processor may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware may access the code from a memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or sub-components of a single component.

Accordingly, in one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise a random access memory (RAM) , a read-only memory (ROM) , an electrically erasable programmable ROM (EEPROM) , optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that may be used to store computer executable code in the form of instructions or data structures that may be accessed by a computer.

In general, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphical content, and/or reducing the load of a processing unit, i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU. For example, this disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

As used herein, instances of the term “content” may refer to “graphical content, ” “image, ” and vice versa. This is true regardless of whether the terms are being used as an adjective, noun, or other parts of speech. In some examples, as used herein, the term “graphical content” may refer to a content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term “graphical content” may refer to a content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term “graphical content” may refer to a content produced by a graphics processing unit.

In some examples, as used herein, the term “display content” may refer to content generated by a processing unit configured to perform displaying processing. In some examples, as used herein, the term “display content” may refer to content generated by a display processing unit. Graphical content may be processed to become display content. For example, a graphics processing unit may output graphical content, such as a frame, to a buffer (which may be referred to as a framebuffer) . A display processing unit may read the graphical content, such as one or more frames from the buffer, and perform one or more display processing techniques thereon to generate display content. For example, a display processing unit may be configured to perform composition on one or more rendered layers to generate a frame. As another example, a display processing unit may be configured to compose, blend, or otherwise combine two or more layers together into a single frame. A display processing unit may be configured to perform scaling, e.g., upscaling or downscaling, on a frame. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have already been blended together to form the frame, i.e., the frame includes two or more layers, and the frame that includes two or more layers may subsequently be blended.

FIG. 1 is a block diagram that illustrates an example content generation system 100 configured to implement one or more techniques of this disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of an SOC. The device 104 may include one or more components configured to perform one or more techniques of this disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder/decoder 122, and a system memory 124. In some aspects, the device 104 may include a number of components, e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. Reference to the display 131 may refer to the one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first and second display may receive different frames for presentment thereon. In other examples, the first and second display may receive the same frames for presentment thereon. In further examples, the results of the graphics processing may not be displayed on the device, e.g., the first and second display may not receive any frames for presentment thereon. Instead, the frames or graphics processing results may be transferred to another device. In some aspects, this may be referred to as split-rendering.

The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing, such as in a graphics processing pipeline 107. The content encoder/decoder 122 may include an internal memory 123. In some examples, the device 104 may include a display processor, such as the display processor 127, to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before presentment by the one or more displays 131. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of: a liquid crystal display (LCD) , a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

Memory external to the processing unit 120 and the content encoder/decoder 122, such as system memory 124, may be accessible to the processing unit 120 and the content encoder/decoder 122. For example, the processing unit 120 and the content encoder/decoder 122 may be configured to read from and/or write to external memory, such as the system memory 124. The processing unit 120 and the content encoder/decoder 122 may be communicatively coupled to the system memory 124 over a bus. In some examples, the processing unit 120 and the content encoder/decoder 122 may be communicatively coupled to each other over the bus or a different connection.

The content encoder/decoder 122 may be configured to receive graphical content from any source, such as the system memory 124 and/or the communication interface 126. The system memory 124 may be configured to store received encoded or decoded graphical content. The content encoder/decoder 122 may be configured to receive encoded or decoded graphical content, e.g., from the system memory 124 and/or the communication interface 126, in the form of encoded pixel data. The content encoder/decoder 122 may be configured to encode or decode any graphical content.

The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or the system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM) , electrically erasable programmable ROM (EEPROM) , flash memory, a magnetic data media or an optical storage media, or any other type of memory.

The internal memory 121 or the system memory 124 may be a non-transitory storage medium according to some examples. The term “non-transitory” may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that internal memory 121 or the system memory 124 is non-movable or that its contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.

The processing unit 120 may be a central processing unit (CPU) , a graphics processing unit (GPU) , a general purpose GPU (GPGPU) , or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into a motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card that is installed in a port in a motherboard of the device 104, or may be otherwise incorporated within a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs) , field programmable gate arrays (FPGAs) , arithmetic logic units (ALUs) , digital signal processors (DSPs) , discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 121, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

The content encoder/decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder/decoder 122 may be integrated into a motherboard of the device 104. The content encoder/decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs) , field programmable gate arrays (FPGAs) , arithmetic logic units (ALUs) , digital signal processors (DSPs) , video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the content encoder/decoder 122 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 123, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information, e.g., eye or head position information, rendering commands, or location information, from another device. The transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving function and/or transmitting function described herein with respect to the device 104.

Referring again to FIG. 1, in certain aspects, the display processor 127 may include a composition component 198 configured to configure a DPU to process each of a set of layers of at least one previous frame based on full frame image processing, where at least one current frame is subsequent to the at least one previous frame. The composition component 198 may also be configured to perform a layer parameter run-time analysis for each of a set of layers of the at least one current frame, where at least one condition associated with a partial update of the at least one current frame is detected based on the layer parameter run-time analysis. The composition component 198 may also be configured to receive at least one signal from an application associated with the at least one current frame, where the at least one condition associated with the partial update of the at least one current frame is detected based on the at least one signal from the application. The composition component 198 may also be configured to detect at least one condition associated with a partial update of at least one current frame including a set of layers, where each of the set of layers includes a plurality of pixels. The composition component 198 may also be configured to switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition. The composition component 198 may also be configured to configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing. The composition component 198 may also be configured to detect at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, where the at least one subsequent frame is subsequent to the at least one current frame. The composition component 198 may also be configured to switch from the per-layer image processing to the full frame image processing for the at least one subsequent frame. The composition component 198 may also be configured to configure the DPU to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing. Although the following description may be focused on display processing, the concepts described herein may be applicable to other similar processing techniques.

As described herein, a device, such as the device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, user equipment, a client device, a station, an access point, a computer, e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device, e.g., a portable video game device or a personal digital assistant (PDA) , a wearable computing device, e.g., a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-car computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein may be described as performed by a particular component (e.g., a GPU) , but, in further embodiments, may be performed using other components (e.g., a CPU) , consistent with disclosed embodiments.

GPUs may process multiple types of data or data packets in a GPU pipeline. For instance, in some aspects, a GPU may process two types of data or data packets, e.g., context register packets and draw call data. A context register packet may be a set of global state information, e.g., information regarding a global register, shading program, or constant data, which may regulate how a graphics context will be processed. For example, context register packets may include information regarding a color format. In some aspects of context register packets, there may be a bit that indicates which workload belongs to a context register. Also, there may be multiple functions or programming running at the same time and/or in parallel. For example, functions or programming may describe a certain operation, e.g., the color mode or color format. Accordingly, a context register may define multiple states of a GPU.

Context states may be utilized to determine how an individual processing unit functions, e.g., a vertex fetcher (VFD) , a vertex shader (VS) , a shader processor, or a geometry processor, and/or in what mode the processing unit functions. In order to do so, GPUs may use context registers and programming data. In some aspects, a GPU may generate a workload, e.g., a vertex or pixel workload, in the pipeline based on the context register definition of a mode or state. Certain processing units, e.g., a VFD, may use these states to determine certain functions, e.g., how a vertex is assembled. As these modes or states may change, GPUs may need to change the corresponding context. Additionally, the workload that corresponds to the mode or state may follow the changing mode or state.

FIG. 2 illustrates an example GPU 200 in accordance with one or more techniques of this disclosure. As shown in FIG. 2, GPU 200 includes command processor (CP) 210, draw call packets 212, VFD 220, VS 222, vertex cache (VPC) 224, triangle setup engine (TSE) 226, rasterizer (RAS) 228, Z process engine (ZPE) 230, pixel interpolator (PI) 232, fragment shader (FS) 234, render backend (RB) 236, level 2 (L2) cache (UCHE) 238, and system memory 240. Although FIG. 2 displays that GPU 200 includes processing units 220-238, GPU 200 may include a number of additional processing units. Additionally, processing units 220-238 are merely an example and any combination or order of processing units may be used by GPUs according to the present disclosure. GPU 200 also includes command buffer 250, context register packets 260, and context states 261.

As shown in FIG. 2, a GPU may utilize a CP, e.g., CP 210, or hardware accelerator to parse a command buffer into context register packets, e.g., context register packets 260, and/or draw call data packets, e.g., draw call packets 212. The CP 210 may then send the context register packets 260 or draw call packets 212 through separate paths to the processing units or blocks in the GPU. Further, the command buffer 250 may alternate different states of context registers and draw calls. For example, a command buffer may be structured in the following manner: context register of context N, draw call (s) of context N, context register of context N+1, and draw call (s) of context N+1.

GPUs may render images in a variety of different ways. In some instances, GPUs may render an image using rendering and/or tiled rendering. In tiled rendering GPUs, an image may be divided or separated into different sections or tiles. After the division of the image, each section or tile may be rendered separately. Tiled rendering GPUs may divide computer graphics images into a grid format, such that each portion of the grid, i.e., a tile, is separately rendered. In some aspects, during a binning pass, an image may be divided into different bins or tiles. In some aspects, during the binning pass, a visibility stream may be constructed where visible primitives or draw calls may be identified. In contrast to tiled rendering, direct rendering does not divide the frame into smaller bins or tiles. Rather, in direct rendering, the entire frame is rendered at a single time. Additionally, some types of GPUs may allow for both tiled rendering and direct rendering.

FIG. 3 is a block diagram 300 that illustrates an example display framework including the processing unit 120, the system memory 124, the display processor 127, and the display (s) 131, as may be identified in connection with the device 104.

A GPU may be included in devices that provide content for visual presentation on a display. For example, the processing unit 120 may include a GPU 310 configured to render graphical data for display on a computing device (e.g., the device 104) , which may be a computer workstation, a mobile phone, a smartphone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, and the like. Operations of the GPU 310 may be controlled based on one or more graphics processing commands provided by a CPU 315. The CPU 315 may be configured to execute multiple applications concurrently. In some cases, each of the concurrently executed multiple applications may utilize the GPU 310 simultaneously. Processing techniques may be performed via the processing unit 120 output a frame over physical or wireless communication channels.

The system memory 124, which may be executed by the processing unit 120, may include a user space 320 and a kernel space 325. The user space 320 (sometimes referred to as an “application space” ) may include software application (s) and/or application framework (s) . For example, software application (s) may include operating systems, media applications, graphical applications, workspace applications, etc. Application framework (s) may include frameworks used by one or more software applications, such as libraries, services (e.g., display services, input services, etc. ) , application program interfaces (APIs) , etc. The kernel space 325 may further include a display driver 330. The display driver 330 may be configured to control the display processor 127. For example, the display driver 330 may cause the display processor 127 to compose a frame and transmit the data for the frame to a display.

The display processor 127 includes a display control block 335 and a display interface 340. The display processor 127 may be configured to manipulate functions of the display (s) 131 (e.g., based on an input received from the display driver 330) . The display control block 335 may be further configured to output image frames to the display (s) 131 via the display interface 340. In some examples, the display control block 335 may additionally or alternatively perform post-processing of image data provided based on execution of the system memory 124 by the processing unit 120.

The display interface 340 may be configured to cause the display (s) 131 to display image frames. The display interface 340 may output image data to the display (s) 131 according to an interface protocol, such as, for example, the MIPI DSI (Mobile Industry Processor Interface, Display Serial Interface) . That is, the display (s) 131, may be configured in accordance with MIPI DSI standards. The MIPI DSI standard supports a video mode and a command mode. In examples where the display (s) 131 is/are operating in video mode, the display processor 127 may continuously refresh the graphical content of the display (s) 131. For example, the entire graphical content may be refreshed per refresh cycle (e.g., line-by-line) . In examples where the display (s) 131 is/are operating in command mode, the display processor 127 may write the graphical content of a frame to a buffer 350.

In some such examples, the display processor 127 may not continuously refresh the graphical content of the display (s) 131. Instead, the display processor 127 may use a vertical synchronization (Vsync) pulse to coordinate rendering and consuming of graphical content at the buffer 350. For example, when a Vsync pulse is generated, the display processor 127 may output new graphical content to the buffer 350. Thus, generation of the Vsync pulse may indicate that current graphical content has been rendered at the buffer 350.

Frames are displayed at the display (s) 131 based on a display controller 345, a display client 355, and the buffer 350. The display controller 345 may receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 may output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 may represent a local memory to the display (s) 131. In some examples, the display controller 345 may output the image data received from the display interface 340 directly to the display client 355.

The display client 355 may be associated with a touch panel that senses interactions between a user and the display (s) 131. As the user interacts with the display (s) 131, one or more sensors in the touch panel may output signals to the display controller 345 that indicate which of the one or more sensors have sensor activity, a duration of the sensor activity, an applied pressure to the one or more sensor, etc. The display controller 345 may use the sensor outputs to determine a manner in which the user has interacted with the display (s) 131. The display (s) 131 may be further associated with/include other devices, such as a camera, a microphone, and/or a speaker, that operate in connection with the display client 355.

Some processing techniques of the device 104 may be performed over three stages (e.g., stage 1: a rendering stage; stage 2: a composition stage; and stage 3: a display/transfer stage) . However, other processing techniques may combine the composition stage and the display/transfer stage into a single stage, such that the processing technique may be executed based on two total stages (e.g., stage 1: the rendering stage; and stage 2: the composition/display/transfer stage) . During the rendering stage, the GPU 310 may process a content buffer based on execution of an application that generates content on a pixel-by-pixel basis. During the composition and display stage (s) , pixel elements may be assembled to form a frame that is transferred to a physical display panel/subsystem (e.g., the displays 131) that displays the frame.

Instructions executed by a CPU (e.g., software instructions) or a display processor may cause the CPU or the display processor to search for and/or generate a composition strategy for composing a frame based on a dynamic priority and runtime statistics associated with one or more composition strategy groups. A frame to be displayed by a physical display device, such as a display panel, may include a plurality of layers. Also, composition of the frame may be based on combining the plurality of layers into the frame (e.g., based on a frame buffer) . After the plurality of layers are combined into the frame, the frame may be provided to the display panel for display thereon. The process of combining each of the plurality of layers into the frame may be referred to as composition, frame composition, a composition procedure, a composition process, or the like.

A frame composition procedure or composition strategy may correspond to a technique for composing different layers of the plurality of layers into a single frame. The plurality of layers may be stored in doubled data rate (DDR) memory. Each layer of the plurality of layers may further correspond to a separate buffer. A composer or hardware composer (HWC) associated with a block or function may determine an input of each layer/buffer and perform the frame composition procedure to generate an output indicative of a composed frame. That is, the input may be the layers and the output may be a frame composition procedure for composing the frame to be displayed on the display panel.

Some aspects of display processing may utilize different types of mask layers, e.g., a shape mask layer. A mask layer is a layer that may represent a portion of a display or display panel. For instance, an area of a mask layer may correspond to an area of a display, but the entire mask layer may depict a portion of the content that is actually displayed at the display or panel. For example, a mask layer may include a top portion and a bottom portion of a display area, but the middle portion of the mask layer may be empty. In some examples, there may be multiple mask layers to represent different portions of a display area. Also, for certain portions of a display area, the content of different mask layers may overlap with one another. Accordingly, a mask layer may represent a portion of a display area that may or may not overlap with other mask layers.

FIG. 4 is a diagram 400 illustrating an example mask layer for display processing. More specifically, diagram 400 depicts one type of mask layer that may represent portions of a display panel. As shown in FIG. 4, diagram 400 includes mask layer 402 including top regions 410 and bottom regions 420. Top regions 410 include region 411, region 412, region 413, and region 414, and bottom regions 420 include region 421, region 422, region 423, and region 424. As depicted in FIG. 4, mask layer 402 may represent the different regions that are displayed on a display panel.

Some types of displays may use a certain type of mask layer (e.g., a shape mask layer) to reshape a display frame. For instance, a mask layer may reshape the display frame to provide more optimized visual shapes at the display panel (e.g., improved round corners, improved circular shape, improved rectangular shape, etc. ) . These types of mask layers (e.g., shape mask layers) may be processed by software (e.g., graphics processing unit (GPU) software or central processing unit (CPU) software) or by hardware (e.g., display processing unit (DPU) hardware) . Also, these mask layers may be processed by other specific types of hardware logic modules (e.g., modules in a display driver integrated circuit (DDIC) or bridge chips) . In some aspects, these types of mask layers (e.g., shape mask layers) may be based on certain unit, such as a pixel. That is, the shape generation basis unit of the shape mask layers may be a single pixel.

Some aspects of display processing may utilize frame buffers to cache or store a composition output of a GPU. For instance, display layers may be cached or stored in a frame buffer after composition at a GPU. In some aspects, a composition hardware (HW) or software (SW) stack may use a frame buffer target to cache a composition output (e.g., a GPU composition output or a CPU composition output) . The cached composition output may then be sent to another processor (e.g., a DPU) as an input layer. The frame buffer may have a number of different color formats, such as a red (R) green (G) blue (B) alpha (A) (RGBA) format (e.g., RGBA8888 format) . Also, the frame buffer may be a certain size, (e.g., a 32-bit triple buffer) . For example, at the beginning of a display/graphics subsystem design, a frame buffer may be created as an RGBA8888 format and a 32-bit triple buffer. In some instances, if the frame layers do not use a certain composition (e.g., a GPU or client composition) , the frame buffers may be ignored. Also, the layers (e.g., frame layers or display layers associated with display processing) may be directly fetched and composed. For instance, a DPU or hardware composer may directly fetch the layers and then compose the layers.

FIG. 5 is a diagram 500 illustrating an example of a layer composition scheme for display processing. More specifically, diagram 500 depicts a layer composition of display layers where certain layers (e.g., layers of a certain composition) are cached in a frame buffer, and some layers are directly fetched and composed by a DPU. As shown in FIG. 5, diagram 500 includes layer 510, layer 511, layer 512, layer 513, frame buffer 530 (e.g., an RGBA8888 format frame buffer) , DPU 540, and display 550. FIG. 5 depicts that layers composed at a GPU (i.e., layers associated with GPU composition) may be cached or stored in a frame buffer. For example, layer 510, layer 511, and layer 512 may be composed at a GPU and then cached/stored at frame buffer 530. Alternatively, layers that are not composed at a GPU (i.e., layers associated with non-GPU composition) may be directly fetched and composed at a DPU. For instance, layer 513 may be directly fetched and composed at DPU 540. That is, layer 510, layer 511, and layer 512 may be a certain type of composition (e.g., GPU composition) , while layer 513 may be another type of composition (non-GPU composition) . After being cached/stored in frame buffer 530, the layer 510, layer 511, and layer 512 may be sent to DPU 540. Further, after processing at DPU 540, the layers 510-513 may be sent to display 550.

Some types of display processing devices (e.g., mobile devices, computers, TVs, or other consumer devices) may utilize complex multiple content layouts in a single display processing layer or multiple display processing layers. That is, for graphics or display stacks in operating systems of the devices, there may be a single display processing layer (i.e., display layer or layer that is associated with display processing) or multiple display processing layers. For instance, there may be at least one display layer that may be associated with a screen or frame for a display processing device, such that the display panel at the device may be divided amongst the display layers. Additionally, for content or end users, there may be multiple content entities in the display processing layer. This may be due to operating system limitations and/or application rendering/resource management limitations. Further, some types of applications may choose to render in using a single display processing layer. Color processing capability on a per-region basis (i.e., for each region of interest (ROI) in a layer) may be utilized with certain types of display processing unit (DPU) architecture.

Different types of DPU image processing (e.g., DPU per-layer flexible image processing) may be utilized by current mobile consumer electronics devices. Based on the content of different layers, providing accurate per-layer image processing may be important to the perception of an end user. There may be a number of different types of per-layer image processing, such as video high dynamic range (HDR) layer tone mapping and processing and/or video standard dynamic range (SDR) layer visual contrast boosting. Types of per-layer image processing may also include proper tone mapping for photo image layers, game layer color processing and flexible visual control options provided to end users, flexible visual control options for video layers provided to end users, and flexible visual control options for texts/user interface (UI) layers provided to end users.

Some aspects of display processing may utilize a number of different frame enhancement procedures, such as detail enhancement procedures. Detail enhancement (DE) procedures or detail sharpening procedures may be used to increase the quality of images or frames, such as by enhancing the details of the frame. For instance, detail enhancement procedures may increase the high frequency gain and/or high frequency details of images or frames. In display devices (e.g., mobile devices or user equipments (UEs) ) , this function may be used in many different scenarios with adaptive detail enhancement strength. Moreover, detail enhancement procedures may be used as a particular manner in which to optimize the visual quality of the image or frame. Other types of frame enhancement procedures are frame update procedures or partial frame update procedures, which may be used for saving power at display devices. For instance, as different portions of an image or frame change, there may be a need to refresh or update the changing areas of the frame (i.e., pixel-changing areas) , while maintaining other frame areas constant. Accordingly, non-updating portions of a frame may not need to be updated, while the updating portion may be updated. Further, as the display panel size and resolution of display devices (e.g., mobile devices or UEs) continue to increase, the contents of certain portions of images or frames may increasingly change.

FIG. 6 includes diagram 600 illustrating an example of a frame enhancement procedure and diagram 650 illustrating an example of a frame update procedure. More specifically, diagram 600 illustrates a frame detail enhancement process 620 and diagram 650 illustrates a partial frame update process 660. As shown in FIG. 6, diagram 600 includes frame 610, frame content 612, frame detail enhancement process 620, frame 630, and enhanced frame content 632. That is, frame 610 including frame content 612 may experience frame detail enhancement process 620, which enhances the details of the frame 610 to result in frame 630 including enhanced frame content 632. As further depicted in FIG. 6, diagram 650 includes partial frame update process 660, frame 670, region 672, and frame content 674. As show in FIG. 6, frame 670 may experience partial frame update process 660 on the region 672. That is, a portion of frame 670 (i.e., region 672) may be updated via partial frame update process 660. Indeed, partial frame update process 660 may allow the non-updating portions of frame 670 to not be updated, while the updating portions (i.e., region 672) may be updated.

In some aspects, detail enhancement procedures and partial frame update procedures may be utilized concurrently. For instance, detail enhancement procedures may be utilized with local region processing or convolution-based processing. In these instances, each filtered pixel value may be determined from its neighbor region pixels (e.g., a region of 4x6 pixels, 6x12 pixels, or 8x8 pixels) . Also, partial frame update procedures may be performed on a layer basis. That is, pixels of a same layer in the frame may be updated at the same time. For non-refreshing layer boundary region pixels, their current pixel value may be calculated using a previous frame neighbor layer pixel value convolution. If a neighbor layer pixel has already changed (e.g., changed from a detail enhancement algorithm) , those particular pixels may be refreshed as well. However, a partial frame update procedure may solely update or refresh dirty layer regions. By doing so, the processed neighbor pixels corresponding to the detail enhancement procedure may be ignored.

In some instances, detail enhancement procedures and partial frame update procedures may conflict with each other. Indeed, detail enhancement procedures and partial frame update procedures may cause side effects if they are concurrently run on a display device. For instance, when a partial frame update procedure and a detail enhancement procedure are concurrently running, the partially updated region may experience visual displays issues. For example, when a partial frame update procedure and a detail enhancement procedure are concurrently running, the partially updated region may experience edge flickering (i.e., the edges of the region appear to flicker) . These issues may also be associated with frame convolution processing concurrently conflicting with layer basis partial frame update.

FIG. 7 includes diagram 700 illustrating an example of a frame enhancement procedure and a frame update procedure. More specifically, diagram 700 illustrates a frame detail enhancement process 720 and a partial frame update process 760. As shown in FIG. 7, diagram 700 includes frame 710, frame content 712, frame detail enhancement process 720, frame 730, enhanced frame content 732, partial frame update process 760, region 772, and edge flickering 780. FIG. 7 depicts that frame detail enhancement process 720 and partial frame update process 760 are performed simultaneously. For instance, frame detail enhancement process 720 is performed on frame 710 including frame content 712 to produce frame 730 including enhanced frame content 732. At the same time, partial frame update process 760 is performed on region 772 in frame 730. However, due to the simultaneously performance of frame detail enhancement process 720 and partial frame update process 760, region 772 in frame 730 experiences edge flickering 780 (i.e., the edges of the region 772 appear to flicker) .

As indicated herein, when a partial frame update procedure and a detail enhancement procedure are concurrently running, the partially updated region may experience visual displays issues around the region (e.g., edge flickering) . In some aspects, in order to overcome such visual issues, when a partial frame update is used, a detail enhancement procedure may be stopped or closed. However, by doing so, just one of these procedures may be run at a time. Based on the above, it may be beneficial to simultaneously perform a partial frame update procedure and a detail enhancement procedure. For instance, it may be beneficial to concurrently run a partial frame update procedure and a detail enhancement procedure for a display frame without experiencing any visual issues.

Aspects of the present disclosure may simultaneously perform certain types of frame enhancement procedures. In some instances, aspects of the present disclosure may simultaneously perform partial frame update procedures and detail enhancement procedures. For instance, aspects presented herein may concurrently run a partial frame update procedure and a detail enhancement procedure for a display frame without experiencing any visual issues. By doing so, aspects presented herein may solve detail enhancement and partial frame update concurrency issues. Accordingly, aspects presented herein may reduce the amount of visual issues experienced during frame enhancement procedures. That is, aspects presented herein may increase the visual quality and/or user experience of a display device. In addition, aspects of the present disclosure may allow for frame convolution processing that concurrently conflicts with layer-basis partial frame updates. In some instances, aspects of the present disclosure may switch to an individual layer regional detail enhancement procedure. After doing so, aspects presented herein may start a partial frame update procedure. Further, aspects of the present disclosure may apply detail enhancement procedures to a GPU composition cache frame buffer target (FBT) .

In some instances, aspects of the present disclosure may utilize certain types of detailed enhancement procedures for frames in display processing. For instance, if a current frame global detail enhancement is in use, and when a partial frame update is triggered, aspects presented herein may switch from a global frame detail enhancement (DE) to an individual layer detail enhancement in certain frames (e.g., in frame N) . In some aspects, a current frame (e.g., frame N) may utilize full frame processing (i.e., the frame may utilize a full frame refresh) before switching to per layer individual detail enhancement (DE) processing. Also, a partial frame update of corresponding layers may correspond to subsequent frames (e.g., frame N+1) . Further, if GPU composition of layers is involved in the partial update frame, the detail enhancement procedure may be applied to a GPU composition cache (e.g., a GPU composition cache frame buffer target (FBT) ) . Once the partial frame update has stopped, aspects presented herein (e.g., a CPU or display driver) may switch back to global frame DE processing from the per layer individual DE processing.

In some aspects, after determining a need for a partial update to a frame, a CPU or display driver may switch from a global frame image processing (e.g., a detail enhancement procedure) to a per-layer image processing (e.g., a per-layer detail enhancement procedure) . That is, a DPU may include the image processing capability to perform a per-layer detail enhancement procedure for each layer that can utilize an independent partial update. Once the CPU or display driver determines the partial frame update, then the global frame detail enhancement may transition to regional per-layer detail enhancement. The user of the display device may notice the reduction in visual issues, which may be associated with a content change or an animation change. As the CPU or display driver may switch back to regional layer detail enhancement, then in the subsequent or upcoming frames, the partial frame update may run as it normally functions.

In some instances, if a GPU composition is involved, this may mean that some layers are already composed by the GPU. In these cases, aspects presented herein may process the GPU composition, output the frame buffer target, and then process this as an individual layer detail enhancement. For GPU hardware, the incoming content layer and the GPU computation output frame buffer target layer may be the same. So each pipe in the DPU hardware may process the layer detail enhancement. Accordingly, aspects presented herein may detect a need to trigger a partial frame update, and then switch to regional convolution processing. After this, the partial frame update may begin, then once the partial frame update is finished, the session may be finished and the CPU may switch back to global frame processing. So once the partial frame update is triggered, CPUs and display drivers may have the logic to determine if a partial frame update is needed, and then the switch to per-layer image processing may be triggered.

In some aspects, once a partial frame update is triggered, a previous frame (e.g., frame N-1) may be processed using full frame processing, and a current frame (e.g., frame N) may be processed with per layer individual detail enhancement. Then for a subsequent frame (e.g., frame N+1) , there may be a partial frame update and if there are some GPU composition, the frame buffer target (FBT) may correspond to an independent enhancement target. Once it is determined that there is no use for a partial frame update, the CPU or display driver may switch back to global frame display processing or any frame convolution processing. Further, aspects presented herein may utilize artificial intelligence (AI) , a neural network (NN) or convolutional neural network (CNN) , and/or any other potential frame image processing algorithm. Based on these frame image processing algorithms, aspects presented herein may trigger a switch from the global frame processing to an individual per-layer processing. Aspects presented herein may reduce the amount of visual artifacts experienced, such as reducing the amount of edge flickering. Moreover, aspects presented herein may utilize a straightforward image processing flow.

Additionally, aspects presented herein may utilize a generic frame convolution processing. For instance, when a current frame is utilizing global frame convolution processing, once a partial frame update is triggered, aspects presented herein may switch from the global frame convolution processing to an individual layer convolution processing in the current frame (e.g., in frame N) . That is, a current frame N may be utilizing a full frame refresh prior to switching to a per-layer individual convolution processing. Also, a partial frame update of corresponding layers may be utilized for each subsequent frame (e.g., frame N+1) . Further, if a GPU composition of layers is involved in the partial update frame, a specific convolution processing may be applied to a GPU composition cache frame buffer target (FBT) . After the partial frame update has stopped, aspects presented herein may switch back to global frame specific convolution processing for subsequent frames.

FIG. 8 is a diagram 800 illustrating an example of a composition scheme for display processing. More specifically, diagram 800 depicts a composition scheme for a switch from a global frame detail enhancement 801 to a regional per-layer detail enhancement 810, as well as different composition stages and corresponding components in DPU hardware 825. As shown in FIG. 8, diagram 800 includes frame 802 with enhanced frame content 804 that corresponds to the global frame detail enhancement 801. Aspects presented herein may detect a partial frame update for a current frame (e.g., frame 812 including enhanced frame content 814 and region 816) , and then switch to a regional per-layer detail enhancement 810. After switching to regional per-layer detail enhancement 810 for the frame 812, there may be multiple composition stages (e.g., composition stage 820, composition stage 821, and composition stage 822) . For instance, region 816 may utilize a per-layer detail enhancement 817 associated with composition stage 820. Enhanced frame content 814 may utilize a per-layer detail enhancement 818 associated with composition stage 821. Also, the GPU composed individual detail enhancement 819 may utilize composition stage 822. These composition stages may correspond to different components in the DPU hardware 825.

As illustrated in FIG. 8, DPU hardware 825 includes bus interface 826, color converter 828, multiple latency buffering components (e.g., latency buffering component 830, latency buffering component 831, latency buffering component 832, and latency buffering component 833) and multiple image processing components (e.g., image processing component 840, image processing component 841, image processing component 842, and image processing component 843) . DPU hardware 825 also includes crossbar 850, multiple layer mixers (e.g., layer mixer 860, layer mixer 861, layer mixer 862, and layer mixer 863) , multiple frame processing components (e.g., frame processing component 870 and frame processing component 871) , and multiple physical display processing components (e.g., physical display processing component 880, physical display processing component 881, physical display processing component 882, and physical display processing component 883) . In some aspects, the latency buffering components or image processing component may correspond to a processing pipe or a source surface processor pipe (SSPP) in a DPU. As depicted in FIG. 8, composition stage 820 may correspond to latency buffering component 830, composition stage 821 may correspond to image processing component 841, and composition stage 822 may correspond to image processing component 842.

As depicted in FIG. 8, the frame 802 and the frame 812 may include multiple layers that are obtained from a GPU, an application, or a game. For instance, a CPU may receive at least one signal from an application associated with a current frame (e.g., frame 812) , where a partial frame update condition is detected based on the at least one signal from the application. Prior to receiving the signal, the CPU may configure a DPU (e.g., DPU hardware 825) to process each of the set of layers of at least one previous frame (e.g., frame 802) based on the full frame image processing. For example, configuring the DPU (e.g., DPU hardware 825) to process each of the set of layers of the at least one previous frame (e.g., frame 802) may include: transmitting, to the DPU, an indication to process each of the set of layers of the at least one previous frame (e.g., frame 802) based on full frame image processing. The CPU may also perform a layer parameter run-time analysis for each of the set of layers of the current frame (e.g., frame 812) , where the partial frame update condition is detected based on the layer parameter run-time analysis.

Next, the CPU may detect at least one condition associated with a partial update of a current frame (e.g., frame 812) including a set of layers, where each of the set of layers includes a plurality of pixels. The CPU may switch from full frame image processing to per-layer image processing for the current frame (e.g., frame 812) based on the at least one condition. The CPU may also configure the DPU (e.g., DPU hardware 825) to initiate the partial update of the current frame (e.g., frame 812) . The CPU may also configure the DPU (e.g., DPU hardware 825) to process each of the set of layers of the current frame (e.g., frame 812) based on the per-layer image processing. For example, configuring the DPU (e.g., DPU hardware 825) to initiate the partial update and to process each of the set of layers may include: transmitting, to the DPU (e.g., DPU hardware 825) , an indication to initiate the partial update of the current frame (e.g., frame 812) and to process each of the set of layers of the current frame (e.g., frame 812) based on the per-layer image processing. Additionally, the CPU may detect at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, where the at least one subsequent frame is subsequent to the current frame (e.g., frame 812) . After this, the CPU may switch from the per-layer image processing to the full frame image processing for the at least one subsequent frame; and configure the DPU (e.g., DPU hardware 825) to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing.

FIG. 9 is a diagram 900 illustrating an example of a flowchart for display processing associated with partial frame updates. As shown in FIG. 9, at 910, aspects presented herein (e.g., a CPU or DPU driver) may detect or trigger a partial frame update for a current frame (e.g., frame 812) . At 920, aspects presented herein (e.g., a CPU or DPU driver) may switch to a regional convolution processing for a current frame (e.g., frame N or frame 812) . Also, at 930, aspects presented herein (e.g., a CPU or DPU driver) may configure a partial frame update of corresponding layers in a subsequent frame (e.g., frame N+1) . At 940, aspects presented herein may apply specific convolution processing to a GPU composition cache if GPU composition layers are involved in the partial frame update. At 950, aspects presented herein may switch to global frame convolution processing once the partial frame update is over.

Aspects of the present disclosure may include a number of benefits or advantages. For instance, aspects presented herein may simultaneously perform certain types of frame enhancement procedures. In some instances, aspects of the present disclosure may simultaneously perform partial frame update procedures and detail enhancement procedures. Aspects presented herein may concurrently run a partial frame update procedure and a detail enhancement procedure for a display frame without experiencing any visual issues. Therefore, aspects presented herein may solve detail enhancement and partial frame update concurrency issues. As such, aspects presented herein may reduce the amount of visual issues experienced during frame enhancement procedures. That is, aspects presented herein may increase the visual quality and/or user experience of a display device. Also, aspects of the present disclosure may allow for frame convolution processing that concurrently conflicts with layer-basis partial frame updates. In some instances, aspects of the present disclosure may switch to an individual layer regional detail enhancement procedure. After doing so, aspects presented herein may start a partial frame update procedure. For example, aspects presented herein may utilize a partial frame update for display devices, such as UEs (e.g., smart phones) or mobile devices. Further, aspects of the present disclosure may apply detail enhancement procedures to a GPU composition cache frame buffer target (FBT) .

FIG. 10 is a communication flow diagram 1000 of display processing in accordance with one or more techniques of this disclosure. As shown in FIG. 10, diagram 1000 includes example communications between CPU 1002 (e.g., a DPU driver, other central processor, or display processor) , application 1004, and DPU 1006, in accordance with one or more techniques of this disclosure.

At 1010, CPU 1002 may configure a DPU (e.g., DPU 1006) to process each of a set of layers of at least one previous frame based on full frame image processing, where at least one current frame is subsequent to the at least one previous frame. In some aspects, configuring the DPU to process each of the set of layers of the at least one previous frame may include: transmitting, to the DPU, an indication to process each of the set of layers of the at least one previous frame based on the full frame image processing. That is the CPU may transmit, to the DPU, an indication to process each of the set of layers of the at least one previous frame based on the full frame image processing.

At 1020, CPU 1002 may perform a layer parameter run-time analysis for each of a set of layers of the at least one current frame, where at least one condition associated with a partial update of the at least one current frame is detected based on the layer parameter run-time analysis. The layer parameter run-time analysis may be associated with at least one of: one or more layer coordinates, a layer content, a layer update flag, or metadata associated with the plurality of pixels for each of the set of layers.

At 1030, CPU 1002 may receive at least one signal (e.g., signal 1032) from an application (e.g., application 1004) associated with the at least one current frame, where the at least one condition associated with the partial update of the at least one current frame is detected based on the at least one signal from the application.

At 1040, CPU 1002 may detect at least one condition associated with a partial update of at least one current frame including a set of layers, where each of the set of layers includes a plurality of pixels. In some aspects, detecting the at least one condition associated with the partial update of the at least one current frame may include: detecting an adjustment in one or more layer coordinates or a layer content for at least one layer of the set of layers in the at least one current frame. That is, the CPU may detect an adjustment in one or more layer coordinates or a layer content for at least one layer of the set of layers in the at least one current frame. The adjustment in the layer content may be associated with a layer update flag. The at least one condition may be one or more of: at least one frame parameter of the at least one current frame, at least one layer parameter of at least one layer in the set of layers of the at least one current frame, or an adjustment in the at least one layer parameter.

At 1050, CPU 1002 may switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition. The full frame image processing may correspond to an application of a same processing algorithm to an entire portion of the at least one current frame. The per-layer image processing may correspond to an application of a first processing algorithm to at least one first layer in the set of layers of the at least one current frame and a second processing algorithm to at least one second layer in the set of layers of the at least one current frame. In some instances, the first processing algorithm may be different from the second processing algorithm, and the at least one first layer may be different from the at least one second layer. In some instances, switching from the full frame image processing to the per-layer image processing may include: initiating the per-layer image processing for the at least one current frame. That is, the CPU may initiate the per-layer image processing for the at least one current frame.

At 1060, CPU 1002 may configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing. In some instances, configuring the DPU to initiate the partial update and to process each of the set of layers may include: transmitting, to the DPU, an indication to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing. That is, the CPU may transmit, to the DPU, an indication (e.g., indication 1062) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.

At 1070, CPU 1002 may detect at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, where the at least one subsequent frame is subsequent to the at least one current frame.

At 1080, CPU 1002 may switch from the per-layer image processing to the full frame image processing for the at least one subsequent frame.

Additionally, at 1080, CPU 1002 may configure the DPU to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing. In some instances, configuring the DPU to initiate the full frame update of the at least one subsequent frame may include: transmitting, to the DPU, an indication to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing. That is, the CPU may transmit an indication (e.g., indication 1082) to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing.

FIG. 11 is a flowchart 1100 of an example method of display processing in accordance with one or more techniques of this disclosure. The method may be performed by a CPU (or other central processor) , a DPU driver, a DPU (or other display processor) , a GPU (or other graphics processor) , a DDIC, an apparatus for display processing, a wireless communication device, and/or any apparatus that may perform display processing as used in connection with the examples of FIGs. 1-10.

At 1108, the CPU may detect at least one condition associated with a partial update of at least one current frame including a set of layers, where each of the set of layers includes a plurality of pixels, as described in connection with the examples in FIGs. 1-10. For example, as described in 1040 of FIG. 10, CPU 1002 may detect at least one condition associated with a partial update of at least one current frame including a set of layers, where each of the set of layers includes a plurality of pixels. Further, step 1108 may be performed by display processor 127 in FIG. 1. In some aspects, detecting the at least one condition associated with the partial update of the at least one current frame may include: detecting an adjustment in one or more layer coordinates or a layer content for at least one layer of the set of layers in the at least one current frame. That is, the CPU may detect an adjustment in one or more layer coordinates or a layer content for at least one layer of the set of layers in the at least one current frame. The adjustment in the layer content may be associated with a layer update flag. The at least one condition may be one or more of: at least one frame parameter of the at least one current frame, at least one layer parameter of at least one layer in the set of layers of the at least one current frame, or an adjustment in the at least one layer parameter.

At 1110, the CPU may switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition, as described in connection with the examples in FIGs. 1-10. For example, as described in 1050 of FIG. 10, CPU 1002 may switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition. Further, step 1110 may be performed by display processor 127 in FIG. 1. The full frame image processing may correspond to an application of a same processing algorithm to an entire portion of the at least one current frame. The per-layer image processing may correspond to an application of a first processing algorithm to at least one first layer in the set of layers of the at least one current frame and a second processing algorithm to at least one second layer in the set of layers of the at least one current frame. In some instances, the first processing algorithm may be different from the second processing algorithm, and the at least one first layer may be different from the at least one second layer. In some instances, switching from the full frame image processing to the per-layer image processing may include: initiating the per-layer image processing for the at least one current frame. That is, the CPU may initiate the per-layer image processing for the at least one current frame.

At 1112, the CPU may configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing, as described in connection with the examples in FIGs. 1-10. For example, as described in 1060 of FIG. 10, CPU 1002 may configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing. Further, step 1112 may be performed by display processor 127 in FIG. 1. In some instances, configuring the DPU to initiate the partial update and to process each of the set of layers may include: transmitting, to the DPU, an indication to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing. That is, the CPU may transmit, to the DPU, an indication to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.

FIG. 12 is a flowchart 1200 of an example method of display processing in accordance with one or more techniques of this disclosure. The method may be performed by a CPU (or other central processor) , a DPU driver, a DPU (or other display processor) , a GPU (or other graphics processor) , a DDIC, an apparatus for display processing, a wireless communication device, and/or any apparatus that may perform display processing as used in connection with the examples of FIGs. 1-10.

At 1202, the CPU may configure a DPU to process each of a set of layers of at least one previous frame based on full frame image processing, where at least one current frame is subsequent to the at least one previous frame, as described in connection with the examples in FIGs. 1-10. For example, as described in 1010 of FIG. 10, CPU 1002 may configure a DPU to process each of a set of layers of at least one previous frame based on full frame image processing, where at least one current frame is subsequent to the at least one previous frame. Further, step 1202 may be performed by display processor 127 in FIG. 1. In some aspects, configuring the DPU to process each of the set of layers of the at least one previous frame may include: transmitting, to the DPU, an indication to process each of the set of layers of the at least one previous frame based on the full frame image processing. That is the CPU may transmit, to the DPU, an indication to process each of the set of layers of the at least one previous frame based on the full frame image processing.

At 1204, the CPU may perform a layer parameter run-time analysis for each of a set of layers of the at least one current frame, where at least one condition associated with a partial update of the at least one current frame is detected based on the layer parameter run-time analysis, as described in connection with the examples in FIGs. 1-10. For example, as described in 1020 of FIG. 10, CPU 1002 may perform a layer parameter run-time analysis for each of a set of layers of the at least one current frame, where at least one condition associated with a partial update of the at least one current frame is detected based on the layer parameter run-time analysis. Further, step 1204 may be performed by display processor 127 in FIG. 1. The layer parameter run-time analysis may be associated with at least one of: one or more layer coordinates, a layer content, a layer update flag, or metadata associated with the plurality of pixels for each of the set of layers.

At 1206, the CPU may receive at least one signal from an application associated with the at least one current frame, where the at least one condition associated with the partial update of the at least one current frame is detected based on the at least one signal from the application, as described in connection with the examples in FIGs. 1-10. For example, as described in 1030 of FIG. 10, CPU 1002 may receive at least one signal from an application associated with the at least one current frame, where the at least one condition associated with the partial update of the at least one current frame is detected based on the at least one signal from the application. Further, step 1206 may be performed by display processor 127 in FIG. 1.

At 1208, the CPU may detect at least one condition associated with a partial update of at least one current frame including a set of layers, where each of the set of layers includes a plurality of pixels, as described in connection with the examples in FIGs. 1-10. For example, as described in 1040 of FIG. 10, CPU 1002 may detect at least one condition associated with a partial update of at least one current frame including a set of layers, where each of the set of layers includes a plurality of pixels. Further, step 1208 may be performed by display processor 127 in FIG. 1. In some aspects, detecting the at least one condition associated with the partial update of the at least one current frame may include: detecting an adjustment in one or more layer coordinates or a layer content for at least one layer of the set of layers in the at least one current frame. That is, the CPU may detect an adjustment in one or more layer coordinates or a layer content for at least one layer of the set of layers in the at least one current frame. The adjustment in the layer content may be associated with a layer update flag. The at least one condition may be one or more of: at least one frame parameter of the at least one current frame, at least one layer parameter of at least one layer in the set of layers of the at least one current frame, or an adjustment in the at least one layer parameter.

At 1210, the CPU may switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition, as described in connection with the examples in FIGs. 1-10. For example, as described in 1050 of FIG. 10, CPU 1002 may switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition. Further, step 1210 may be performed by display processor 127 in FIG. 1. The full frame image processing may correspond to an application of a same processing algorithm to an entire portion of the at least one current frame. The per-layer image processing may correspond to an application of a first processing algorithm to at least one first layer in the set of layers of the at least one current frame and a second processing algorithm to at least one second layer in the set of layers of the at least one current frame. In some instances, the first processing algorithm may be different from the second processing algorithm, and the at least one first layer may be different from the at least one second layer. In some instances, switching from the full frame image processing to the per-layer image processing may include: initiating the per-layer image processing for the at least one current frame. That is, the CPU may initiate the per-layer image processing for the at least one current frame.

At 1212, the CPU may configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing, as described in connection with the examples in FIGs. 1-10. For example, as described in 1060 of FIG. 10, CPU 1002 may configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing. Further, step 1212 may be performed by display processor 127 in FIG. 1. In some instances, configuring the DPU to initiate the partial update and to process each of the set of layers may include: transmitting, to the DPU, an indication to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing. That is, the CPU may transmit, to the DPU, an indication to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.

At 1214, the CPU may detect at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, where the at least one subsequent frame is subsequent to the at least one current frame, as described in connection with the examples in FIGs. 1-10. For example, as described in 1070 of FIG. 10, CPU 1002 may detect at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, where the at least one subsequent frame is subsequent to the at least one current frame. Further, step 1214 may be performed by display processor 127 in FIG. 1.

At 1216, the CPU may switch from the per-layer image processing to the full frame image processing for the at least one subsequent frame, as described in connection with the examples in FIGs. 1-10. For example, as described in 1080 of FIG. 10, CPU 1002 may switch from the per-layer image processing to the full frame image processing for the at least one subsequent frame. Further, step 1216 may be performed by display processor 127 in FIG. 1.

Additionally, at 1216, the CPU may configure the DPU to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing, as described in connection with the examples in FIGs. 1-10. For example, as described in 1080 of FIG. 10, CPU 1002 may configure the DPU to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing. Further, step 1216 may be performed by display processor 127 in FIG. 1. In some instances, configuring the DPU to initiate the full frame update of the at least one subsequent frame may include: transmitting, to the DPU, an indication to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing. That is, the CPU may transmit an indication to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing.

In configurations, a method or an apparatus for display processing is provided. The apparatus may be a CPU (or other central processor) , a DPU (or other display processor) , a GPU (or other graphics processor) , a DPU driver, a DDIC, an apparatus for display processing, and/or some other processor that may perform display processing. In aspects, the apparatus may be the display processor 127 within the device 104, or may be some other hardware within the device 104 or another device. The apparatus, e.g., display processor 127, may include means for detecting at least one condition associated with a partial update of at least one current frame including a set of layers, where each of the set of layers includes a plurality of pixels. The apparatus, e.g., display processor 127, may also include means for switching from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition. The apparatus, e.g., display processor 127, may also include means for configuring a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing. The apparatus, e.g., display processor 127, may also include means for performing a layer parameter run-time analysis for each of the set of layers of the at least one current frame, where the at least one condition is detected based on the layer parameter run-time analysis. The apparatus, e.g., display processor 127, may also include means for receiving at least one signal from an application associated with the at least one current frame, where the at least one condition is detected based on the at least one signal from the application. The apparatus, e.g., display processor 127, may also include means for configuring the DPU to process each of the set of layers of at least one previous frame based on the full frame image processing, where the at least one current frame is subsequent to the at least one previous frame. The apparatus, e.g., display processor 127, may also include means for detecting at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, where the at least one subsequent frame is subsequent to the at least one current frame. The apparatus, e.g., display processor 127, may also include means for switching from the per-layer image processing to the full frame image processing for the at least one subsequent frame. The apparatus, e.g., display processor 127, may also include means for configuring the DPU to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing.

The subject matter described herein may be implemented to realize one or more benefits or advantages. For instance, the described display processing techniques may be used by a CPU, a central processor, a DPU driver, a DPU, a display processor, a GPU, or some other processor that may perform display processing to implement the partial frame update techniques described herein. This may also be accomplished at a low cost compared to other display processing techniques. Moreover, the display processing techniques herein may improve or speed up data processing or execution. Further, the display processing techniques herein may improve resource or data utilization and/or resource efficiency. Additionally, aspects of the present disclosure may utilize partial frame update techniques in order to improve memory bandwidth efficiency and/or increase processing speed at a CPU, a DPU or a GPU.

It is understood that the specific order or hierarchy of blocks in the processes /flowcharts disclosed is an illustration of example approaches. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes /flowcharts may be rearranged. Further, some blocks may be combined or omitted. The accompanying method claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more. ” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration. ” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

Unless specifically stated otherwise, the term “some” refers to one or more and the term “or” may be interpreted as “and/or” where context does not dictate otherwise. Combinations such as “at least one of A, B, or C, ” “one or more of A, B, or C, ” “at least one of A, B, and C, ” “one or more of A, B, and C, ” and “A, B, C, or any combination thereof” include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C, ” “one or more of A, B, or C, ” “at least one of A, B, and C, ” “one or more of A, B, and C, ” and “A, B, C, or any combination thereof” may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. The words “module, ” “mechanism, ” “element, ” “device, ” and the like may not be a substitute for the word “means. ” As such, no claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for. ”

In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

In accordance with this disclosure, the term “or” may be interpreted as “and/or” where context does not dictate otherwise. Additionally, while phrases such as “one or more” or “at least one” or the like may have been used for some features disclosed herein but not others, the features for which such language was not used may be interpreted to have such a meaning implied where context does not dictate otherwise.

In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media, which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that may be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices. Disk and disc, as used herein, includes compact disc (CD) , laser disc, optical disc, digital versatile disc (DVD) , floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

The code may be executed by one or more processors, such as one or more digital signal processors (DSPs) , general purpose microprocessors, application specific integrated circuits (ASICs) , arithmetic logic units (ALUs) , field programmable logic arrays (FPGAs) , or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor, ” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques could be fully implemented in one or more circuits or logic elements.

The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set. Various components, modules or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of inter-operative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware. Accordingly, the term “processor, ” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques may be fully implemented in one or more circuits or logic elements.

The following aspects are illustrative only and may be combined with other aspects or teachings described herein, without limitation.

Aspect 1 is an apparatus for display processing, including a memory and at least one processor coupled to the memory and, based at least in part on information stored in the memory, the at least one processor is configured to: detect at least one condition associated with a partial update of at least one current frame including a set of layers, where each of the set of layers includes a plurality of pixels; switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition; and configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.

Aspect 2 is the apparatus of aspect 1, where the at least one processor is further configured to: perform a layer parameter run-time analysis for each of the set of layers of the at least one current frame, where the at least one processor is configured to detect the at least one condition based on the layer parameter run-time analysis.

Aspect 3 is the apparatus of aspect 2, where the layer parameter run-time analysis is associated with at least one of: one or more layer coordinates, a layer content, a layer update flag, or metadata associated with the plurality of pixels for each of the set of layers.

Aspect 4 is the apparatus of any of aspects 1 to 3, where to detect the at least one condition associated with the partial update of the at least one current frame, the at least one processor is configured to: detect an adjustment in one or more layer coordinates or a layer content for at least one layer of the set of layers in the at least one current frame.

Aspect 5 is the apparatus of aspect 4, where the adjustment in the layer content is associated with a layer update flag.

Aspect 6 is the apparatus of any of aspects 1 to 5, where the at least one processor is further configured to: receive at least one signal from an application associated with the at least one current frame, where the at least one processor is configured to detect the at least one condition based on the at least one signal from the application.

Aspect 7 is the apparatus of any of aspects 1 to 6, where the full frame image processing corresponds to an application of a same processing algorithm to an entire portion of the at least one current frame, and where the per-layer image processing corresponds to an application of a first processing algorithm to at least one first layer in the set of layers of the at least one current frame and a second processing algorithm to at least one second layer in the set of layers of the at least one current frame.

Aspect 8 is the apparatus of aspect 7, where the first processing algorithm is different from the second processing algorithm, and where the at least one first layer is different from the at least one second layer.

Aspect 9 is the apparatus of any of aspects 1 to 8, where the at least one processor is further configured to: configure the DPU to process each of the set of layers of at least one previous frame based on the full frame image processing, where the at least one current frame is subsequent to the at least one previous frame.

Aspect 10 is the apparatus of aspect 9, where to configure the DPU to process each of the set of layers of the at least one previous frame, the at least one processor is configured to: transmit, to the DPU, an indication to process each of the set of layers of the at least one previous frame based on the full frame image processing.

Aspect 11 is the apparatus of any of aspects 1 to 10, where the at least one processor is further configured to: detect at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, where the at least one subsequent frame is subsequent to the at least one current frame.

Aspect 12 is the apparatus of aspect 11, where the at least one processor is further configured to: switch from the per-layer image processing to the full frame image processing for the at least one subsequent frame; and configure the DPU to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing.

Aspect 13 is the apparatus of any of aspects 1 to 12, where to switch from the full frame image processing to the per-layer image processing, the at least one processor is configured to: initiate the per-layer image processing for the at least one current frame.

Aspect 14 is the apparatus of any of aspects 1 to 13, where the at least one condition is one or more of: at least one frame parameter of the at least one current frame, at least one layer parameter of at least one layer in the set of layers of the at least one current frame, or an adjustment in the at least one layer parameter.

Aspect 15 is the apparatus of any of aspects 1 to 14, where to configure the DPU to initiate the partial update and to process each of the set of layers, the at least one processor is configured to: transmit, to the DPU, an indication to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.

Aspect 16 is the apparatus of any of aspects 1 to 15, where the apparatus is a wireless communication device, further including at least one of an antenna or a transceiver coupled to the at least one processor, where to transmit the indication to initiate the partial update of the at least one current frame, the at least one processor is configured to:transmit, via at least one of the antenna or the transceiver, the indication to initiate the partial update of the at least one current frame.

Aspect 17 is a method of display processing for implementing any of aspects 1 to 16.

Aspect 18 is an apparatus for display processing including means for implementing any of aspects 1 to 16.

Aspect 19 is a computer-readable medium (e.g., a non-transitory computer-readable medium) storing computer executable code, the code when executed by at least one processor causes the at least one processor to implement any of aspects 1 to 16.

Claims

An apparatus for display processing, comprising:

a memory; and

at least one processor coupled to the memory and, based at least in part on information stored in the memory, the at least one processor is configured to:

detect at least one condition associated with a partial update of at least one current frame including a set of layers, wherein each of the set of layers includes a plurality of pixels;

switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition; and

configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.
The apparatus of claim 1, wherein the at least one processor is further configured to:

perform a layer parameter run-time analysis for each of the set of layers of the at least one current frame, wherein the at least one processor is configured to detect the at least one condition based on the layer parameter run-time analysis.
The apparatus of claim 2, wherein the layer parameter run-time analysis is associated with at least one of: one or more layer coordinates, a layer content, a layer update flag, or metadata associated with the plurality of pixels for each of the set of layers.
The apparatus of claim 1, wherein to detect the at least one condition associated with the partial update of the at least one current frame, the at least one processor is configured to:detect an adjustment in one or more layer coordinates or a layer content for at least one layer of the set of layers in the at least one current frame.
The apparatus of claim 4, wherein the adjustment in the layer content is associated with a layer update flag.
The apparatus of claim 1, wherein the at least one processor is further configured to:

receive at least one signal from an application associated with the at least one current frame, wherein the at least one processor is configured to detect the at least one condition based on the at least one signal from the application.
The apparatus of claim 1, wherein the full frame image processing corresponds to an application of a same processing algorithm to an entire portion of the at least one current frame, and wherein the per-layer image processing corresponds to an application of a first processing algorithm to at least one first layer in the set of layers of the at least one current frame and a second processing algorithm to at least one second layer in the set of layers of the at least one current frame.
The apparatus of claim 7, wherein the first processing algorithm is different from the second processing algorithm, and wherein the at least one first layer is different from the at least one second layer.
The apparatus of claim 1, wherein the at least one processor is further configured to:

configure the DPU to process each of the set of layers of at least one previous frame based on the full frame image processing, wherein the at least one current frame is subsequent to the at least one previous frame.
The apparatus of claim 9, wherein to configure the DPU to process each of the set of layers of the at least one previous frame, the at least one processor is configured to: transmit, to the DPU, an indication to process each of the set of layers of the at least one previous frame based on the full frame image processing.
The apparatus of claim 1, wherein the at least one processor is further configured to:

detect at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, wherein the at least one subsequent frame is subsequent to the at least one current frame.
The apparatus of claim 11, wherein the at least one processor is further configured to:

switch from the per-layer image processing to the full frame image processing for the at least one subsequent frame; and

configure the DPU to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing.
The apparatus of claim 1, wherein to switch from the full frame image processing to the per-layer image processing, the at least one processor is configured to: initiate the per-layer image processing for the at least one current frame.
The apparatus of claim 1, wherein the at least one condition is one or more of: at least one frame parameter of the at least one current frame, at least one layer parameter of at least one layer in the set of layers of the at least one current frame, or an adjustment in the at least one layer parameter.
The apparatus of claim 1, wherein to configure the DPU to initiate the partial update and to process each of the set of layers, the at least one processor is configured to: transmit, to the DPU, an indication to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.
The apparatus of claim 15, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein to transmit the indication to initiate the partial update of the at least one current frame, the at least one processor is configured to: transmit, via at least one of the antenna or the transceiver, the indication to initiate the partial update of the at least one current frame.
A method of display processing, comprising:

detecting at least one condition associated with a partial update of at least one current frame including a set of layers, wherein each of the set of layers includes a plurality of pixels;

switching from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition; and

configuring a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.
The method of claim 17, further comprising:

performing a layer parameter run-time analysis for each of the set of layers of the at least one current frame, wherein the at least one condition is detected based on the layer parameter run-time analysis, and wherein the layer parameter run-time analysis is associated with at least one of: one or more layer coordinates, a layer content, a layer update flag, or metadata associated with the plurality of pixels for each of the set of layers.
The method of claim 17, wherein detecting the at least one condition associated with the partial update of the at least one current frame comprises: detecting an adjustment in one or more layer coordinates or a layer content for at least one layer of the set of layers in the at least one current frame, and wherein the adjustment in the layer content is associated with a layer update flag.
The method of claim 17, further comprising:

receiving at least one signal from an application associated with the at least one current frame, wherein the at least one condition is detected based on the at least one signal from the application.
The method of claim 17, wherein the full frame image processing corresponds to an application of a same processing algorithm to an entire portion of the at least one current frame, and wherein the per-layer image processing corresponds to an application of a first processing algorithm to at least one first layer in the set of layers of the at least one current frame and a second processing algorithm to at least one second layer in the set of layers of the at least one current frame, wherein the first processing algorithm is different from the second processing algorithm, and wherein the at least one first layer is different from the at least one second layer.
The method of claim 17, further comprising:

configuring the DPU to process each of the set of layers of at least one previous frame based on the full frame image processing, wherein the at least one current frame is subsequent to the at least one previous frame.
The method of claim 22, wherein configuring the DPU to process each of the set of layers of the at least one previous frame comprises: transmitting, to the DPU, an indication to process each of the set of layers of the at least one previous frame based on the full frame image processing.
The method of claim 17, further comprising:

detecting at least one second condition associated with a full frame update for at least one subsequent frame including the set of layers, wherein the at least one subsequent frame is subsequent to the at least one current frame.
The method of claim 24, further comprising:

switching from the per-layer image processing to the full frame image processing for the at least one subsequent frame; and

configuring the DPU to initiate the full frame update of the at least one subsequent frame and to process each of the set of layers of the at least one subsequent frame based on the full frame image processing.
The method of claim 17, wherein switching from the full frame image processing to the per-layer image processing comprises: initiating the per-layer image processing for the at least one current frame.
The method of claim 17, wherein the at least one condition is one or more of: at least one frame parameter of the at least one current frame, at least one layer parameter of at least one layer in the set of layers of the at least one current frame, or an adjustment in the at least one layer parameter.
The method of claim 17, wherein configuring the DPU to initiate the partial update and to process each of the set of layers comprises: transmitting, to the DPU, an indication to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.
An apparatus for display processing, comprising:

means for detecting at least one condition associated with a partial update of at least one current frame including a set of layers, wherein each of the set of layers includes a plurality of pixels;

means for switching from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition; and

means for configuring a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.
A computer-readable medium storing computer executable code for display processing, the code when executed by a processor causes the processor to:

detect at least one condition associated with a partial update of at least one current frame including a set of layers, wherein each of the set of layers includes a plurality of pixels;

switch from full frame image processing to per-layer image processing for the at least one current frame based on the at least one condition; and

configure a display processing unit (DPU) to initiate the partial update of the at least one current frame and to process each of the set of layers of the at least one current frame based on the per-layer image processing.