WO2023246346A1

WO2023246346A1 - Data transmission apparatus

Info

Publication number: WO2023246346A1
Application number: PCT/CN2023/093000
Authority: WO
Inventors: 严增超; 马会肖; 黄科超; 杨小玲
Original assignee: 华为技术有限公司
Priority date: 2022-06-25
Filing date: 2023-05-09
Publication date: 2023-12-28
Also published as: CN117335922A

Abstract

A data transmission apparatus, which is used for solving the problem in the prior art of it being impossible to realize low delay and also meet the transmission performance during an interleaving process. The data transmission apparatus can be applied to the fields such as short-distance interconnection, cloud application, augmented reality (AR), virtual reality (VR) and artificial intelligence (AI). The data transmission apparatus comprises z physical coding sublayer (PCS) channels and z convolutional interleaving modules, wherein one convolutional interleaving module corresponds to one PCS channel, each convolutional interleaving module comprises x stages of cascaded convolutional interleavers, x is an integer greater than 1, and z is a positive integer. Each PCS channel is used for receiving a first data stream from a PCS layer, wherein one first data stream corresponds to one PCS channel; and each convolutional interleaving module is used for performing interleaving processing on a first data stream from a corresponding PCS channel, so as to obtain a second data stream, wherein the interleaving depth of the second data stream is related to the number of input bits of an inner-code coder. By means of cascaded interleavers, the number of stages of the cascaded interleavers can be flexibly selected.

Description

a data transmission device

Cross-references to related applications

This application claims priority to the Chinese patent application filed with the China Patent Office on June 25, 2022, with application number 202210731905.0 and the application title "A data transmission device", the entire content of which is incorporated into this application by reference.

Technical field

The present application relates to the field of communication technology, and in particular, to a data transmission device.

Background technique

As data traffic continues to grow at a rapid rate, the capacity of equipment is also rapidly increasing, and the requirements for Ethernet transmission rates are also getting higher and higher. The International Standards Organization defines the Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet protocol. The IEEE 802.3 Ethernet protocol defines the interface protocols for 100 Gigabit Ethernet (GE), 200GE, and 400GE. . However, 400GE network port technology can no longer meet the demand, and there is an urgent need for next-generation Ethernet technology with a throughput rate exceeding 400 Gbit per second (Gbps) (such as 800Gbps or 1.6Tbps).

However, as the Ethernet transmission rate increases, the transmission error rate also increases, and forward error correction (FEC) has become a key technology to solve transmission errors. How to design an interleaver with low latency and sufficient transmission performance is an urgent technical problem that needs to be solved.

Contents of the invention

This application provides a data transmission device that can not only meet the transmission performance of the data stream, but also help reduce the delay of the data stream transmission.

In a first aspect, this application provides a data transmission device. The data transmission device includes z physical coding sublayer (PCS) channels and z convolutional interleaving modules. One convolutional interleaving module corresponds to one PCS channel. The convolution interleaving module includes cascaded x-level convolution interleaver, x is an integer greater than 1, and z is a positive integer. The PCS channel is used to receive the first data stream from the PCS layer, and one first data stream corresponds to one PCS channel. The convolutional interleaving module is used to interleave the first data stream from the corresponding PCS channel to obtain a second data stream. The interleaving depth of the second data stream is related to the input bit number of the inner code encoder.

Based on the above data transmission device, by cascading multiple convolutional interleaver, the number of cascaded interleaver stages can be flexibly selected, which can not only meet the transmission performance of the data stream, but also help to reduce the delay of data stream transmission.

In a possible implementation manner, the convolutional interleaving module is specifically configured to interleave the first data stream from the corresponding PCS channel according to the received indication signal. Wherein, the indication signal is used to indicate to bypass at least one stage of the convolutional interleaver in the z convolutional interleaving modules; or, the indication signal is used to indicate to bypass the i-th convolutional interleaving module in the z convolutional interleaving modules. The jth-level convolutional interleaver, i is an integer less than z, j is an integer less than x.

Through the indication signal, it is possible to flexibly control which stage or stages of the convolution interleaver among the z convolution interleaving modules is bypassed, so that there is no need to limit the bit width of the inner code encoder, and the inner code encoder can be flexibly selected. . Alternatively, the number of cascaded convolution interleaver stages of each convolution interleave module can be controlled independently, which can enable different corrections on different PCS channels. The error capability helps further increase the applicable scenarios. For example, hash (Breakout) transmission mode can be supported.

In a possible implementation, the device further includes a management data input/output (MDIO) interface, and the indication signal includes the value of the MDIO control bit; the MDIO interface is used to receive the first information, and the first information includes The value of the control variable of MDIO, which is mapped to the control variable of the x-level convolutional interleaver.

Transmitting the indication signal through the MDIO interface does not occupy the bandwidth of the communication data stream.

In a possible implementation, the device further includes an attachment unit interface (AUI), the indication signal includes a first preset sequence or a second preset sequence; the AUI is used to receive alignment from the corresponding PCS channel Marker (alignment marker, AM) sequence, the AM sequence includes a first preset sequence; or is used to receive a second preset sequence from the corresponding PCS channel.

By carrying the indication signal in the AM sequence, it helps to reduce the overhead between the optical module and the device.

In a possible implementation, the number of input symbols of the sub-channels of the k-th level convolution interleaver is equal to the number of output symbols of the sub-channels of the k-th level convolution interleaver, and the k-th level convolution interleaver is the first convolution interleaver. Any one of the x convolutional interleavers in the product interleaving module, the first convolutional interleaving module is any one of the z convolutional interleaving modules, and k is a positive integer less than or equal to x.

Further, optionally, the input interleaving depth of the first convolutional interleaving module is related to the coding method and symbol distribution method of the PCS layer; the output interleaving depth of the first convolutional interleaving module is w _x ×p _x ; where, w _x is the number of sub-channels input to the x-th level convolution interleaver of the first convolution interleaving module, and p _x is the number of sub-channels included in the x-th level convolution interleaver of the first convolution interleaving module.

In a possible implementation, when k is a positive integer greater than 1 and less than or equal to x, the input interleaving depth of the k-th level convolution interleaver is w _k-1 ×p _k-1 , and the k-th level convolution interleaving _The _output interleaving depth of the interleaver _is _w _k _-1 is the number of input symbols of the sub-channels of the k-1th level convolution interleaver, p _k-1 is the number of sub-channels included in the k-1th level convolutional interleaver; the first level of the first convolutional interleaving module The input interleaving depth of the convolutional interleaver is equal to the input interleaving depth of the first convolutional interleaving module.

In a possible implementation, when k is a positive integer greater than 1 and less than or equal to x, the delay between the k-th stage convolutional interleaver and the first-stage convolutional interleaver satisfies the following formula 1:

Among them, w _k is the number of symbols input to the sub-channel of the k-th level convolution interleaver, p _k is the number of sub-channels included in the k-th level convolution interleaver, and w ₁ is the sub-channel input of the first-level convolution interleaver. The number of symbols, p ₁ is the number of sub-channels included in the first-level convolutional interleaver, and Δ ₁ is the delay between two adjacent sub-channels in the first-level convolutional interleaver.

Through the above formula 1, the delay relationship between other stages of convolutional interleaver except the first stage convolutional interleaver and the first stage convolutional interleaver can be obtained. And it is guaranteed that the interleaving depth increases with the increase of convolutional interleaver cascade.

For example, the delay between the k-th stage convolutional interleaver and the first-stage convolutional interleaver satisfies the following formula 2:

Through the above formula 2, the delays of other stages of convolutional interleaver except the first stage convolutional interleaver can be obtained through simple design.

In a possible implementation, the delay Δ ₁ between two adjacent sub-channels in the first-stage convolutional interleaver is an integer multiple of the interleaving depth input by the first convolutional interleaving module, and satisfies the following formula 3:

Where, L is the number of symbols allocated to the PCS channel corresponding to the first convolutional interleaving module.

Through the above formula 3, the output interleaving depth of the first-stage convolutional interleaver can be increased.

In a possible implementation, the x-level convolution interleaver included in the first convolutional interleaving module has different sub-channel numbers, and the first convolutional interleaving module is any one of z convolutional interleaving modules.

Further, optionally, the number of sub-channels of the first-level convolution interleaver included in the first convolution interleaving module is the same as the x-1 level convolution included in the first convolution interleaving module except the first convolution interleaver. The number of sub-channels of the interleaver is different, and the number of sub-channels of the x-1 stage convolution interleaver included in the first convolution interleaving module except the first convolution interleaver is the same.

For example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules; the first-level convolutional interleaver The delay between two adjacent sub-channels is 24 symbols; and/or the delay of the second-stage convolutional interleaver is 144 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules; the first-level convolutional interleaving module The delay between two adjacent sub-channels in the processor is 24 symbols; and/or the delay of the second-stage convolutional interleaver is 120 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules; the first-level convolutional interleaving module The delay between two adjacent sub-channels in the processor is 26 symbols; and/or the delay of the second-stage convolutional interleaver is 130 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules; the first-level convolutional interleaving module The delay between two adjacent sub-channels in the processor is 26 symbols; and/or the delay of the second-stage convolutional interleaver is 156 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; the delay between two adjacent sub-channels in the level 1 convolutional interleaver is 24 symbols; and/or, the delay in the level 2 convolutional interleaver is 120 symbols; and/or, the level 3 convolutional interleaver The delay of the product interleaver is 216 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; the delay between two adjacent sub-channels in the level 1 convolutional interleaver is 24 symbols; and/or, the delay in the level 2 convolutional interleaver is 144 symbols; and/or, the level 2 convolutional interleaver The delay of the product interleaver is 288 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; the delay between two adjacent sub-channels in the level 1 convolutional interleaver is 26 symbols; and/or, the delay in the level 2 convolutional interleaver is 130 symbols; and/or, the level 3 convolutional interleaver The delay of the product interleaver is 234 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; the delay between two adjacent sub-channels in the level 1 convolutional interleaver is 24 symbols; and/or, the delay in the level 2 convolutional interleaver is 120 symbols; and/or, the level 3 convolutional interleaver The delay of the product interleaver is 240 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; the delay between two adjacent sub-channels in the level 1 convolutional interleaver is 26 symbols; and/or, the delay in the level 2 convolutional interleaver is 130 symbols; and /Or, the stage 3 convolutional interleaver has a delay of 260 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules; the first-level convolutional interleaving module The delay between two adjacent sub-channels in the processor is 46 symbols; and/or the delay of the second-stage convolutional interleaver is 230 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules; the first-level convolutional interleaving module The delay between two adjacent sub-channels in the processor is 46 symbols; and/or the delay of the second-stage convolutional interleaver is 276 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; the delay between two adjacent sub-channels in the level 1 convolutional interleaver is 46 symbols; and/or, the delay in the level 2 convolutional interleaver is 230 symbols; and/or, the level 3 convolutional interleaver The delay of the product interleaver is 414 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; the delay between two adjacent sub-channels in the level 1 convolutional interleaver is 46 symbols; and/or, the delay in the level 2 convolutional interleaver is 276 symbols; and/or, the level 3 convolutional interleaver The delay of the product interleaver is 552 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; the delay between two adjacent sub-channels in the level 1 convolutional interleaver is 48 symbols; and/or, the delay in the level 2 convolutional interleaver is 240 symbols; and/or, the level 3 convolutional interleaver The delay of the product interleaver is 432 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; the delay between two adjacent sub-channels in the level 1 convolutional interleaver is 48 symbols; and/or, the delay in the level 2 convolutional interleaver is 288 symbols; and/or, the level 3 convolutional interleaver The delay of the product interleaver is 576 symbols.

In a possible implementation, the first-level convolutional interleaver includes 3 sub-channels, and the x-1-level convolutional interleaver except the first convolutional interleaver all includes 2 sub-channels; except the first-level convolutional interleaver, The delay of two adjacent stages of convolutional interleaver in the x-1 stage convolutional interleaver outside the convolutional interleaver satisfies the following formula 4:
Δ _k ＝2×Δ _k-1 ＝2 ^k-1 ×3×Δ _1Formula 4

Among them, Δ _k-1 is the delay of the k-1th stage interleaver, and Δ ₁ is the delay between two adjacent sub-channels in the first-stage convolutional interleaver.

In a possible implementation manner, the x-level convolution interleaver included in the first convolutional interleaving module includes the same number of sub-channels, and the first convolutional interleaving module is any one of z convolutional interleaving modules.

For example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules; the first-level convolutional interleaver The delay between two adjacent sub-channels is 36 symbols; and/or the delay of the second-stage convolutional interleaver is 72 symbols.

In a possible implementation manner, the x-level convolutional interleaver included in the first convolutional interleaving module includes the same number of sub-channels.

In a possible implementation, each x-level convolutional interleaver includes 2 sub-channels; the delay of two adjacent levels of convolutional interleaver in the x-level convolutional interleaver satisfies the following formula 5:
Δ _k ＝2×Δ _k-1 ＝2 ^k-1 ×Δ _1Formula 5

Among them, Δk _-1 is the delay of the k-1th stage interleaver.

Exemplarily, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver, and the first convolutional interleaving module is any one of the z convolutional interleaving modules; The delay between two adjacent sub-channels in the first-stage convolutional interleaver is 36 symbols; and/or the delay in the second-stage convolutional interleaver is 72 symbols.

For example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver; a delay of 34 symbols between two adjacent sub-channels in the first-level convolutional interleaver; and/or, The delay of the stage 2 convolutional interleaver is 68 symbols.

For example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver; a delay of 38 symbols between two adjacent sub-channels in the first-level convolutional interleaver; and/or, The delay of the stage 2 convolutional interleaver is 76 symbols.

For example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules. ; The delay between two adjacent sub-channels in the first-level convolutional interleaver is 34 symbols; and/or, the delay in the second-level convolutional interleaver is 68 symbols; and/or, the third-level convolutional interleaving The delay of the processor is 136 symbols.

For example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules. ; The delay between two adjacent sub-channels in the first-level convolutional interleaver is 68 symbols; and/or, the delay in the second-level convolutional interleaver is 136 symbols; and/or, the third-level convolutional interleaving The delay of the processor is 272 symbols.

For example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any one of z convolutional interleaving modules. ; The delay between two adjacent sub-channels in the first-level convolutional interleaver is 70 symbols; and/or, the delay in the second-level convolutional interleaver is 140 symbols; and/or, the third-level convolutional interleaving The delay of the processor is 280 symbols.

For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. The first convolutional interleaving module is any of z convolutional interleaving modules. a; a delay of 72 symbols between two adjacent sub-channels in the convolutional interleaver at stage 1; and/or, a delay of 144 symbols in the convolutional interleaver at stage 2; and/or, a convolutional stage 3 The interleaver delay is 288 symbols.

In a possible implementation, the number of input symbols of the sub-channels of the x-level convolution interleaver included in the first convolutional interleaving module is the same, and the sub-channels of the x-level convolutional interleaver included in the first convolutional interleaving module The number of output symbols is the same, and the number of input symbols of the sub-channel of the k-th level convolution interleaver is greater than the number of output symbols of the sub-channel of the k-th level convolution interleaver; among them, the k-th level convolution interleaver is the first Any one of the x convolutional interleavers in the convolutional interleaving module, the first convolutional interleaving module is any one of the z convolutional interleaving modules, and k is a positive integer less than or equal to x.

In a possible implementation, the input interleaving depth of the first convolutional interleaving module is related to the coding method and symbol distribution method of the PCS layer; the output interleaving depth of the first convolutional interleaving module is interleaving depth × p ₁ ×… p _x-1 ×p _x , p ₁ is the number of sub-channels included in the first-level interleaver of the first convolutional interleaving module, _p The number of sub-channels included in the interleaver, p _x is the number of sub-channels included in the x-th level convolution interleaver of the first convolution interleaving module.

In a possible implementation, the number of input symbols of the sub-channels of the x-level convolutional interleaver is obtained based on the number of sub-channels of the x-level convolutional interleaver and the maximum interleaving depth output by the first convolutional interleaving module; The number of output symbols of the sub-channels of the x-level convolutional interleaver is obtained according to the input interleaving depth of the first convolutional interleaving module.

In a possible implementation, the number of input symbols of the sub-channels of the x-level convolutional interleaver is equal to the maximum interleaving depth of the output of the first convolutional interleaving module divided by the number of sub-channels of the x-th level convolutional interleaver; x The number of output symbols of the sub-channels of the first-stage convolutional interleaver is equal to the input interleaving depth of the first convolutional interleaving module.

In a possible implementation, the number of input symbols of the sub-channels of the x-level convolutional interleaver and the number of output symbols of the sub-channels of the x-level convolutional interleaver are any of the following: The number of input symbols of the sub-channel is 8, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is 2; or, the number of input symbols of the sub-channel of the x-level convolutional interleaver is 6, and the number of The number of output symbols of the sub-channel is 2; alternatively, the number of input symbols of the sub-channel of the x-level convolutional interleaver is 4, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is 2; or, The number of input symbols of the sub-channel of the x-level convolution interleaver is 8, and the number of output symbols of the sub-channel of the The number of output symbols of the sub-channel of the x-level convolutional interleaver is 1; alternatively, the number of input symbols of the sub-channel of the x-level convolutional interleaver is 4, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is 1.

In a possible implementation, the device further includes an AM locking module, which is used to align boundaries of symbols in the first data stream.

In a possible implementation, the device further includes an inner code encoding module, and the inner code encoding module is used to encode the second data stream.

In a second aspect, the present application provides an optical module, which may include the above-mentioned first aspect or any one of the data transmission devices in the first aspect.

The technical effects that can be achieved in the above second aspect can be referred to the description of the beneficial effects in the above first aspect, and will not be repeated here.

Description of the drawings

Figure 1a is a schematic diagram of the architecture of a data center applicable to this application;

Figure 1b is a schematic diagram of the architecture of another data center to which this application can be applied;

Figure 2a is a schematic structural diagram of an optical module provided by this application;

Figure 2b is a schematic structural diagram of another optical module provided by this application;

Figure 3 is a schematic structural diagram of a device provided by this application;

Figure 4 is a schematic diagram of communication between an optical module and equipment provided by this application;

Figure 5 is a schematic structural diagram of a data transmission device provided by this application;

Figure 6a is a schematic structural diagram of z roll call interleaving modules provided by this application;

Figure 6b is a schematic structural diagram of another z volume interleaving module provided by this application;

Figure 7a is a schematic structural diagram of another z convolution interleaving module provided by this application;

Figure 7b is a schematic structural diagram of another z convolutional interleaving module provided by this application;

Figure 8 is a schematic structural diagram of a k-th level convolutional interleaver provided by this application;

Figure 9 is a schematic structural diagram of a first convolutional interleaving module provided by this application;

Figure 10 is a schematic structural diagram of a first convolutional interleaving module provided by this application;

Figure 11 is a schematic structural diagram of yet another first convolutional interleaving module provided by this application;

Figure 12 is a schematic structural diagram of another first convolutional interleaving module provided by this application;

Figure 13 is a schematic structural diagram of yet another first convolutional interleaving module provided by this application;

Figure 14 is a schematic structural diagram of another k-th level convolutional interleaver provided by this application;

Figure 15 is a schematic structural diagram of yet another first convolutional interleaving module provided by this application;

Figure 16 is a schematic structural diagram of another first convolutional interleaving module provided by this application;

Figure 17 is a schematic structural diagram of yet another first convolutional interleaving module provided by this application;

Figure 18 is a schematic structural diagram of yet another first convolutional interleaving module provided by this application.

Detailed ways

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Below, some terms used in this application are explained. It should be noted that these explanations are for the convenience of understanding by those skilled in the art and do not limit the scope of protection claimed by this application.

1. The relationship between codewords and symbols

Taking the PCS layer of the 800G-Ethernet technology consortium (ETC) mode as an example, each PCS layer includes 4 Reed-Solomon (RS) codewords, and the RS codeword is represented as KP4 (544, 514), KP4 (544, 514) means that a codeword includes 544 symbols. The PCS layer in 800G-ETC mode has a total of 32 PCS channels. Every two RS codewords are a group. The codewords of the first group are represented by RS codeword A and RS codeword B. The codewords of the second group are represented by RS codeword C and RS codeword D. The codewords of the third group are represented by RS codeword C and RS codeword D. The codewords are identified as RS codeword E and RS codeword F. The symbol of RS codeword A is represented by symbol a, the symbol of RS codeword B is represented by symbol b, the symbol of RS codeword C is represented by symbol c, the symbol of RS codeword D is represented by symbol c, and the symbol of RS codeword E is represented by symbol c. The symbol is represented by symbol e, and the symbol of RS codeword F is represented by symbol f. One group is allocated to 16 PCS channels. Taking one group as an example, each PCS channel can be allocated to 2×544/16=68 symbols, and each channel is interleaved with two symbols. Specifically, taking the first group of codewords (RS codeword A and RS codeword B) as an example, each PCS channel on the 16 PCS channels is an interleaving of symbol a and symbol b, with a total of 34 interleaved ab , each a represents the symbol of a position of codeword a. For example, the first a represents the 543rd symbol of codeword A, and each b represents the symbol of a position of codeword B. For example, the first b represents the 544th symbol of codeword B.

Taking the possible PCS layer of IEEE 800G as an example, each PCS layer includes 2 RS codewords. The codeword is represented as KP4 (544, 514). KP4 (544, 514) indicates that a codeword includes 544 symbols. The PCS layer in IEEE 800G mode has a total of 16 PCS channels, and the rate of each channel is 50Gbps. Every two RS codewords are a group. The codewords of the first group are represented by RS codeword A and RS codeword B. The codewords of the second group are represented by RS codeword C and RS codeword D. The codewords of the third group are represented by RS codeword C and RS codeword D. The codewords are identified as RS codeword E and RS codeword F. The symbol of RS codeword A is represented by symbol a, the symbol of RS codeword B is represented by symbol b, the symbol of RS codeword C is represented by symbol c, the symbol of RS codeword D is represented by symbol c, and the symbol of RS codeword E is represented by symbol c. The symbol is represented by symbol e, and the symbol of RS codeword F is represented by symbol f. One group is allocated to 16 PCS channels. Taking one group as an example, each PCS channel can be allocated to 2×544/16=68 symbols, and each channel is interleaved with two symbols. Specifically, taking the first group of codewords (RS codeword A and RS codeword B) as an example, each PCS channel on the 16 PCS channels is an interleaving of symbol a and symbol b, with a total of 34 interleaved ab , each a represents the symbol of a position of codeword a. For example, the first a represents the 543rd symbol of codeword A, and each b represents the symbol of a position of codeword B. For example, the first b represents the 544th symbol of codeword B.

Taking the possible PCS layer of IEEE 800G as an example, each PCS layer includes 2 RS codewords. The codeword is represented as KP4 (544, 514). KP4 (544, 514) indicates that a codeword includes 544 symbols. The PCS layer in IEEE 800G mode has a total of 8 PCS channels, and the rate of each channel is 100Gbps. Every two RS codewords are a group. The codewords of the first group are represented by RS codeword A and RS codeword B. The codewords of the second group are represented by RS codeword C and RS codeword D. The codewords of the third group are represented by RS codeword C and RS codeword D. The codewords are identified as RS codeword E and RS codeword F. The symbol of RS codeword A is represented by symbol a, the symbol of RS codeword B is represented by symbol b, the symbol of RS codeword C is represented by symbol c, the symbol of RS codeword D is represented by symbol c, and the symbol of RS codeword E is represented by symbol c. The symbol is represented by symbol e, and the symbol of RS codeword F is represented by symbol f. One group is allocated to 8 PCS channels. Taking one group as an example, each PCS channel can be allocated to 2×544/8=136 symbols, and each channel is interleaved with two symbols. Specifically, taking the first group of codewords (RS codeword A and RS codeword B) as an example, each PCS channel on the 8 PCS channels is an interleaving of symbol a and symbol b, with a total of 68 interleaved ab , each a represents a bit of codeword a set symbol. For example, the first a represents the 543rd symbol of codeword A, and each b represents the symbol of a position of codeword B. For example, the first b represents the 544th symbol of codeword B.

It should be noted that the outer codewords of the PCS layer on the host side are RS(544,514), and the number of included codewords may also be 3 or 4, etc. Alternatively, the outer code word of the PCS layer on the host side is RS (576, 514), and the number of code words contained is 1, 2, 3, or 4, etc.

2. Field

Field refers to the number of symbols input to each stage of the convolutional interleaver at one time. Taking the 800G-ETC mode as an example, the total number of symbols allocated by two codewords to a PCS channel can be called a symbol set, and a symbol set includes 68 symbols. Taking the first data stream including three symbol sets as an example and each field including 4 symbols as an example, each symbol set includes 17 fields. Symbol set 1 is abababab…ab, repeated 34 times; symbol set 2 is cdcdcdcd…cd, repeated 34 times; symbol set 3 is efefefef…ef, repeated 34 times. The first field to the 17th field are abab, the 18th field to the 34th field are cdcd, and so on.

The previous article introduced some terms involved in this application, and the possible structure of this application is introduced below.

Figure 1a is a schematic diagram of the architecture of a data center to which this application can be applied. The data center network includes three layers, namely the core layer (Core), the aggregation layer (Aggregation) and the access layer (Access). The access layer can also be called the edge layer. Each layer may include one or more devices (or hosts). Figure 1a takes the example of the core layer including 2 devices, the aggregation layer including 4 devices, and the access layer including 3 devices. Among them, the devices included in the core layer can be called Core nodes, the devices included in the aggregation layer can be called Aggregation nodes, and the devices included in the access layer can be called Access nodes or top of rack (TOR) nodes. The device may be, for example, a switch or a host.

In the architecture shown in Figure 1a, the downlink port of the Access node can be connected to the server (Server), the uplink port of the Access node can be connected to the Aggregatio node; the downlink port of the Aggregation node can be connected to the Access node, and the uplink port of the Aggregation node can be connected to the Core node . Among them, the Core node can be called the upstream node of the Aggregation node, and the Aggregation node can be called the upstream node of the Access node.

It should be noted that the architecture of the data center shown in Figure 1a is only an example, and the data center can also be divided into two layers, or it can also be divided into three or more layers. In addition, the number of devices included in the core layer, aggregation layer and access layer may be the same or different, and this application does not limit this.

Figure 1b is a schematic diagram of the architecture of another data center to which this application can be applied. The data center network includes two levels of equipment, namely spine equipment and leaf equipment. Among them, a backbone device is used to connect to each leaf device, and the leaf devices are used to connect to the server. Figure 1b takes 2 backbone devices and 4 leaf devices as an example. It can be understood that the architecture of the data center shown in Figure 1b is only an example. The number of backbone devices and leaf devices included in the data center may be the same or different, and this application does not limit this.

The above data center can be used in short-distance interconnection, cloud storage, cloud computing, fifth-generation (5rd-Generation, 5G) base station backbone network, augmented reality/virtual reality (AR/VR), artificial intelligence ( This application does not limit application scenarios such as artificial intelligence (AI), cloud computing, cloud storage, optical transmission, optical access or base station fronthaul.

In a possible implementation, the above-mentioned device in Figure 1a or Figure 1b is also provided with an optical module or an electrical module to implement communication between the devices. Optical modules or electrical modules can be targeted at next-generation Ethernet, B800 Gigabit (G)-SR4, B400G-DR4, B400G-DR4-2, B400G-FR4, B400G-LR4, B400G-FR1, B400G-LR2, B400G- LR1 and other pluggable optical modules. Among them, 800GBASE-SR4 means 800 gigabit per second data stream PCS or PMA pass PMD transmission through 4 pairs of multimode optical fibers. 800GBASE-SR8 means that 800 gigabits per second data stream PCS/PMA is transmitted through 8 pairs of PMDs of multimode optical fiber. 800GBASE-SR16 means that 800 gigabits per second data stream PCS/PMA is transmitted through 16 pairs of multimode fiber PMDs. 800GBASE-DR4 means that 800 gigabits per second data stream PCS/PMA is transmitted through PMD of 4 pairs of single-mode optical fibers, with a coverage range of 500 meters (m). 800GBASE-DR8 means that 800 gigabits per second data stream PCS/PMA is transmitted through 8 pairs of PMD single-mode optical fibers, with a coverage range of 500m. 800GBASE-DR4-2 means that 800 gigabits per second data stream PCS/PMA is transmitted through PMD of 4 pairs of single-mode optical fibers, with a coverage range of 2km. 800GBASE-DR8-2 means that 800 gigabit per second data stream PCS/PMA is transmitted through 8 pairs of single-mode fiber PMD, with a coverage range of 2km. 800GBASE-FR4 means that the 800 gigabit per second data stream PCS/PMA uses 4-level amplitude modulation and is transmitted through PMD transmission of 4 WDM (wavelength division multiplexing) channels on a pair of single-mode optical fibers, with a coverage range of 2km. 800GBASE-LR4 means 800 gigabit per second data stream PCS/PMA uses 4-level amplitude modulation and is transmitted through PMD transmission of 4 wavelength division multiplexing (WDM) channels on a pair of single-mode optical fibers, covering the range Reach 10km.

Please refer to Figure 2a, which is a schematic structural diagram of an optical module provided by this application. The optical module may include a physical media dependent (PMD) layer and a physical medium attachment (PMA) layer. Furthermore, the PMA layer includes units that can implement the functions of the inner (Inner)-FEC layer. It can also be understood that the functions of the Inner-FEC layer are integrated in the PMA layer.

Please refer to Figure 2b, which is a schematic structural diagram of another optical module provided by this application. The optical module may include a PMD layer, a PMA layer and an Inner-FEC layer. It can also be understood that the Inner-FEC layer and the PMA layer are two independent layers.

Please refer to Figure 3, which is a schematic structural diagram of a device provided by this application. The device may include a physical coding sublayer (PCS) and an Inner-FEC layer; alternatively, the Inner-FEC layer function is integrated into the PCS.

Please refer to Figure 4, which is a schematic diagram of a communication method between an optical module and a device provided in this application. The optical module in this example takes the structure shown in Figure 2b above as an example. The attachment unit interface (AUI) is included between the optical module and the device. Specifically, the PMA layer or Inner-FEC layer of the optical module and the PCS layer of the device can communicate through the AUI. For example, the data flow can be exchanged between the PMA layer or Inner-FEC layer of the optical module and the PCS layer of the device through the AUI. Furthermore, the management data input/output (MDIO) interface is also included between the optical module and the device. Specifically, the PMA layer or FEC layer of the optical module and the PCS layer of the device can communicate through the MDIO interface. For example, the indication signal can be transmitted through the MDIO interface between the PMA layer or FEC layer of the optical module and the PCS layer of the device.

Based on the above content, the data transmission device proposed in this application will be described in detail below with reference to the accompanying drawings.

As shown in Figure 5, it is a schematic structural diagram of a data transmission device provided by this application. The data transmission device may include z physical coding sub-layer PCS channels and z convolutional interleaving modules. One convolutional interleaving module corresponds to one PCS channel. The convolutional interleaving module includes cascaded x-level convolutional interleaver, x is An integer greater than 1, z is a positive integer, such as z equals 8, 16 or 32, etc.; PCS channel, used to receive the first data stream from the PCS layer, one first data stream corresponds to one PCS channel; convolution interleave module, It is used to interleave the first data stream from the corresponding PCS channel to obtain the second data stream. The interleaving depth of the second data stream is related to the input bit number of the inner code encoder.

With reference to the above-mentioned Figure 2a, Figure 2b and Figure 3, z convolutional interleaving modules can be integrated in the PMA layer or Inner-FEC layer of the optical module. It can also be understood that the optical module can include the above-mentioned data transmission device. Or z convolutional interleaving modules can also be integrated into the PCS layer of the device. In other words, the device can include the above-mentioned data transmission device. This application does not limit this.

Based on the above data transmission device, multiple convolutional interleaver are cascaded, which can flexibly select the number of cascaded interleaver stages, thereby not only meeting the transmission performance of the data stream, but also helping to reduce the delay of data stream transmission.

In a possible implementation, the Inner FEC encoder (n, k) refers to a code whose input is k bits and whose output is n bits. n and k are positive integers, and k is the length of a symbol (such as a symbol). Integer multiple. Among them, the code with k=120 and n=128 is the extended Hamming code, also known as Extended Hamming (128, 120) code; or the code with k=170, n=180 is the extended Hamming code, also known as Extended Hamming (180, 170) code; or the code with k=136, n=144 is Hamming code, also known as Hamming (180, 170) code; or the code with k=68, n=76 is extended Hamming code, Also known as Extended Hamming (76, 68) encoding; or k = 170, n = 180 encoding, which is double extended Hamming encoding, also known as Doubly Extended Hamming (180, 170) encoding; or k = 160, n = 180 The encoding is double extended Hamming encoding, also known as Doubly Extended BCH (180, 160) encoding; or the encoding of k=110, n=126 is double extended Hamming encoding, also called Doubly Extended BCH (126, 110) encoding . It can be understood that k is also called a payload bit or an information bit.

Taking the inner code encoder as Extended Hamming (128, 120) encoding as an example, the length of a symbol is 10 bits, and the number of input bits of the inner code encoder is 120, which means that the maximum interleaving depth required by the inner code encoder is 120/10= 12. Further, it is explained that the maximum interleaving depth of the second data stream output from the data transmission device is 12. It should be noted that the maximum interleaving depth required by inner code encoders using other encoding methods can be found in the introduction of Extended Hamming (128, 120), which will not be described again here.

In a possible implementation, z convolutional interleaving modules can bypass a certain level or levels of convolutional interleaver and directly enter the inner code encoder according to the received instruction signal, thereby enabling flexible adjustment of the convolutional interleaver. The delay of the interleaver can also be flexibly selected by the inner code encoder. The indication signal may include but is not limited to a bypass or bypass signal. A valid bypass signal indicates that the convolution interleaver needs to be bypassed, and an invalid bypass signal indicates that the convolution interleaver needs to be passed through (or not bypassed or enabled).

Two possible ways of indicating signals are exemplarily shown below.

Method 1, the indication signal is a one-dimensional signal.

In a possible implementation, the indication signal is used to instruct to bypass (or bypass or disable) the convolutional interleaver of the same stage in z convolutional interleaving modules. It can also be understood that convolutional interleaver of the same stage in z convolutional interleaving modules share an instruction signal. In other words, one instruction signal can control convolutional interleaver of the same stage in z convolutional interleaving modules. Among them, bypassing the convolutional interleaver means that the data stream does not pass through the convolutional interleaver.

Please refer to Figure 6a, which is a schematic structural diagram of z curl interleaving modules provided by this application. In this example, x=3 is taken as an example. A convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. An indication signal can indicate to bypass all the third-level convolutional interleaver in the z convolutional interleaving modules. In other words, the bypass signal input to the third-level convolutional interleaver in the z convolutional interleaving modules is valid and input to The bypass signals of the second-level convolutional interleaver and the first-level convolutional interleaver in z convolutional interleaving modules are invalid. Specifically, the indication signal is used to indicate to bypass the z third-level convolutional interleaver on PCS channel 1 to PCS channel z, that is: field 1 from PCS channel 1 passes through the first-level convolutional interleaver and the second-level convolutional interleaver. The interleaving of the convolutional interleaver bypasses (or does not go through) the third-level convolutional interleaver and directly enters the inner code encoder; field 2 from PCS channel 2 passes through the first-level convolutional interleaver and the second-level convolutional interleaver. The interleaving of the product interleaver directly enters the inner code encoder without passing through the third-level convolutional interleaver; and by analogy, the field z from the PCS channel z passes through the first-level convolutional interleaver and the second-level convolutional interleaver. Interleaving, directly enters the inner code encoder without going through the third-level convolutional interleaver. It can be understood that field 1, field 2...field z all belong to the first data flow.

Alternatively, the indication signal may also indicate bypassing two or more stages of convolutional interleaver. Referring to Figure 6b, the indication signal may also indicate to bypass the 3rd level convolutional interleaver and the 2nd level convolutional interleaver in the z convolutional interleaving modules. Specifically, the indication signal indicates that z second-level convolutional interleavers and z third-level convolutional interleavers on PCS channel 1 to PCS channel z are bypassed, and field 1 from PCS channel 1 passes through the first-level convolution. Interleaving of the interleaver, bypassing (or not passing through) the 2nd-level convolutional interleaver and the 3rd-level convolutional interleaver directly enters the inner code encoder; field 2 from PCS channel 2 goes through the 1st-level convolution The interleaving of the interleaver directly enters the inner code encoder without passing through the second-level convolutional interleaver and the third-level convolutional interleaver; and so on, the field z from PCS channel z is interleaved by the first-level convolutional interleaver. , directly enters the inner code encoder without passing through the second-level convolutional interleaver and the third-level convolutional interleaver.

In a possible implementation manner, among the z convolutional interleaving modules, the convolutional interleaver of the same stage is connected to a first register included in the optical module. Combined with the above-mentioned Figure 6a or Figure 6b, among the z convolutional interleaving modules, the z first-level convolutional interleavers are connected to the first register 1, and the z second-level convolutional interleavers are connected to the first register 2. The z third-level convolution interleavers are all connected to the first register 3. For example, the indication signal can be represented by three bits, for example, 001 indicates bypassing the third-level convolutional interleaver, 011 indicates bypassing the second-level convolutional interleaver and the third-level convolutional interleaver, and 111 indicates bypassing the first-level convolutional interleaver. Level 1 convolution interleaver, Level 2 convolution interleaver and Level 3 convolution interleaver, 000 indicates passing through Level 1 convolution interleaver, Level 2 convolution interleaver and Level 3 convolution interleaver. It should be noted that the specific form of the indication signal may be agreed in advance or specified in an agreement, which is not limited in this application.

Through the indication signal of the above method 1, it is possible to flexibly control which level or levels of convolution interleaver among the z convolution interleave modules to be bypassed, so that there is no need to limit the bit width of the inner code encoder, and thus the choice can be flexibly Internal code encoder.

Method 2: The indication signal is a two-dimensional signal.

In a possible implementation, the indication signal is used to indicate to bypass the j-th convolutional interleaver in the i-th convolutional interleaving module among the z convolutional interleaving modules, i is an integer less than z, and j is An integer less than x. It can also be understood that each convolutional interleaving module is controlled by an independent instruction signal. In other words, one instruction signal can control one or several convolutional interleaver. For example, it can be expressed as (convolutional interleaving module i, convolutional interleaver stage number j) or (PCS sub-channel i, convolutional interleaver stage number j), where, (convolutional interleaving module i, convolutional interleaver stage number j) The level j) represents the j-th level convolution interleaver in the i-th convolution interleaving module, (PCS channel i, convolution interleaver level j) represents the j-th level convolution interleaver corresponding to the i-th PCS channel .

Please refer to Figure 7a, which is a schematic structural diagram of another z convolutional interleaving module provided by this application. In this example, x=3 is taken as an example. The indication signal (PCS channel 1 to PCS channel z, third-level convolutional interleaver) is used to indicate to bypass the third-level convolutional interleaver corresponding to PCS channel 1 to PCS channel z. The indication signal (PCS channel 2 to PCS channel z, second-level convolutional interleaver) is used to indicate bypassing the second-level convolutional interleaver corresponding to PCS channel 2 to PCS channel z.

Please refer to Figure 7b, which is a schematic structural diagram of another z convolutional interleaving module provided by this application. In this example, x=3 is taken as an example. The indication signal (PCS channel 1 to PCS channel z, third-level convolutional interleaver) is used to indicate to bypass the third-level convolutional interleaver corresponding to PCS channel 1 to PCS channel z. The indication signal (PCS channel 2 to PCS channel z, second-level convolutional interleaver) is used to bypass the second-level convolutional interleaver corresponding to PCS channel 2 to PCS channel z; the indication signal (PCS channel z, first-level convolutional interleaver) is used to indicate Bypass the first-level convolutional interleaver corresponding to PCS channel z.

In a possible implementation, the one-stage convolutional interleaver is connected to a first register. Combined with the above-mentioned Figure 7a and Figure 7b, each stage of the convolutional interleaver in the z convolutional interleaving modules is connected to a first register. Taking the interleaving module corresponding to PCS channel 1 as an example, the first-level convolutional interleaver is connected to the first register 1, the second-level convolutional interleaver is connected to the first register 2, and the third-level convolutional interleaver is connected to the first register. 3 connections. For example, the indication signal may be represented by 1 bit For example, 1 indicates to bypass the convolutional interleaver, and 0 indicates to bypass the convolutional interleaver.

In another possible implementation, some convolutional interleaver in the same stage of convolutional interleaver share a first register. Combined with the above Figure 7b, for example, the second-level convolutional interleaver corresponding to PCS channel 2 to PCS channel z is connected to a first register. It can also be understood that z-1 second-level convolutional interleaver is connected to a first register. The first register is connected, and the second-stage convolutional interleaver corresponding to PCS channel 1 is connected to a first register. For another example, the second-level convolutional interleaver corresponding to PCS channel 1 to PCS channel 2 is connected to a first register, and the second-level convolutional interleaver corresponding to PCS channel 3 to PCS channel z is connected to a first register.

Through the indication signal of the above-mentioned method 2, the number of cascaded convolution interleaver stages of each convolution interleave module can be independently controlled, thereby enabling different error correction capabilities on different PCS channels and helping to further increase the number of applications. scene. For example, hash (Breakout) transmission mode can be supported.

It should be noted that for each convolutional interleaving module, the indication signal needs to indicate bypass starting from the last stage of convolutional interleaving, and cannot bypass across levels. Combined with the above-mentioned Figure 7b, for each convolutional interleaving module, the indication signal must start from the third-level convolutional interleaver to indicate bypass.

Based on the above content, the following exemplarily shows a possible implementation manner of transmitting the indication signal.

Implementation method 1, through the MDIO interface between the device and the optical module.

In a possible implementation, the device sends the first information to the optical module through the MDIO interface. The first information includes the value of the MDIO control bit, which is mapped to the control bit of the x-level convolutional interleaver. Correspondingly, the optical module receives the first information from the host through the MDIO interface, and the PMA layer or the FEC layer can control which stage or stages of the x-level convolutional interleaver to bypass based on the first information.

As shown in Table 1, this application provides a mapping relationship between the MDIO control bits and the control bits of the three-level convolutional interleaver. Table 1 takes the convolutional interleaving module as an example including a three-level convolutional interleaver (respectively: a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver). Specifically, taking the control of the third-level convolution interleaver as an example, the host-side Inner-CI-3 bypass indication enable (column 1 of Table 1) uses the MDIO interface to control the control bit of the second register included in the host (the third column) value (such as 1 or 0) is sent to the Inner-FEC control register (column 2) on the optical module side, and the Inner-FEC control register on the optical module side sends the corresponding third-level convolutional interleaver to the The value of the control bit of a register is refreshed to (such as 1 or 0), and is controlled by FEC_bypass_CI3_enable (column 4) to bypass or pass through the third-level convolutional interleaver. Taking 1.200.6 as an example, "1" represents the device address, "200" represents the register address, and "6" represents the control bit of the register. It can be understood that the value of the control bit of the first register connected to the convolutional interleaver is related to the bypass indication signal. For example, the value of the control bit of the first register connected to the convolutional interleaver is 1, indicating that the bypass indication signal is valid, and the value of the control bit of the first register connected to the convolutional interleaver is 0, indicating that the bypass indication signal is invalid.

Table 1 Mapping relationship between MDIO control bits and control bits of cascaded 3-level convolutional interleaver

In Table 1, FEC_bypass_correction_enable is set to 1, which means that the inner code decoder performs error detection without error correction. FEC_bypass_correction_enable is set to 0, indicating that the inner code decoder performs error detection and correction. FEC bypass indication enable is set to 1, indicating that the error indication function is bypassed. When FEC bypass indication enable is set to 0, it means that the decoder indicates the error to the PCS layer.

When Inner-CI-3bypass indication enable is set to 1, it means to bypass the function of the third-level convolutional interleaver (CI3), or to bypass the third-level convolutional interleaver. When Inner-CI-3bypass indication enable is set to 0, it means not to bypass the function of the third-level convolutional interleaver, or to pass through (or not bypass) the third-level convolutional interleaver. When Inner-CI-2bypass indication enable is set to 1, it means to bypass the function of the second-level convolutional interleaver (CI2), or to bypass the second-level convolutional interleaver. When Inner-CI-2bypass indication enable is set to 0, it means that the function of the second-level convolutional interleaver is not bypassed. When Inner-CI-1bypass indication enable is set to 1, it means to bypass the function of the first-level convolutional interleaver (CI1), or to bypass the first-level convolutional interleaver. When Inner-CI-1bypass indication enable is set to 0, it means that the function of the first-level convolutional interleaver is not bypassed. It should be noted that the default value of each variable in Table 1 above is 0.

Table 2 takes the convolutional interleaving module as an example including 3-level convolutional interleaver (such as the 1st-level convolutional interleaver, the 2nd-level convolutional interleaver and the 3rd-level convolutional interleaver). The Inner-FEC layer can choose to wrap Through the functions of the third-level convolutional interleaver (CI3) and/or the second-level convolutional interleaver (CI2) and/or the first-level convolutional interleaver (CI1), the delay of the Inner-FEC layer can be reduced. Furthermore, the PMA layer of the optical module can report Table 2 to the host, so that the host can determine the indication signal.

Table 2 Mapping relationship between MDIO status and status bits of 3-cascade convolutional interleaver

When Inner-CI-3bypass indication ability is set to 1, it means that the Inner-FEC layer has the ability to bypass the third level convolutional interleaver (CI3); when Inner-CI-3bypass indication ability is set to 0, it means that the Inner-FEC layer The ability to bypass the convolutional interleaver level 3 (CI3) is not supported. When Inner-CI-2bypass indication ability is set to 1, it means that the Inner-FEC layer has the ability to bypass the second-level convolutional interleaver (CI2); when Inner-CI-1bypass indication ability is set to 0, it means that the Inner-FEC layer The ability to bypass the convolutional interleaver level 1 (CI1) is not supported. It should be noted that the default value of each variable in Table 2 above is 0.

Implementation method 2 is through the common management interface specification (CMIS) interface between the device and the optical module.

In a possible implementation, the device can determine which convolution interleaver(s) to bypass and which convolution interleaver(s) to pass through (or not bypass). The device can update the volume to the optical module through the CMIS interface. The control bit value of the first register corresponding to the product interleaver is taken. Combined with the above Figure 6a, the device can determine to bypass the third-level convolution interleaver in the z convolution interleaving modules, pass the first-level convolution interleaver and the second-level convolution interleaver, and transfer the third-level convolution interleaver through the CMIS interface. The value of the control bit of the first register corresponding to the product interleaver is refreshed to 1, and the value of the control bit of the first register corresponding to the first-stage convolutional interleaver and the second-stage convolutional interleaver is refreshed to 0.

Exemplarily, the CMIS interface may include, but is not limited to, an integrated circuit bus I2C general software interface.

Implementation method 3, through the AUI between the device and the optical module.

In a possible implementation, the indication signal is a first preset sequence. Specifically, the PCS layer inserts the first preset sequence into the AM sequence. Further, the PCS layer may insert the first preset sequence into the pad bits of the AM sequence. The PCS layer sends and inserts a first data stream to the PMA layer or FEC layer. The first data stream includes an AM sequence, and the AM sequence includes a first preset sequence. Correspondingly, the PMA layer or FEC layer can extract the corresponding first preset sequence during the AM locking (Lock) process on the first data stream, thereby determining which convolutional interleaver or interleaver to bypass. Alternatively, the PMA layer or FEC layer performs AM lock on the first data stream and then extracts the corresponding first preset sequence to determine which convolutional interleaver or interleavers to bypass.

In another possible implementation, the indication signal is a second preset sequence. Specifically, the PCS layer separately sends the second preset sequence to the PMA layer or FEC layer. Correspondingly, the PMA layer or the FEC layer may determine which convolutional interleaver(s) to bypass based on the second preset sequence.

It should be noted that the first preset sequence and the second preset sequence may be pre-agreed between the PCS layer and the PMA layer or the FEC layer, or may be specified by a protocol, which is not limited in this application.

It can be understood that the indication signal can also be implemented through other possible transmission methods. The three implementation methods given above are only examples, and this application does not limit them.

In a possible implementation, the data stream of the PCS layer is transmitted to the PMA layer or FEC layer through z PCS channels (or called logical channels). The PMA layer or FEC layer recovers (or demultiplexes) z data streams. The AM locking module included in the data transmission device can first align the boundaries of symbols of the z data streams. Specifically, the AM locking module performs a symbol boundary locking operation on z data streams, or it is called an alignment operation on the boundary of a symbol-level data block (such as a 10-bit RS symbol), or it is called AM locking (Lock), or it is called AM locking (Lock). Boundary locking for 10-bit data blocks, or q-symbol alignment, or q×10-bit data block boundary alignment, or q-symbol boundary locking, or q×10-bit data block boundary locking, specifically The process can be found in the introduction of the prior art and will not be described in detail here.

The symbols in this application may be, for example, RS symbols, or they may be half RS symbols, or four-level pulse amplitude modulation (PAM4) symbols, etc., which are not limited in this application. Among them, the RS symbol is a data block with a length of 10 bits, the half RS symbol is a data block with a length of 5 bits, and the PAM4 symbol is a data block with a length of 2 bits.

Further, the first data streams from z PCS channels are independently interleaved based on z convolutional interleaving modules. The minimum unit of the first data stream input by the x-cascaded convolutional interleaver included in the convolutional interleaving module is a symbol. It can also be understood that the granularity of the first data stream input to the convolutional interleaver is symbols. Specifically, the length of one input field of the convolutional interleaver includes q symbols, for example, q=1, 2, 4, 8, etc. The first data stream includes multiple fields, and each input convolution intersection Weaver a field, the length of the corresponding field is 10 bits, 20 bits, 40 bits or 80 bits.

In the following, one convolutional interleaving module among z convolutional interleaving modules is taken as an example, which is called the first convolutional interleaving module. The first convolution interleaving module includes an x-level convolution interleaver. Taking the first-level convolution interleaving in the x-level convolution interleaver as an example, it is called the k-th level convolution interleaver, and k is a positive integer less than or equal to x.

The following is a situation-by-case introduction based on the relationship between the number of input symbols of the sub-channel of the k-th stage convolutional interleaver and the number of output symbols of the sub-channel of the k-th stage convolutional interleaver.

Case 1: The number of input symbols of the sub-channel of the k-th stage convolutional interleaver is equal to the number of output symbols of the sub-channel of the k-th stage convolutional interleaver.

In other words, the number of input symbols and the number of output symbols of the sub-channel of the k-th stage convolutional interleaver are both w _k . It can also be understood that the size of the input slice data block on the sub-channel of the k-th level convolutional interleaver is equal to the size of the output slice data block.

Among them, the parameters of the k-th level convolution interleaver include (w _k , p _k , Δ _k ), where w _k represents the number of input symbols of the sub-channel of the k-th level convolution interleaver, and p _k represents the k-th level convolution interleaver. The number of sub-channels included in the product interleaver, Δ _k represents the delay of the k-th stage convolution interleaver, specifically indicating the delay of the k-th stage convolution interleaver by Δ _k symbols. Please refer to Figure 8, taking the k-th level convolutional interleaver as an example including 2 sub-channels (sub-channel 1 and sub-channel 2 respectively). The field abababab inputs the k-th level convolutional interleaver, a comes from codeword A, and b comes from code Word B. The number of symbols input to the sub-channel of the k-th stage convolutional interleaver is w _k =2, and w _k symbols are distributed to p _k sub-channels in a polling manner. Specifically, the distribution time of sub-channel 1 is T ₁ =2×t, and the distribution time of sub-channel 2 is T ₂ =2×t+1, and t is an integer. It can also be understood that w _k symbols are distributed to sub-channel 1 at time 0, w _k symbols are distributed to sub-channel 2 at time 1, w k symbols are distributed to sub-channel 1 at time 2, and w _k symbols are distributed to sub-channel 1 at time 3. Distribute w _k symbols to sub-channel 2, distribute w _k symbols to sub-channel 1 at the 4th moment, distribute w _k symbols to sub-channel 2 at the 5th moment, and so on. The delay of sub-channel 1 is 0 symbols and the delay of sub-channel 1 is Δ _k symbols.

It should be noted that sub-channel 1 may also have a delay. For example, the delay of sub-channel 1 is Δ _k symbols, and the delay of sub-channel 2 is 2Δ _k symbols, or the two sub-channels may also have other possible delay relationships. This application does not limit this. In addition, the number of sub-channels included in the k-th level convolutional interleaver may also start from sequence number 0. For example, the k-th level convolutional interleaver includes sub-channel 0, sub-channel 1, etc. In order to facilitate the explanation of the solution, in this application, the number of sub-channels included in the k-th stage convolutional interleaver may also start from sequence number 1.

Based on this, the output interleaving depth of the k-th stage convolutional interleaver is w _k ×p _k . The input interleaving depth of the k-th stage convolutional interleaver is w _k-1 ×p _k-1 . It can also be understood that the input interleaving depth of the subsequent convolutional interleaver is determined by the output interleaving depth of the previous convolutional interleaver. For example, the input interleaving depth of the second-level convolutional interleaver is equal to w ₁ × p ₁ , the input interleaving depth of the third-level convolutional interleaver is equal to w ₂ ×p ₂ ,…, the input interleaving depth of the x-th level convolutional interleaver is The depth is equal to w _x-1 ×p _x-1 . It should be noted that when k=1, the input interleaving depth of the first-stage convolutional interleaver is related to the coding method of the PCS layer and the symbol distribution method. Specifically, the coding method of the PCS layer includes two encoder encodings, such as encoder A and encoder B. The encoders are all RS(5440,5140,10) encoding, that is, the input of encoder A is 514 symbols and the output is 544 symbols. The input of encoder B is 514 symbols and the output is 544 symbols. The output symbols of encoder A and the output symbols of encoder B are distributed on z PCS channels in turn. It can also be understood that the 543rd symbol of encoder A is distributed to PCS channel 1, the 543rd symbol of encoder B is distributed to PCS channel 2; the 542nd symbol of encoder A is distributed to PCS channel 3, Distribute the 542nd symbol of encoder B to PCS channel 4; ... distribute the 543rd-(z/2) symbol of encoder A to PCS channel z-1, and distribute the 543rd-(z/2) symbol of encoder B to PCS channel z-1. 2) symbols are distributed to PCS channels z. Then distribute the 543-(z/2)-1 symbol of encoder B to PCS channel 1, and distribute the 543-(z/2)-1 symbol of encoder A to PCS channel 2; The 543-(z/2)-2 symbols of encoder B are distributed to PCS channel 1, and the 543-(z/2)-2 symbols of encoder A are distributed to PCS channel 2; the 543-(z/2)-2 symbols of encoder B are distributed to PCS channel 2; 543-(z/2)-(z/2) symbols are distributed to PCS channel z-1, and the 543-(z/2)-(z/2) symbols of encoder A are distributed to PCS channel z; then the input interleaving depth of the first-stage convolutional interleaver is Num_RS =2. Num_RS=2 indicates that the PCS layer includes 2 interleaving depths, or indicates that the PCS layer includes 1 interleaving depth and a lane permutation (Lane Permutation) operation is performed on the PMA layer or FEC layer.

Further, the input interleaving depth of the first convolutional interleaving module is the same as the input interleaving depth of the first convolutional interleaver. The output interleaving depth _of the first convolutional interleaving module is _w _x × _p The number of sub-channels included in the x-th level convolutional interleaver of the module. The output interleaving depth of the first convolutional interleaving module is the same as the output interleaving depth of the xth-level convolutional interleaver. It can also be understood that the input interleaving depth of the first-level convolutional interleaver is the interleaving depth input by the first convolutional interleaving module, and the output interleaving depth of the xth-level convolutional interleaver is the output interleaving depth of the first convolutional interleaving module. .

When k is a positive integer greater than 1 and less than or equal to x, the delay between the k-th stage convolutional interleaver and the first-stage convolutional interleaver satisfies the following formula 1:

Among them, w ₁ is the number of input symbols of the sub-channels of the first-level convolutional interleaver, p ₁ is the number of sub-channels included in the first-level convolutional interleaver, and Δ ₁ is the number of adjacent two sub-channels in the first-level convolutional interleaver. Delay between sub-channels.

Furthermore, the delay between the k-th stage convolutional interleaver and the first-stage convolutional interleaver satisfies the following formula 2:

Where, L is the number of symbols allocated to the PCS channel corresponding to the first convolutional interleaving module. Combined with the above-mentioned 800G-ETC mode, the number of symbols allocated to the PCS channel corresponding to the first convolutional interleaving module is 68, that is, L=68.

Two possible situations are further divided into two possible situations based on whether the number of sub-channels included in x-level convolutional interleaving is the same.

In case 1.1, the number of sub-channels of the x-level convolutional interleaver included in the first convolutional interleaving module is different.

In a possible implementation, the number of sub-channels of the first-stage convolutional interleaver of the first convolutional interleaving module is equal to the number of sub-channels of the first-stage convolutional interleaver except for the first convolutional interleaver. The number of sub-channels of the convolutional interleaver is different, and the number of sub-channels of the x-1 level convolutional interleaver included in the first convolutional interleaving module except the first convolutional interleaver is the same.

Exemplarily, the first-level convolutional interleaver includes 3 sub-channels (ie, p ₁ =3), and the x-1-level convolutional interleaver except the first-level convolutional interleaver includes 2 sub-channels (ie, p 1 =3). ₂ ～ _px =3). Specifically, the parameters of the first-level convolution interleaver include (w ₁ , 3, Δ ₁ , 2Δ ₁ ), the parameters of the second-level convolution interleaver include (w ₂ , 2, Δ ₂ ), and the parameters of the third-level convolution interleaver include The parameters of the product interleaver include (w ₃ , 2, Δ ₃ ), and by analogy, the parameters of the x-th stage convolution interleaver include (w _x , 2, Δ _x ).

The delay between the adjacent two-stage convolutional interleaver in the x-1th-stage convolutional interleaver except the first-stage convolutional interleaver in the first convolutional interleaving module satisfies the following formula 4:
Δ _k ＝2×Δ _k-1 ＝2 ^k-1 ×3×Δ _1Formula 4

Among them, _Δk is the delay of the k-th level interleaver, and Δk _-1 is the delay of the k-1-th level interleaver.

Combined with the above formula 4, the parameters of the first-level convolutional interleaver include (w ₁ , 3, Δ ₁ , 2Δ ₁ ), and the parameters of the second-level convolutional interleaver include (w ₂ , 2, Δ ₂ = 6×Δ ₁ ), the parameters of the third-level convolutional interleaver include (w ₃ , 2, Δ ₃ = 12 × Δ ₁ ), and by analogy, the parameters of the x-th level convolutional interleaver include (w _x , 2, Δ _x = 2 ^x-1 ×3×Δ ₁ ).

For example, L=68, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The delay between two adjacent sub-channels in the first-level convolutional interleaver is 24 symbols; and/or, the delay of the second-stage convolutional interleaver is 144 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The delay between two adjacent sub-channels in the first-level convolutional interleaver is 24 symbols; and/ Alternatively, the stage 2 convolutional interleaver has a delay of 120 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The delay between two adjacent sub-channels in the first-level convolutional interleaver is 26 symbols; and/ Or, the delay of the stage 2 convolutional interleaver is 130 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver; the delay between two adjacent sub-channels in the first-level convolutional interleaver is 26 symbols; and/ Or, the delay of the stage 2 convolutional interleaver is 156 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 24 symbols; and/or the delay of the stage 2 convolutional interleaver is 144 symbols; and/or the delay of the stage 2 convolutional interleaver is 288 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 36 symbols; and/or the delay of the stage 2 convolutional interleaver is 72 symbols; and/or the delay of the stage 3 convolutional interleaver is 144 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 24 symbols; and/or the delay of the stage 2 convolutional interleaver is 120 symbols; and/or the delay of the stage 3 convolutional interleaver is 216 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 26 symbols; and/or the delay of the stage 2 convolutional interleaver is 130 symbols; and/or the delay of the stage 3 convolutional interleaver is 234 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 24 symbols; and/or the delay of the stage 2 convolutional interleaver is 120 symbols; and/or the delay of the stage 3 convolutional interleaver is 240 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 26 symbols; and/or the delay of the stage 2 convolutional interleaver is 130 symbols; and/or the delay of the stage 3 convolutional interleaver is 260 symbols.

For example, L=136, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver; the delay between two adjacent sub-channels in the first-level convolutional interleaver is 46 symbols; and/or, the delay of the second-stage convolutional interleaver is 230 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver; the delay between two adjacent sub-channels in the first-level convolutional interleaver is 46 symbols; and/ Or, the delay of the stage 2 convolutional interleaver is 276 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 46 symbols; and/or the delay of the stage 2 convolutional interleaver is 230 symbols; and/or the delay of the stage 3 convolutional interleaver is 414 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 46 symbols; and/or the delay of the stage 2 convolutional interleaver is 276 symbols; and/or the delay of the stage 3 convolutional interleaver is 552 symbols. For another example, the first convolutional interleaving module includes the first-level convolutional interleaver, the second-level convolutional interleaver and the third-level convolutional interleaver. Interleaver; the delay between two adjacent sub-channels in the stage 1 convolutional interleaver is 48 symbols; and/or, the delay in the stage 2 convolutional interleaver is 240 symbols; and/or, the stage 3 The delay of the convolutional interleaver is 432 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 48 symbols; and/or the delay of the stage 2 convolutional interleaver is 288 symbols; and/or the delay of the stage 3 convolutional interleaver is 576 symbols.

Taking the first convolutional interleaving module including a three-level convolutional interleaver as an example, the configuration parameters of each level of convolutional interleaver are introduced.

Please refer to FIG. 9 , which is a schematic structural diagram of a first convolutional interleaving module provided in this application. In this example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver.

k=1, the parameters of the first-level convolutional interleaver include (w ₁ , p ₁ , Δ ₁ , 2Δ ₁ ), where w ₁ represents the number of input symbols of the sub-channel of the first-level convolutional interleaver, p ₁ Indicates the number of sub-channels of the first-level convolutional interleaver, _{and Δ1} indicates the delay between two adjacent sub-channels in the first-level convolutional interleaver. Combined with Figure 9, taking p ₁ =3 as an example, the first-level convolutional interleaver includes 3 sub-channels, w ₁ symbol is distributed to 3 sub-channels in a polling manner (for details, please refer to the relevant introduction above), and the delay of sub-channel 1 is 0 symbols, sub-channel 2 is delayed by Δ ₁ symbol, and sub-channel 3 is delayed by 2Δ ₁ symbol. The three sub-channels are then subjected to w ₁ symbol polling multiplexing processing as the output of the first-stage convolutional interleaver.

k=2, the parameters of the second-level convolutional interleaver include (w ₂ , p ₂ , Δ ₂ ), where w ₂ represents the number of symbols input by the sub-channel of the second-level convolutional interleaver, and p ₂ represents the second-level convolutional interleaver. The number of sub-channels of the first-level convolutional interleaver, _Δ2 represents the delay of the second-level convolutional interleaver. Combined with Figure 9, taking p ₂ =2 as an example, the first-level convolutional interleaver includes 2 sub-channels, w ₂ symbols are distributed to 2 sub-channels in a polling manner, sub-channel 1 is delayed by 0 symbols, and sub-channel 2 is delayed by Δ ₂ symbol. The two sub-channels are then subjected to w ₂ symbol polling multiplexing processing as the output of the second-stage convolutional interleaver.

k=3, the parameters of the third-level convolutional interleaver include (w ₃ , p ₃ , Δ ₃ ), where w ₃ represents the number of input symbols of the sub-channel of the third-level convolutional interleaver, and p ₃ represents the number of input symbols of the sub-channel of the third-level convolutional interleaver. The number of sub-channels of the first-level convolutional interleaver, _Δ3 represents the delay of the third-level convolutional interleaver. Combined with Figure 9, taking p ₃ =2 as an example, the first-level convolutional interleaver includes 2 sub-channels, w ₃ symbols are distributed to 2 sub-channels in a polling manner, sub-channel 1 is delayed by 0 symbols, and sub-channel 2 is delayed by Δ ₃ symbol. The two sub-channels are then subjected to w ₃ symbol polling multiplexing processing as the output of the third-level convolutional interleaver.

Please refer to Figure 10, taking Δ ₁ =24 as an example, the parameter configuration of the first-level convolution interleaver is (w ₁ , p ₁ , Δ ₁ , 2Δ ₁ ) = (2, 3, 24, 48), the first The output interleaving depth of the stage convolutional interleaver is w ₁ ×p ₁ =6. The parameter configuration of the second-stage convolutional interleaver is (w ₂ , p ₂ , Δ ₂ =6 × Δ ₁ ) = (6, 2, 144), and the output interleaving depth of the second-stage convolutional interleaver is w ₂ × p ₂ =12, the interleaving depth of the second-stage convolutional interleaver input is degree w ₁ ×p ₁ =6. The parameter configuration of the third convolutional interleaver is (12, 2, Δ ₃ =12×Δ ₁ )=(12, 2, 288), and the input interleaving depth of the third convolutional interleaver is w ₂ ×p ₂ =12 , the output interleaving depth of the third convolutional interleaver is w ₃ ×p ₃ =24.

It should be noted that the parameters of the second-level convolutional interleaver included in the first convolutional interleaving module can also be other possibilities. For example, the parameters of the first-level convolutional interleaver are configured as (w ₁ , p ₁ , Δ ₁ , 2Δ ₁ ) = (2, 3, 24, 48), and the parameter configuration of the second-stage convolutional interleaver is (w ₂ , p ₂ , Δ ₂ =5×Δ ₁ ) = (6, 2, 120).

In a possible implementation, the inner code encoder suitable for the first convolutional interleaving module shown in the above scenario 1.1 includes but is not limited to Hamming (128, 120) encoder.

In case 1.2, the number of input symbols of the sub-channels of the x-level convolutional interleaver included in the first convolutional interleaving module are all the same.

Exemplarily, each x-level convolutional interleaver includes 2 sub-channels. Specifically, the parameters of the first-level convolution interleaver include (w ₁ , 3, Δ ₁ ), the parameters of the second-level convolution interleaver include (w ₂ , 2, Δ ₂ ), and the parameters of the third-level convolution interleaver include The parameters of include (w ₃ , 2, Δ ₃ ), and so on, and the parameters of the x-th level convolutional interleaver include (w _x , 2, Δ _x ).

The delay of two adjacent stages of convolutional interleaver in x-stage convolutional interleaver satisfies the following formula 5:
Δ _k ＝2×Δ _k-1 ＝2 ^k-1 ×Δ _1Formula 5

Among them, Δk _-1 is the delay of the k-1th stage interleaver.

Based on this, each level of convolutional interleaver in the 2 times the delay of the convolutional interleaver. Combined with the above formula 5, the parameters of the first-level convolutional interleaver include (w ₁ , 3, Δ ₁ ), and the parameters of the second-level convolutional interleaver include (w ₂ , 2, Δ ₂ = 2×Δ ₁ ), The parameters of the third-level convolutional interleaver include (w ₃ , 2, Δ ₃ = 4 × Δ ₁ ), and by analogy, the parameters of the x-th level convolutional interleaver include (w _x , 2, Δ _x = 2 ^{x- 1} × _Δ1 ). It can also be understood that the delay of the first-level convolutional interleaver is Δ symbols, the delay of the second-level convolutional interleaver is 2×Δ symbols, and the delay of the third-level convolutional interleaver is 4×Δ symbols. , the delay length of the x-th stage convolutional interleaver is 2 ^(x-1) ×Δ symbols.

Exemplarily, L=68, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver, and the first convolutional interleaving module is one of the z convolutional interleaving modules. Any one; the delay between two adjacent sub-channels in the first-stage convolutional interleaver is 36 symbols; and/or the delay of the second-stage convolutional interleaver is 72 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver; the delay between two adjacent sub-channels in the first-level convolutional interleaver is 34 symbols; and/or , the delay of the level 2 convolutional interleaver is 68 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver; the delay between two adjacent sub-channels in the first-level convolutional interleaver is 38 symbols; and/or , the delay of the level 2 convolutional interleaver is 76 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 34 symbols; and/or the delay of the stage 2 convolutional interleaver is 68 symbols; and/or the delay of the stage 3 convolutional interleaver is 136 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels The delay is 68 symbols; and/or the delay of the stage 2 convolutional interleaver is 136 symbols; and/or the delay of the stage 3 convolutional interleaver is 272 symbols. For another example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver and a third-level convolutional interleaver; the first-level convolutional interleaver between two adjacent sub-channels A delay of 70 symbols; and/or a delay of 140 symbols for the stage 2 convolutional interleaver; and/or a delay of 280 symbols for the stage 3 convolutional interleaver.

Exemplarily, L=136, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver and a third-level convolutional interleaver. The first convolutional interleaving module is z convolutions. Any of the interleaving modules; a delay of 72 symbols between two adjacent sub-channels in the level 1 convolutional interleaver; and/or, a delay of 144 symbols in the level 2 convolutional interleaver; and/or, The delay of the level 3 convolutional interleaver is 288 symbols.

Taking the first convolutional interleaving module including a 2-level convolutional interleaver as an example, the configuration parameters of each level of convolutional interleaver are introduced.

Please refer to Figure 11, which is a schematic structural diagram of another first convolutional interleaving module provided in this application. In this example, the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver. The first convolutional interleaver and the second convolutional interleaver both include two sub-channels as an example.

k=1, the parameters of the first-stage convolutional interleaver include (w ₁ , p ₁ , Δ ₁ ). For descriptions of w ₁ , p ₁ and Δ ₁ , please refer to the relevant introduction mentioned above and will not be repeated here. Combined with Figure 11, the first-stage convolutional interleaver includes 2 sub-channels, w ₁ symbol is distributed to 2 sub-channels in polling, sub-channel 1 is delayed by 0 symbols (that is, sub-channel 0 has no delay), and sub-channel 2 is delayed by Δ ₁ symbol. The two sub-channels are then subjected to w ₁ symbol polling multiplexing processing as the output of the first-stage convolutional interleaver.

k=2, the parameters of the second-stage convolutional interleaver include (w ₂ , p ₂ , Δ ₂ ). For descriptions of w ₂ , p ₂ , Δ ₂ , please refer to the above related introduction, and will not be repeated here. Combined with Figure 11, the first-stage convolutional interleaver includes 2 sub-channels, w ₂ symbols are distributed to 2 sub-channels in polling, sub-channel 1 is delayed by 0 symbols, and sub-channel 2 is delayed by Δ ₂ symbols. Then pair the 2 sub-channels Perform w ₂ symbol polling multiplexing processing as the output of the second-level convolutional interleaver.

Please refer to Figure 12, taking Δ ₁ =36 as an example, the parameter configuration of the first-level convolutional interleaver is (w ₁ , p ₁ , Δ ₁ ) = (2, 2, 36), the first-level convolutional interleaver The output interleaving depth is w ₁ ×p ₁ =4. The parameter configuration of the second-stage convolutional interleaver is (w ₂ , p ₂ , Δ ₂ =2 × Δ ₁ ) = (4, 2, 72), and the output interleaving depth of the second-stage convolutional interleaver is w ₂ × p ₂ =12, the interleaving depth of the second-stage convolutional interleaver input is degree w ₁ ×p ₁ =4.

For another example, the parameter configuration of the first-level convolutional interleaver is (w ₁ , p ₁ , Δ ₁ ) = (2, 2, 36), and the parameter configuration of the second-level convolutional interleaver is (w ₂ , p ₂ , Δ ₂ =2 × Δ ₁ ) = (4, 2, 72), and the parameter configuration of the third-stage convolutional interleaver is (w ₃ , p ₃ , Δ ₃ ) = (8, 2, 144).

In a possible implementation, the inner code encoder applicable to the first convolutional interleaving module shown in the above scenario 1.1 includes but is not limited to a Hamming (170,160) encoder or a Hamming (180,170) encoder.

Case 2: The number of input symbols of the sub-channel of the k-th stage convolutional interleaver is greater than the number of output symbols of the sub-channel of the k-th stage convolutional interleaver.

Further, optionally, the number of input symbols of the sub-channels of the x-level convolutional interleaver included in the first convolutional interleaving module are all the same, and the output symbols of the subchannels of the x-level convolutional interleaver included in the first convolutional interleaving module are The numbers are all the same. In order to facilitate the explanation of the solution, the number of input symbols of the sub-channel of the convolutional interleaver is represented by w, and the number of output symbols of the sub-channel of the convolutional interleaver is represented by y. w>y.

It can also be understood that the input slice data block size on the corresponding sub-channel is larger than the output slice data block size. For example, the input slice data block of the first-level interleaver sub-channel is w ₁ symbol, and the output slice data block is y ₁ symbol; the input slice data block of the second-level interleaver sub-channel is w ₂ symbols, and the output slice data block is w 2 symbols. is y ₂ symbols; the input slice data block of the third-level interleaver sub-channel is w ₃ symbols, and the output slice data block is y ₃ symbols; and so on, the input slice data block of the x-level interleaver sub-channel is w _x symbols, the output slice data block is y _x symbols.

Please refer to Figure 13, which is a schematic structural diagram of another first convolutional interleaving module provided by the present application. In this example, the first convolutional interleaving module includes a first-level convolutional interleaver, a second-level convolutional interleaver, and a third-level convolutional interleaver. Each level of convolutional interleaver includes 2 sub-channels. example. The number of input symbols of the sub-channels of the first-level convolutional interleaver, the second-level convolutional interleaver and the third-level convolutional interleaver is w. The first-level convolutional interleaver, the second-level convolutional interleaver and the third-level convolutional interleaver are all w. The number of input symbols of the sub-channels of the 3-level convolutional interleaver is all y, and w is greater than y.

The parameters of the k-th stage convolution interleaver include (w _k , p _k , Δ _k , y _k ), where w _k represents the number of input symbols of the sub-channel of the k-th stage convolution interleaver, and p _k represents the k-th stage The number of sub-channels included in the convolution interleaver, Δ _k represents the delay of the k-th stage convolution interleaver, and y _k represents the number of output symbols of the sub-channels of the k-th stage convolution interleaver. Please refer to Figure 14. Taking the k-th level convolutional interleaver as an example including 2 sub-channels (sub-channel 1 and sub-channel 2 respectively), the field abababab inputs the k-th level convolutional interleaver, a comes from the code word A, and b comes from the code word Word B. The number of symbols input to the sub-channel of the k-th stage convolutional interleaver is w _k =4, and w _k symbols are distributed to p _k sub-channels in a polling manner. Specifically, the distribution time of sub-channel 1 is T ₁ =2×t, and the distribution time of sub-channel 2 is T ₂ =2×t+1, and t is an integer. It can also be understood that at time 0, w _k symbols are distributed to sub-channel 1, and sub-channel 1 outputs y _k symbols; at time 1, w _k symbols are distributed to sub-channel 2, and sub-channel 2 outputs y _k symbols. ; At the 2nd moment, w _k symbols are distributed to sub-channel 1, and sub-channel 1 outputs y _k symbols; at the 3rd moment, w _k symbols are distributed to sub-channel 2, and sub-channel 2 outputs y _k symbols; at the 4th moment Distribute w _k symbols to sub-channel 1, and sub-channel 1 outputs y _k symbols; at time 5, w _k symbols are distributed to sub-channel 2, and sub-channel 2 outputs y _k symbols; and so on. The delay of sub-channel 1 is 0 symbols and the delay of sub-channel 1 is Δ _k symbols.

Based on this, the input interleaving depth of the first convolutional interleaving module is related to the coding method of the PCS layer and the symbol distribution method. For related information, please refer to the relevant introduction mentioned above and will not be repeated here. The output interleaving depth of the first convolutional interleaving module is interleaving depth × p ₁ ×...p _x-1 ×p _x , where p ₁ is the number of sub-channels included in the first-stage interleaver of the first convolutional interleaving module, p _{x -1} is the number of sub-channels included in the x-1th level convolution interleaver of the first convolution interleaving module, and p _x is the number of sub-channels included in the x-th level convolution interleaver of the first convolution interleaving module. It should be noted that the input interleaving depth of the first convolutional interleaver is the same as the input interleaving depth of the first convolutional interleaving module.

In a possible implementation, the number of input symbols of the sub-channels of the x-level convolutional interleaver can be obtained based on the number of sub-channels of the x-level convolutional interleaver and the maximum interleaving depth output by the first convolutional interleaving module. . Among them, the maximum interleaving depth output by the first convolutional interleaving module is equal to the maximum interleaving depth required by the inner code encoder. The maximum interleaving depth required by the inner code encoder can be found in the relevant introduction mentioned above and will not be described again here.

Exemplarily, the number of input symbols of the sub-channels of the x-level convolutional interleaver is equal to the maximum interleaving depth of the output of the first convolutional interleaving module divided by the number of sub-channels of the x-th level convolutional interleaver. For example, the inner code encoder is Extended Hamming (128, 120) encoding, and the maximum interleaving depth required by the inner code encoder is 120/10 = 12, which means that the maximum interleaving depth output by the first convolutional interleaving module is equal to 12. Further, x The number of input symbols w of the sub-channels of the x-level convolutional interleaver is equal to the maximum interleaving depth 12 of the output of the first convolutional interleaving module divided by the number of sub-channels of the x-th level convolutional interleaver 2, that is, the The number of input symbols of the sub-channel w=6.

In a possible implementation, the number of output symbols of the sub-channels of the x-level convolutional interleaver is obtained according to the interleaving depth input by the first convolutional interleaving module.

Exemplarily, the number of output symbols of the sub-channels of the x-level convolutional interleaver is equal to the interleaving depth input by the first convolutional interleaving module; or the number of output symbols of the sub-channels of the x-level convolutional interleaver is equal to the first convolutional interleaving module. 1/2 times the input interleaving depth; or the number of output symbols of the sub-channels of the x-level convolutional interleaver is equal to 1/4 times the input interleaving depth of the first convolutional interleaving module, etc. For example, the interleaving depth input by the first convolutional interleaving module is Num_RS=2, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is y=2, or y=1.

The following example shows a specific example of the parameters of the first convolutional interleaving module based on scenario 2.

Exemplary A, x=2, w ₁ =w ₂ =4, y ₁ =y ₂ =1, Num_RS=2.

In this example, the first convolutional interleaving module includes a 2-level convolutional interleaver (x=2), which are a 1st-level convolutional interleaver and a 2nd-level convolutional interleaver respectively. Specifically, the four parameters of the first-level convolutional interleaver (w ₁ , p ₁ , Δ ₁ , y ₁ ) = (4, 2, Δ, 1), and the output interleaving depth of the first-level convolutional interleaver is Num_RS×p ₁ =2×2=4; the four parameters of the second-level convolution interleaving (w ₂ , p ₂ , Δ ₂ , y ₂ )=(4, 2, 2×Δ, 1), the second level The output interleaving depth of the convolutional interleaver is Num_RS×p ₁ ×p ₂ =2×2×2=8.

As shown in Figure 15, the first field input to the first-level convolutional interleaver is 8 symbols, coming from codeword A and codeword B. The distribution pattern of the 8 symbols is abababab, every 4 (that is, w ₁ = w ₂ =4) symbols are distributed in polling on sub-channel 1 and sub-channel 2. The 4 symbols allocated to sub-channel 1 are abab, and the 4 symbols allocated to sub-channel 2 are also abab. The data stream of sub-channel 2 undergoes a delay greater than L/2 symbols to ensure that the output symbols of sub-channel 2 are the symbols of the second field, that is, cdcd. Then the first field and the second field on the two sub-channels of sub-channel 1 and sub-channel 2 are cyclically multiplexed and output with 1 (i.e. y ₁ = y ₂ = 1) symbols. In other words, the first-stage convolutional interleaver output The field is acbdacbd.

Exemplary B, x=2, w ₁ =w ₂ =4, y ₁ =y ₂ =2, Num_RS=2.

In this example, the first convolutional interleaving module includes a 2-level convolutional interleaver (x=2), which are a 1st-level convolutional interleaver and a 2nd-level convolutional interleaver respectively. Specifically, the four parameters of the first-level convolutional interleaver (w ₁ , p ₁ , Δ ₁ , y ₁ ) = (4, 2, Δ, 2), and the output interleaving depth of the first-level convolutional interleaver is Num_RS×p ₁ =2×2=4; Level 2 convolution The four parameters of the interleaver (w ₂ , p ₂ , Δ ₂ , y ₂ ) = (4, 2, 2 × Δ, 2), the output interleaving depth of the second-stage convolutional interleaver is Num_RS × p ₁ × p ₂ =2×2×2=8.

As shown in Figure 16, the first field input to the first-level convolutional interleaver is 8 symbols, coming from codeword A and codeword B. The distribution pattern of the 8 symbols is abababab, every 4 (that is, w ₁ = w ₂ =4) symbols are distributed in polling on sub-channel 1 and sub-channel 2. The 4 symbols allocated to sub-channel 1 are abab, and the 4 symbols allocated to sub-channel 2 are also abab. The data stream of sub-channel 2 undergoes a delay greater than L/2 symbols to ensure that the output symbols of sub-channel 2 are the symbols of the second field, that is, cdcd. Then the first field and the second field on the two sub-channels of sub-channel 1 and sub-channel 2 are multiplexed and output in a round-robin manner with 2 (i.e. y ₁ = y ₂ = 2) symbols. In other words, the first-stage convolutional interleaver output The field is abefcdgh.

Exemplary C, x=2, w ₁ =w ₂ =8, y ₁ =y ₂ =1, Num_RS=4.

In this example, the first convolutional interleaving module includes a 2-level convolutional interleaver (x=2), which are a 1st-level convolutional interleaver and a 2nd-level convolutional interleaver respectively. Specifically, the four parameters of the first-level convolutional interleaving (w ₁ , p ₁ , Δ ₁ , y ₁ ) = (8, 2, 2 × Δ, 2), the output interleaving depth of the first-level convolutional interleaver is Num_RS×p ₁ =4×2=8; the four parameters of the second-level convolutional interleaver (w ₂ , p ₂ , Δ ₂ , y ₂ )=(8, 2, 4×Δ, 2), the The output interleaving depth of the 2-stage convolutional interleaver is Num_RS×p ₁ ×p ₂ =4×2×2=16.

As shown in Figure 17, the first field input to the first-level convolutional interleaver is 16 symbols, which come from codeword A, codeword B, codeword C and codeword D. The symbols of RS codeword A are symbol a, The symbol of RS codeword B is symbol b, the symbol of RS codeword C is symbol c, and the symbol of RS codeword D is symbol d. Four RS codewords are defined as a group, and the symbols of a group of RS codewords are allocated to each PCS channel. The total symbol length is L. The distribution mode of 16 symbols is abcdabcdabcdabcd, and every 8 (that is, w ₁ =w ₂ =8) symbols are distributed in subchannel 1 and subchannel 2 in a polling manner. The 8 symbols allocated by sub-channel 1 are abcdabcd, and the 8 symbols allocated by sub-channel 2 are also abcdabcd. The data stream of sub-channel 2 undergoes a delay greater than L/2 symbols to ensure that the output symbol of sub-channel 2 is the symbol of the second field, that is, efghefgh. Then the first field and the second field on the two sub-channels of sub-channel 1 and sub-channel 2 are cyclically multiplexed and output with 1 (i.e. y ₁ = y ₂ = 1) symbols. In other words, the first-stage convolutional interleaver output The field is aiejbkflcmgndohp.

Exemplary D, x=2, w ₁ =w ₂ =6, y ₁ =y ₂ =2, Num_RS=2.

In this example, the first convolutional interleaving module includes a 2-level convolutional interleaver (x=2), which are a 1st-level convolutional interleaver and a 2nd-level convolutional interleaver respectively. Specifically, the four parameters of the first-level convolutional interleaver (w ₁ , p ₁ , Δ ₁ , y ₁ ) = (6, 3, Δ, 2), and the output interleaving depth of the first-level convolutional interleaver is Num_RS×p ₁ =2×3=6; the four parameters of the second level (w ₂ , p ₂ , Δ ₂ , y ₂ ) = (6, 2, 2×Δ, 2), the interleaving of the second level output The depth is Num_RS×p ₁ ×p ₂ =2×3×2=12.

As shown in Figure 18, the first field input to the first-level convolutional interleaver is 12 symbols, coming from codeword A and codeword B. The distribution pattern of the 12 symbols is ababababababab. Every 6 (that is, w ₁ =w ₂ =6) symbols in the first-stage convolutional interleaver are distributed in sub-channel 1, sub-channel 2 and sub-channel 3. The 6 symbols allocated by sub-channel 1 are ababab, and the 6 symbols allocated by sub-channel 2 are also ababab. The data stream of sub-channel 2 undergoes a delay greater than L/2 symbols to ensure that the output symbols of sub-channel 2 are the symbols of the second field, that is, cdcdcd. Then the first field and the second field on the two sub-channels of sub-channel 1 and sub-channel 2 are multiplexed and output in a round-robin manner with 2 (i.e. y ₁ = y ₂ = 2) symbols. In other words, the first-stage convolutional interleaver output The field is abcdefabcdef.

Example D, x=3, w ₁ =w ₂ =w ₃ =8, y ₁ =y ₂ =y ₃ =1, Num_RS=2.

In this example, the first convolutional interleaving module takes a cascaded three-level convolutional interleaver (x=3) as an example, which are the first-level convolutional interleaver, the second-level convolutional interleaver and the third-level convolutional interleaver. product interleaver. Specifically, the four parameters of the first-level convolutional interleaver (w ₁ , p ₁ , Δ ₁ , y ₁ ) = (8, 2, Δ, 1), and the output interleaving depth of the first-level convolutional interleaver is Num_RS×p ₁ =2×2=4; the four parameters of the second-stage convolutional interleaver (w ₂ , p ₂ , Δ ₂ , y ₂ )=(8, 2, 2×Δ, 1), The output interleaving depth of the second-level convolutional interleaver is Num_RS×p ₁ ×p ₂ =2×2×2=8; the four parameters of the third-level convolutional interleaver (w ₃ , p ₃ , Δ ₃ , y ₃ )=(8, 2, 4×Δ, 1), the output interleaving depth of the third-stage convolutional interleaver is Num_RS×p ₁ ×p ₂ ×p ₃ =2×2×2×2=16.

Example E, x=3, w ₁ =w ₂ =w ₃ =8, y ₁ =y ₂ =y ₃ =2, Num_RS=2.

In this example, the first convolutional interleaving module takes a cascaded three-level convolutional interleaver (x=3) as an example, which are the first-level convolutional interleaver, the second-level convolutional interleaver and the third-level convolutional interleaver. product interleaver. Specifically, the four parameters of the first-level convolutional interleaver (w ₁ , p ₁ , Δ ₁ , y ₁ ) = (8, 2, Δ, 2), and the output interleaving depth of the first-level convolutional interleaver is Num_RS×p ₁ =2×2=4; the four parameters of the second-level convolution interleaver (w ₂ , p ₂ , Δ ₂ , y ₂ )=(8, 2, 2×Δ, 2), the first The output interleaving depth of the first-level convolutional interleaver is Num_RS×p ₁ ×p ₂ =8; the four parameters of the third-level convolutional interleaver (w ₃ , p ₃ , Δ ₃ , y ₃ ) = (8, 2, 4×Δ, 2), the output interleaving depth of the third-stage convolutional interleaver is Num_RS×p ₁ ×p ₂ ×p ₃ =2×2×2×2=16.

It should be noted that the number of sub-channels included in each stage of the x-level convolution interleaver may also be 3 or include more sub-channels.

Example F, x=3, w ₁ =w ₂ =w ₃ =4, y ₁ =y ₂ =y ₃ =1, Num_RS=1.

In this example, the first convolutional interleaving module takes a cascaded three-level convolutional interleaver (x=3) as an example, which are the first-level convolutional interleaver, the second-level convolutional interleaver and the third-level convolutional interleaver. product interleaver. The four parameters of the first-level convolutional interleaving (w ₁ , p ₁ , Δ ₁ , y ₁ ) = (4, 2, Δ/2, 1), the interleaving depth of the first-level convolutional interleaving output is Num_RS×p ₁ = 1 × 2 = 2; the four parameters of the second-level convolutional interleaving (w ₂ , p ₂ , Δ ₂ , y ₂ ) = (4, 2, Δ, 1), the second convolutional interleaving stage output The interleaving depth is Num_RS×p ₁ ×p ₂ =1×2×2=4; the four parameters of the third-level convolutional interleaving (w ₃ , p ₃ , Δ ₃ , y ₃ )=(4, 2, 2× Δ, 1), the interleaving depth of the third-level convolutional interleaving output is Num_RS×p ₁ ×p ₂ ×p ₃ =1×2×2×2=8.

In a possible implementation, the data transmission device may further include a mapping module. Among them, the mapping module is used to perform mapping processing on the data encoded by the inner encoding module, and the processing granularity can be 1 bit, 2 bits, 4 bits, or 8 bits, etc.

In the various embodiments of this application, if there is no special explanation or logical conflict, the terms and/or descriptions between different embodiments are consistent and can be referenced to each other. The technical features in different embodiments are based on their inherent Logical relationships can be combined to form new embodiments.

In this application, "plurality" means two or more. "And/or" describes the association of associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. In the text description of this application, the character "/" generally indicates that the related objects are in an "or" relationship. In the formula of this application, the character "/" indicates that the related objects are in a "division" relationship. In addition, in this application, the word "exemplary" is used to mean an example, illustration, or illustration. Any embodiment or design described herein as "example" is not intended to be construed as preferred or advantageous over other embodiments or designs. Alternatively, it can be understood that the use of the word "example" is intended to present concepts in a specific manner and does not constitute a limitation on this application.

It can be understood that the various numerical numbers involved in this application are only for convenience of description and are not used to limit the scope of the embodiments of this application. The size of the serial numbers of the above processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic. The terms "first", "second" and other similar expressions are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover a non-exclusive inclusion, for example, the inclusion of a series of steps or units. A method, system, product or apparatus need not be limited to those steps or elements expressly listed but may include those not expressly listed or other steps or units inherent to such processes, methods, products or devices.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, and all of them should be covered. within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A data transmission device, characterized in that it includes z physical coding sub-layer PCS channels and z convolution interleave modules, one convolution interleave module corresponds to one PCS channel, and the convolution interleave module includes cascaded x-level convolutions Product interleaver, the x is an integer greater than 1, and the z is a positive integer;

The PCS channel is used to receive the first data stream from the PCS layer, and one first data stream corresponds to one PCS channel;

The convolution interleaving module is used to interleave the first data stream from the corresponding PCS channel to obtain a second data stream. The interleaving depth of the second data stream is related to the input bit number of the inner code encoder.
The device according to claim 1, characterized in that the convolutional interleaving module is specifically used for:

Perform interleaving processing on the first data stream from the corresponding PCS channel according to the received indication signal;

The indication signal is used to indicate bypassing at least one stage of the convolutional interleaver in the z convolutional interleaving modules; or,

The indication signal is used to indicate to bypass the jth-level convolutional interleaver in the ith convolutional interleaving module among the z convolutional interleaving modules, where the i is an integer less than z, and the j is less than x is an integer.
The device of claim 2, wherein the device further includes a management data input and output MDIO interface, and the indication signal includes the value of the MDIO control bit;

The MDIO interface is configured to receive first information. The first information includes the value of the control variable of the MDIO. The MDIO control variable is mapped to the control variable of the x-level convolutional interleaver.
The device of claim 2, wherein the device further includes an attachment unit interface AUI, and the indication signal includes a first preset sequence or a second preset sequence;

The AUI is used to receive an alignment mark AM sequence from the corresponding PCS channel, where the AM sequence includes the first preset sequence; or, to receive the second alignment mark sequence from the corresponding PCS channel. Preset sequence.
The device according to any one of claims 1 to 4, characterized in that the number of input symbols of the sub-channels of the k-th stage convolutional interleaver is equal to the number of output symbols of the sub-channels of the k-th stage convolutional interleaver, The kth-level convolutional interleaver is any one of the x convolutional interleavers in the first convolutional interleaving module, and the first convolutional interleaving module is any one of the z convolutional interleaving modules. , the k is a positive integer less than or equal to x.
The device according to claim 5, wherein the input interleaving depth of the first convolutional interleaving module is related to the coding method and symbol distribution method of the PCS layer;

The output interleaving depth of the first convolutional interleaving module is w x ×p x ;

Wherein, w x is the number of symbols of the sub-channel input by the x-th level convolution interleaver of the first convolution interleaving module, and p The number of sub-channels included in the interleaver.
The device according to claim 6, wherein k is a positive integer greater than 1 and less than or equal to x, and the input interleaving depth of the k-th stage convolutional interleaver is w k-1 ×p k-1 , the output interleaving depth of the k-th stage convolutional interleaver is w k ×p k ; wherein, the w k is the number of input symbols of the sub-channel of the k-th stage convolutional interleaver, and the p k is The number of sub-channels included in the k-th stage convolution interleaver, the w k-1 is the number of input symbols of the sub-channels of the k-1-th stage convolution interleaver, and the p k-1 is the The number of sub-channels included in the k-1th level convolutional interleaver;

The input interleaving depth of the first-stage convolutional interleaver of the first convolutional interleaving module is equal to the input interleaving depth of the first convolutional interleaving module.
The device according to any one of claims 1 to 7, characterized in that the first convolutional interleaving module includes an x-level convolution The number of sub-channels of the product interleaver is different, and the first convolution interleave module is any one of the z convolution interleave modules.
The device of claim 8, wherein the number of sub-channels of the first-stage convolutional interleaver included in the first convolutional interleaving module is the same as the number of sub-channels of the first-stage convolutional interleaver included in the first convolutional interleaving module. The x-1 level convolution interleaver other than a convolution interleaver has different sub-channel numbers. The first convolution interleaving module includes an x-1 level convolution interleaver other than the first convolution interleaver. The number of sub-channels is the same.
The device according to claim 8 or 9, characterized in that the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver, and the first convolutional interleaving module is the z Any one of the convolutional interleaving modules;

The delay between two adjacent sub-channels in the first-stage convolutional interleaver is 24 symbols; and/or,

The delay of the stage 2 convolutional interleaver is 120 symbols.
The device according to any one of claims 1 to 7, characterized in that the x-level convolution interleaver included in the first convolution interleaving module includes the same number of sub-channels, and the first convolution interleaving module is Any one of the z convolutional interleaved modules.
The device of claim 11, wherein the first convolutional interleaving module includes a first-level convolutional interleaver and a second-level convolutional interleaver, and the first convolutional interleaving module is the z convolutional interleaver. Any one of the product interleaving modules;

The delay between two adjacent sub-channels in the first-stage convolutional interleaver is 36 symbols; and/or,

The delay of the stage 2 convolutional interleaver is 72 symbols; and/or,

The delay of the level 3 convolutional interleaver is 144 symbols.
The device according to any one of claims 1 to 4, characterized in that the number of input symbols of the sub-channels of the x-level convolutional interleaver included in the first convolutional interleaving module are all the same, and the first convolutional interleaving module The number of output symbols of the sub-channels of the x-level convolution interleaver is the same, and the number of input symbols of the sub-channel of the k-th level convolution interleaver is greater than the number of output symbols of the sub-channel of the k-th level convolution interleaver. ;

Wherein, the kth-level convolutional interleaver is any one of the x convolutional interleavers in the first convolutional interleaving module, and the first convolutional interleaving module is any one of the z convolutional interleaving modules. In any case, the k is a positive integer less than or equal to x.
The device of claim 13, wherein the input interleaving depth of the first convolutional interleaving module is related to the coding method and symbol distribution method of the PCS layer;

The output interleaving depth of the first convolution interleaving module is interleaving depth × p 1 ×...p x-1 × p x , and p 1 is the first-stage convolution interleaver of the first convolution interleaving module. The number of sub-channels, the p x-1 is the number of sub-channels included in the x-1th stage convolution interleaver of the first convolution interleaving module, and the p x is the The number of sub-channels included in the x-th level convolutional interleaver.
The device according to claim 13 or 14, wherein the number of input symbols of the sub-channels of the x-level convolution interleaver is based on the number of sub-channels of the Obtained from the maximum interleaving depth output by the interleaving module;

The number of output symbols of the sub-channels of the x-level convolutional interleaver is obtained according to the input interleaving depth of the first convolutional interleaving module.
The apparatus according to claim 15, wherein the number of input symbols of the sub-channels of the x-level convolution interleaver is equal to the maximum interleaving depth of the output of the first convolutional interleaving module divided by the x-th level The number of sub-channels of the convolutional interleaver;

The number of output symbols of the sub-channels of the x-level convolutional interleaver is equal to the input interleaving depth of the first convolutional interleaving module.
The device according to any one of claims 13 to 15, characterized in that the number of input symbols of the sub-channels of the x-level convolutional interleaver and the number of output symbols of the sub-channels of the x-level convolutional interleaver are Be any of the following:

The number of input symbols of the sub-channel of the x-level convolutional interleaver is 8, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is 2; or,

The number of input symbols of the sub-channel of the x-level convolutional interleaver is 6, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is 2; or,

The number of input symbols of the sub-channel of the x-level convolutional interleaver is 4, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is 2; or,

The number of input symbols of the sub-channel of the x-level convolutional interleaver is 8, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is 1; or,

The number of input symbols of the sub-channel of the x-level convolutional interleaver is 6, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is 1; or,

The number of input symbols of the sub-channel of the x-level convolutional interleaver is 4, and the number of output symbols of the sub-channel of the x-level convolutional interleaver is 1.