WO2023174428A1

WO2023174428A1 - On-chip optical diffraction computation processor and all-optical image classification device

Info

Publication number: WO2023174428A1
Application number: PCT/CN2023/082326
Authority: WO
Inventors: 戴琼海; 周天贶; 方璐; 吴嘉敏
Original assignee: 清华大学
Priority date: 2022-03-18
Filing date: 2023-03-17
Publication date: 2023-09-21
Also published as: CN114815961A

Abstract

The present application relates to an on-chip optical diffraction computation processor and an all-optical image classification device. The on-chip optical diffraction computation processor comprises: an input end, which is used for generating a one-dimensional input on the basis of incident light; a waveguide, which is coupled to the input end and is used for limiting a light field to a single mode perpendicular to a plane direction and propagating the light field in an in-plane direction; and at least one dielectric metasurface, wherein the at least one dielectric metasurface is composed of at least one metamaterial unit array and is used for performing amplitude and phase modulation on the light field during a diffraction propagation process, so as to obtain a computation result, thereby completing the computation of neuromorphic photons. In this way, a dielectric-metasurface-based on-chip diffraction processing unit for computing neuromorphic photons is realized, and all-optical image classification is proven by means of experiments; and the space occupied is small, and the light loss is also low.

Description

On-chip optical diffraction calculation processor and all-optical image classification equipment

Cross-references to related applications

This application is based on the Chinese patent application with application number 202210272092.3 and the filing date is March 18, 2022, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into this application as a reference.

Technical field

In recent years, photonic computing has attracted increasing research interest due to its high-speed and energy-efficient information processing capabilities. Integrated photonic circuits, supported by state-of-the-art nanofabrication technologies, are of particular interest as high-performance coprocessors for solving artificial intelligence tasks.

However, the large size of the optoelectronic modulator limits the computing scale of existing photonic computing chips. Although photonic metasurfaces composed of metamaterial unit arrays can achieve effective light field modulation, this has not been confirmed in related technologies.

Background technique

The present application relates to the technical field of integrated photonic circuits, and in particular to an on-chip optical diffraction calculation processor and all-optical image classification equipment.

Contents of the invention

This application provides an on-chip optical diffraction calculation processor and all-optical image classification equipment, realizes an on-chip diffraction processing unit based on dielectric metasurfaces for neuromorphic photon calculations, and proves through experiments that all-optical image classification not only takes up The space is small and the light loss is low.

The first embodiment of the present application provides an on-chip optical diffraction calculation processor, including:

The input terminal is used to generate one-dimensional input based on incident light;

A waveguide coupled to the input end is used to limit the light field to a single mode perpendicular to the plane direction and propagate in the in-plane direction; and

At least one dielectric metasurface, which is composed of at least one metamaterial unit array, is used to modulate the amplitude and phase of the light field during diffraction propagation, obtain calculation results, and complete the neuromorphic Photon calculations.

Optionally, also includes:

An output end includes first to second strip waveguides and corresponding vertical grating couplers for coupling the calculation results to the first to second strip waveguides.

Optionally, the output terminal also includes:

The first to second vertical grating couplers are used to guide the output results of the first to second strip waveguides to make binary decisions.

Optionally, the at least one dielectric metasurface is constructed from silicon dioxide trenches embedded in a device layer of the processor.

Optionally, the metamaterial unit size of the at least one metamaterial unit is 300 nm.

Optionally, the slit width of the at least one metamaterial unit is less than 100 nm, and the groove length is 400 nm.

Optionally, the at least one dielectric metasurface is multi-layered.

Optionally, the layer spacing between each layer of dielectric metasurface is 200um.

Optionally, the waveguide coupled to the input end is a silicon optical SOI (Silicon-On-Insulator, silicon on an insulating substrate) planar waveguide.

A second embodiment of the present application provides an all-optical image classification device, which includes the above-mentioned on-chip optical diffraction calculation processor.

As a result, an on-chip diffraction processing unit for neuromorphic photon computing based on dielectric metasurfaces was implemented, and all-optical image classification was experimentally demonstrated, which not only occupies a small space but also has low optical loss.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Description of the drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

Figure 1 is a block diagram of an on-chip optical diffraction calculation processor provided according to an embodiment of the present application;

Figure 2 is a schematic diagram of the basic principles of an on-chip optical diffraction calculation processor according to an embodiment of the present application;

Figure 3 is a schematic diagram of the angle-dependent modulation characteristics of a metamaterial unit according to an embodiment of the present application;

Figure 4 is an example diagram of wave optics simulation according to an embodiment of the present application;

Figure 5 is a schematic diagram of an SEM (Scanning Electron Microscope) image of a metasurface manufactured according to an embodiment of the present application;

Figure 6 is an example diagram of a test system using an on-chip DPU (Data Processing Unit, processor distributed processing unit) for image classification according to an embodiment of the present application;

Figure 7 is an example diagram of input and test results according to one embodiment of the present application;

Figure 8 is an example diagram of binary classification results of the entire binary classification data set according to an embodiment of the present application.

Detailed ways

The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present application, but should not be construed as limiting the present application.

The on-chip optical diffraction calculation processor and all-optical image classification device according to embodiments of the present application will be described below with reference to the accompanying drawings. In view of the problem mentioned by the background technology center that the large size of the optoelectronic modulator limits the computing scale of existing photonic computing chips, and it has not been proven that a photonic metasurface composed of a metamaterial unit array can achieve effective light field modulation, this application An on-chip optical diffraction calculation processor is provided, which implements an on-chip diffraction processing unit for neuromorphic photon calculations based on dielectric metasurfaces, and experimentally proves all-optical image classification, which not only occupies a small space, but also has low optical loss. .

Specifically, FIG. 1 is a schematic diagram of an on-chip optical diffraction calculation processor provided by an embodiment of the present application.

As shown in FIG. 1 , the on-chip optical diffraction calculation processor 10 includes: an input terminal 100 , a waveguide 200 and at least one dielectric metasurface 300 .

The input terminal 100 is used to generate a one-dimensional input based on incident light; the waveguide 200 is coupled to the input terminal 100 and is used to limit the light field to a single mode perpendicular to the plane direction and propagate in the in-plane direction; at least one medium The electric metasurface 300 is composed of at least one metamaterial unit array, and is used to modulate the amplitude and phase of the light field during the process of diffraction propagation, obtain calculation results, and complete the calculation of neuromorphic photons.

Optionally, in some embodiments, the metamaterial unit size of at least one metamaterial unit is 300 nm.

Optionally, in some embodiments, the slit width of at least one metamaterial unit is less than 100 nm and the groove length is 400 nm.

Optionally, in some embodiments, the above-mentioned on-chip optical diffraction calculation processor 10 also includes: an output end, which includes first to second strip waveguides and corresponding vertical grating couplers, for converting the calculation results to coupled into the first to second strip waveguides.

Optionally, in some embodiments, the output end further includes: first to second vertical grating couplers, used to guide the output results of the first to second strip waveguides to make binary decisions.

Optionally, in some embodiments, at least one dielectric metasurface 300 is constructed from silicon dioxide trenches embedded in the device layer of the processor.

Optionally, in some embodiments, at least one dielectric metasurface 300 is multi-layered.

Optionally, in some embodiments, the layer spacing between each layer of dielectric metasurface is 200um.

Optionally, in some embodiments, the waveguide coupled to the input end is a silicon optical SOI slab waveguide.

Specifically, embodiments of the present application can use one-dimensional (1D) dielectric metasurfaces to design and manufacture on-chip DPUs, as shown in Figure 2. Figure 2 is a schematic diagram of the basic principles of an on-chip optical diffraction calculation processor according to one embodiment of the present application. Incident light, encoding a one-dimensional input in its amplitude, is coupled end-to-end into a silicon photonic SOI slab waveguide, where the light field is constrained to a vertical plane Single mode in the direction and propagates unrestricted in the in-plane direction. During diffractive propagation through the learned metastructure region (i.e., the etched 1D metasurface), the light field is amplitude and phase modulated. After multi-layer modulation and propagation, the calculation results of the DPU are coupled into two strip waveguides and guided outward through corresponding vertical grating couplers for binary decision-making, where the higher light intensity of the strip waveguide determines the input category.

It should be noted that the one-dimensional metasurface is constructed by embedding silicon dioxide grooves in the device layer to form metamaterial units. The structure of the metamaterial unit is shown in Figure 2. In order to comply with the sub-wavelength period working conditions of metamaterials and the accuracy of electron beam lithography and silicon etching processes, the metamaterial unit size of at least one metamaterial unit is set to 300nm.

Further, through Finite Difference Time Domain (FDTD) simulation, embodiments of this application analyze the modulation characteristics of metamaterial units with different gap widths and incident light directions. In order to fully characterize the modulation characteristics, the embodiments of this application studied the modulation characteristics of transmitted light and reflected light.

As shown in Figure 3, enlarging the gap width will increase the phase modulation range, but will reduce the transmittance. In order to balance the modulation range and light efficiency, the embodiment of the present application selects the slit width to be less than 100 nm to keep the amplitude transmission coefficient greater than 90%. In addition, for the robustness of device manufacturing, embodiments of the present application design a DPU with binary modulation, that is, the gap width of the metamaterial unit is limited to 0 or 100 nm. To propagate the high accuracy of the modeling, the groove length was optimized and set to 400 nm. In the embodiment of this application, the DPU is designed to have five layers of metasurface, and the optimized layer spacing is 200um. Each metasurface layer contains 600 trainable parameters, for a total of 3000 parameters. The embodiment of this application trains three DPUs to perform binary classification of handwritten digits in the MNIST data set ("0" and "1", "1" and "6", and "1" and "7" respectively). Light propagation is formulated using Rayleigh-Sommerfeld diffraction (RSD) according to the modulation characteristics in Figure 3, and the DPU is trained using the gradient descent method. The highly matched phase and amplitude modulation curves between the FDTD and RSD models (shown in Figure 4) prove the accuracy of the DPU training process. Figure 5 shows a Scanning Electron Microscope (SEM) image of the partially fabricated meta-atom array, and Figure 5(b) is a partially enlarged schematic diagram of Figure (a).

Further, in order to test the on-chip DPU, the collimated 1550nm continuous wave laser beam is focused onto the Digital Micromirror Device (DMD) through the cylindrical lens line (as shown in Figure 6). Each handwritten image is resized to 100 pixels of 1D and projected onto the DMD (as shown in Figure 7(a)), and then relayed to the input port of the silicon chip by the 20x imaging system. Apply piezoelectric stage alignment to align the input optical signal to the SOI chip. A top-looking infrared camera receives the calculation results. As a test example shown in Figure 7, the input image is "7" (Figure 7(a)). Due to the scattering of light, the output infrared image of the camera shows a five-layer 1D metasurface, matching the overlapping device structure. (Figure 7(b)). Furthermore, the vast majority of light is emitted from the output grating on the upper side, which represents the correct "7" category. The embodiment of this application further tested the entire MNIST test data set of three DPUs. The experimental accuracies of the three DPUs are 77.27%, 87.91% and 96.05% respectively (as shown in ① in Figure 8(a)-Figure 8(c)), and the comparative simulation accuracies are 95.64%, 93.64% and 98.41% respectively, ( As shown in ② in Figure 8(a)-Figure 8(c)).

In the experiment, the input power of the optical chip was about 2mW and the output power was about 5nW. The relatively high insertion loss results from the input and output coupling processes of the on-chip waveguide. Simulations show that the current end-to-end input coupling scheme has a coupling efficiency of approximately 10%. Coupling efficiency can be improved through more advanced and optimized coupling strategies. In addition, the performance of the DPU chip is verified through an infrared camera. The maximum operating speed is limited to about 100 frames per second, and the speed can be further increased by using high-speed photodiodes. Coupling efficiency can be improved through more advanced technologies and optimized coupling strategies. 1D metasurfaces can also be programmed at high speeds.

The on-chip DPU in this work is designed with 3000 parameters and 100 input nodes. DPU scale can be easily achieved by using more meta atoms and layers. Numerical evaluation shows that under the same configuration, the classification accuracy of the complete 10-category MNIST handwritten digits reaches 92.7% and 89.7%, respectively, with 36k grayscale and binary parameters (shown in Table 1). In comparison, using the on-chip photon calculation method of the Mach-Zehnder Interferometer (MZI), the 40×40 and 128×128MZI contain 3.2k and 32.7k parameters respectively, binary (“1” and “7”) and 10-category MNIST respectively. Able to achieve 97.6% and 88.3% accuracy. Furthermore, the number of parameters on this chip-scale platform is reduced by an order of magnitude compared to free-space diffraction neural networks to achieve similar performance.

Table 1

In summary, the embodiments of this application have experimentally proven the ability of the on-chip DPU to be used for all-optical image classification, and predicted its application in large-scale high-performance photon computing.

According to the on-chip optical diffraction calculation processor proposed in the embodiment of the present application, an on-chip diffraction processing unit for neuromorphic photon calculation based on dielectric metasurface is implemented, and the all-optical image classification is proved through experiments, which not only takes up a small space, but also Low optical loss.

In addition, an embodiment of the present application also proposes an all-optical image classification device, which includes an on-chip optical diffraction calculation processor shown in the embodiment of FIG. 1 .

According to the all-optical image classification device proposed in the embodiment of the present application, through the above-mentioned on-chip optical diffraction calculation processor, an on-chip diffraction processing unit based on dielectric metasurface for neuromorphic photon calculation is realized, and the all-optical Image classification not only takes up a small space, but also has low light loss.

In the description of this specification, reference to the terms "one embodiment,""someembodiments,""anexample,""specificexamples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structure, material Materials or features are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically limited.

Any process or method descriptions in flowcharts or otherwise described herein may be understood to represent modules, segments, or portions of code that include one or more executable instructions for implementing customized logical functions or steps of the process. , and the scope of the preferred embodiments of the present application includes additional implementations in which functions may be performed out of the order shown or discussed, including in a substantially simultaneous manner or in the reverse order, depending on the functionality involved, which shall It should be understood by those skilled in the technical field to which the embodiments of this application belong.

The logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered a sequenced list of executable instructions for implementing the logical functions, and may be embodied in any computer-readable medium, For use by, or in combination with, instruction execution systems, devices or devices (such as computer-based systems, systems including processors or other systems that can fetch instructions from and execute instructions from the instruction execution system, device or device) or equipment. For the purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer readable media include the following: electrical connections with one or N wires (electronic device), portable computer disk cartridge (magnetic device), random access memory (RAM), Read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium may even be paper or other suitable medium on which the program may be printed, as the paper or other medium may be optically scanned, for example, and subsequently edited, interpreted, or otherwise suitable as necessary. process to obtain the program electronically and then store it in computer memory.

It should be understood that various parts of the present application can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods may be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if it is implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: discrete logic gate circuits with logic functions for implementing data signals; Logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGA), field-programmable Programming gate array (FPGA), etc.

Those of ordinary skill in the art can understand that all or part of the steps involved in implementing the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. The program can be stored in a computer-readable storage medium. When executed, one of the steps of the method embodiment or a combination thereof is included.

In addition, each functional unit in various embodiments of the present application can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software function modules. If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

The storage media mentioned above can be read-only memory, magnetic disks or optical disks, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above-mentioned embodiments are illustrative and cannot be understood as limitations of the present application. Those of ordinary skill in the art can make modifications to the above-mentioned embodiments within the scope of the present application. The embodiments are subject to changes, modifications, substitutions and variations.

Claims

An on-chip optical diffraction calculation processor, characterized by including:

The input terminal is used to generate one-dimensional input based on incident light;

A waveguide coupled to the input end is used to limit the light field to a single mode perpendicular to the plane direction and propagate in the in-plane direction; and

At least one dielectric metasurface, which is composed of at least one metamaterial unit array, is used to modulate the amplitude and phase of the light field during diffraction propagation, obtain calculation results, and complete the neuromorphic Photon calculations.
The processor of claim 1, further comprising:

An output end includes first to second strip waveguides and corresponding vertical grating couplers for coupling the calculation results to the first to second strip waveguides.
The processor according to claim 1, wherein the output terminal further includes:

The first to second vertical grating couplers are used to guide the output results of the first to second strip waveguides to make binary decisions.
The processor of claim 1, wherein the at least one dielectric metasurface is constructed by embedding silicon dioxide trenches in a device layer of the processor.
The processor according to claim 4, wherein the metamaterial unit size of the at least one metamaterial unit is 300 nm.
The processor according to claim 1 or 4, wherein the slit width of the at least one metamaterial unit is less than 100 nm, and the groove length is 400 nm.
The processor according to any one of claims 1-6, wherein the at least one dielectric metasurface is multi-layered.
The processor according to claim 7, wherein the layer spacing between each layer of dielectric metasurface is 200um.
The processor according to claim 1, wherein the waveguide coupled to the input terminal is a silicon optical SOI planar waveguide.
An all-optical image classification device, characterized by comprising: the on-chip optical diffraction calculation processor according to any one of claims 1-9.