WO2023165059A1

WO2023165059A1 - Scoreboard implementation method and apparatus, scoreboard, electronic device, and storage medium

Info

Publication number: WO2023165059A1
Application number: PCT/CN2022/101759
Authority: WO
Inventors: 金鑫
Original assignee: 北京百度网讯科技有限公司
Priority date: 2022-03-01
Filing date: 2022-06-28
Publication date: 2023-09-07
Also published as: CN114896114B; CN114896114A

Abstract

A scoreboard implementation method and apparatus, a scoreboard, an electronic device, and a storage medium, which relate to artificial intelligence fields such as artificial intelligence chips and intelligent speech. The method comprises: separately constructing M functional layers, where M is a positive integer greater than one, and different functional layers are respectively used for implementing different scoreboard functions (101); and using the M functional layers to form a scoreboard (102). The method is simple to implement and facilitates management and maintenance.

Description

Scoreboard realization method, device, scoreboard, electronic equipment and storage medium

This application claims the priority of the Chinese patent application whose application date is March 1, 2022, and whose application number is 202210195437.X.

technical field

The present disclosure relates to the technical field of artificial intelligence, and in particular to a scoreboard implementation method, device, scoreboard, electronic equipment, and storage medium in the fields of artificial intelligence chips and intelligent voice.

Background technique

The scoreboard (Scordboard) is a key component of chip verification. Its function is to compare whether the actual output data of the device under test (DUT, Device Under Test) is consistent with the theoretical result data, so as to verify the chip function. The chip can be an intelligent voice chip or the like.

Contents of the invention

The present disclosure provides a scoreboard realization method, device, scoreboard, electronic equipment and storage medium.

A method for implementing a scoreboard, comprising:

Construct M functional layers respectively, M is a positive integer greater than one, and different functional layers are used to realize different scoreboard functions;

The scoreboard is composed of the M functional layers.

A scoreboard implementation device, comprising: a first processing unit and a second processing unit;

The first processing unit is used to construct M functional layers respectively, where M is a positive integer greater than one, and different functional layers are respectively used to realize different scoreboard functions;

The second processing unit is configured to use the M functional layers to form the scoreboard.

A scoreboard includes: M functional layers, where M is a positive integer greater than one, and different functional layers are used to realize different functions of the scoreboard.

An electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can perform the method as described above.

A non-transitory computer-readable storage medium storing computer instructions, the computer instructions are used to cause a computer to execute the method as described above.

A computer program product, comprising computer programs/instructions, when executed by a processor, implements the method as described above.

An embodiment in the above disclosure has the following advantages or beneficial effects: the scoreboard is layered, that is, a layered design architecture is adopted, and the functions of each layer are clear and simple, easy to implement, and easy to manage and maintain.

It should be understood that what is described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood through the following description.

Description of drawings

The accompanying drawings are used to better understand the present solution, and do not constitute a limitation to the present disclosure. in:

FIG. 1 is a flow chart of an embodiment of a method for implementing a scoreboard described in the present disclosure;

FIG. 2 is a first schematic diagram of the composition structure of the scoreboard described in the present disclosure;

3 is a second schematic diagram of the composition structure of the scoreboard described in the present disclosure;

FIG. 4 is a schematic diagram of the composition and structure of an embodiment 400 of the scoreboard implementation device described in the present disclosure;

FIG. 5 is a schematic diagram of the composition and structure of the scoreboard embodiment 500 of the present disclosure;

FIG. 6 shows a schematic block diagram of an electronic device 600 that may be used to implement embodiments of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and they should be regarded as exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

In addition, it should be understood that the term "and/or" in this article is only an association relationship describing associated objects, which means that there may be three relationships, for example, A and/or B may mean: A exists alone, and A exists at the same time and B, there are three cases of B alone. In addition, the character "/" in this article generally indicates that the contextual objects are an "or" relationship.

FIG. 1 is a flow chart of an embodiment of a method for implementing a scoreboard in the present disclosure. As shown in FIG. 1 , the following specific implementation manners are included.

In step 101, M functional layers are respectively constructed, where M is a positive integer greater than one, and different functional layers are used to implement different scoreboard functions.

In step 102, the scoreboard is formed by using the M functional layers.

The current scoreboard usually adopts a single-layer design method, which is complex to implement and inconvenient to manage and maintain. In the scheme described in the above method embodiment, the scoreboard is hierarchically processed, that is, a layered design architecture is adopted. The functions of each level are clear and simple, easy to implement, and easy to manage and maintain.

In an embodiment of the present disclosure, the value of M may be 3, and accordingly, three different functional layers may be respectively: bottom layer (scoreboard_base), middle layer (scoreboard_proc) and top layer (scoreboard_top).

Among them, the bottom layer can be used to store the basic functions of the encapsulated scoreboard, the top layer can be used to realize the scheduling management of functional instructions, and the middle layer can be used to inherit the basic functions and complete the verification of the scheduled functional instructions.

Through the above method, the complex scoreboard function is decomposed, and different levels are used to realize different scoreboard functions. The level is clear and the division of labor is clear, easy to implement, easy to manage and maintain, and supports hierarchical nesting. Very flexible and convenient.

The specific implementation of each level is described below.

1) top layer

The top layer can be used to realize the scheduling management of functional instructions, that is, to complete the scheduling work of various functional instructions. Specifically, according to the information extracted from the bus, the functional instructions (including instructions and data, etc.) can be parsed out, and dispatched (that is, assigned) to The middle layer is processed.

In an embodiment of the present disclosure, the top layer may adopt a tree-structured level-by-level scheduling manner. For example, if the functional instruction is recognized as a complex instruction set (csic) instruction or a reduced instruction set (rsic) instruction, it can be assigned to the scoreboard_top_csic or scoreboard_top_rsic module for processing. Taking the scoreboard_top_csic instruction as an example, it can further identify whether it is a calculation instruction or a data transfer instructions etc.

Through the above method, the scheduling efficiency and scheduling effect of the functional instructions can be improved.

2) middle layer

The middle layer can be used to inherit the basic functions and complete the verification of the dispatched function instructions.

In an embodiment of the present disclosure, the middle layer may include N functional instruction verification modules, and N is a positive integer, that is, it may include only one functional instruction verification module, or may include multiple functional instruction verification modules. When N is greater than one, Different functional instruction verification modules can be respectively used to realize the verification of different types of functional instructions.

The specific value of N can be determined according to actual needs. FIG. 2 is a first schematic diagram of the composition structure of the scoreboard of the present disclosure. As shown in Figure 2, assuming that the value of N is 2, that is, the middle layer includes two functional instruction verification modules, and different functional instruction verification modules are used to verify different types of functional instructions, such as the functional instruction verification module a It is used to verify the functional instructions of type a, and the functional instruction verification module b is used to verify the functional instructions of type b, wherein the functional instructions of type a can be computing functional instructions, and the functional instructions of type b can be data moving functional instructions.

By setting multiple functional instruction verification modules, the division of labor between different modules can be realized, thereby improving verification efficiency.

In an embodiment of the present disclosure, for any function instruction verification module, it may include: a scheduling sub-module and P verification sub-modules, P is a positive integer greater than one, and the scheduling sub-module can be used to schedule the The functional instruction is parsed into at least two sub-instructions, and each sub-instruction can be dispatched to a corresponding verification sub-module. Correspondingly, the verification sub-module can be used to complete the verification of the dispatched sub-instructions.

The specific value of P can be determined according to actual needs. For example, for calculation-type functional instructions, there may be various calculation functions such as addition, subtraction, multiplication, and division. Correspondingly, it can be parsed into multiple sub-instructions by using the scheduling sub-module, and each sub-instruction can be dispatched to the corresponding verification sub-module to process.

For example, for a type of functional instruction, the scheduling sub-module can parse it into two sub-instructions a1 and a2, and assuming that the value of P is 2, there are two verification sub-modules, namely verification sub-module a1 and verification sub-module a2, then the sub-command a1 can be dispatched to the verification sub-module a1, and the sub-command a2 can be dispatched to the verification sub-module a2.

By adopting the above processing method, further detailed processing of functional instructions can be realized, thereby further improving verification efficiency.

3) bottom layer

The bottom layer can be used to store the basic functions of the encapsulated scoreboard, that is, some basic operations/basic functions can be encapsulated, such as: direct programming interface (DPI, Direct Programming Interface) interface call, register/memory model instantiation, register /Memory read and write operations, communication interface instantiation, and analysis of received data, etc.

The middle layer can inherit the basic functions of the bottom layer, and can directly call already encapsulated tasks (tasks) and functions (functions).

In an embodiment of the present disclosure, the bottom layer may include: a basic function library, and correspondingly, different functional instruction verification modules in the middle layer may inherit the basic functions in the basic function library.

In addition, in an embodiment of the present disclosure, the bottom layer may further include: L basic function libraries, L is a positive integer greater than one, and different function instruction verification modules in the middle layer may respectively inherit the basic functions in the corresponding basic function libraries. Function.

The specific value of L can be determined according to actual needs, for example, it can be equal to the number of functional instruction verification modules in the middle layer. Correspondingly, each functional instruction verification module can correspond to its own basic function library.

Based on the above introduction, FIG. 3 is a second schematic diagram of the composition structure of the scoreboard in the present disclosure. As shown in Figure 3, it is assumed that the middle layer includes two functional instruction verification modules, namely functional instruction verification module a and functional instruction verification module b, wherein functional instruction verification module a is used to implement functional instruction verification of type a, and functional instruction The verification module b is used to realize the verification of class b functional instructions.

As shown in Figure 3, assuming that the functional instruction verification module a includes a scheduling sub-module a and two verification sub-modules, namely the verification sub-module a1 and the verification sub-module a2, then the scheduling sub-module a can schedule the top-level function The command is parsed into two sub-commands a1 and a2, and the sub-command a1 can be dispatched to the verification sub-module a1, and the sub-command a2 can be dispatched to the verification sub-module a2.

As shown in Figure 3, assuming that the functional command verification module b includes a scheduling sub-module b and 2 verification sub-modules, namely the verification sub-module b1 and the verification sub-module b2, then the scheduling sub-module b can schedule the top-level functions The instruction is parsed into two sub-instructions b1 and b2, and the sub-instruction b1 can be dispatched to the verification sub-module b1, and the sub-instruction b2 can be dispatched to the verification sub-module b2.

The bottom layer may include a basic function library, for example, the basic function library A, the functional instruction verification module a and the functional instruction verification module b can all inherit the basic functions in the basic function library.

Alternatively, it is assumed that the functional instruction verification module a corresponds to a calculation-type functional instruction, and the functional instruction verification module b corresponds to a data-moving functional instruction. As shown in Figure 2, the bottom layer may include a basic function library B and a basic function library C. The functional instruction verification module a can inherit the basic function library B, and the functional instruction verification module b can inherit the basic function library C.

For the basic function library B, it can include all kinds of common basic functions and basic functions required by the calculation class; for the basic function library C, it can include all kinds of general basic functions and the basic functions required by the data movement class basic function. If there is only the basic function library A, then all required basic functions can be encapsulated in the basic function library A, and each functional instruction verification module can use all or part of the basic functions according to its own needs.

It should be noted that, for the aforementioned method embodiments, for the sake of simple description, it is expressed as a series of action combinations, but those skilled in the art should know that the present disclosure is not limited by the described action sequence, because according to this It is disclosed that certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification belong to preferred embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

In short, by adopting the scheme described in the disclosed method embodiment, the complex scoreboard function is decomposed, and different levels are used to realize different scoreboard functions. The levels are clear and the division of labor is clear, easy to implement, and easy to manage and maintain , and can support hierarchical nesting, support rapid development and optimization iterations of design, design update and optimization of different functions only need to optimize the corresponding level, which improves the verification efficiency, etc.

The above is the introduction of the method embodiments, and the solution of the present disclosure will be further described through the device embodiments below.

FIG. 4 is a schematic diagram of the composition and structure of an embodiment 400 of an apparatus for implementing a scoreboard according to the present disclosure. As shown in FIG. 4 , it includes: a first processing unit 401 and a second processing unit 402 .

The first processing unit 401 is configured to construct M functional layers respectively, where M is a positive integer greater than one, and different functional layers are used to implement different scoreboard functions.

The second processing unit 402 is configured to use the M functional layers to form the scoreboard.

In the solutions described in the above embodiments, the scoreboard is hierarchically processed, that is, a layered design architecture is adopted, and the functions of each layer are clear and simple, easy to implement, and easy to manage and maintain.

In an embodiment of the present disclosure, the value of M may be 3, and accordingly, the three different functional layers may be respectively: the bottom layer, the middle layer and the top layer.

In an embodiment of the present disclosure, the top layer may adopt a tree-structured level-by-level scheduling manner.

The middle layer can be used to inherit the basic functions and complete the verification of the dispatched function instructions. In an embodiment of the present disclosure, the middle layer may include N functional instruction verification modules, and N is a positive integer, that is, it may include only one functional instruction verification module, or may include multiple functional instruction verification modules. When N is greater than one, Different functional instruction verification modules can be respectively used to realize the verification of different types of functional instructions.

For example, for calculation-type functional instructions, there may be various calculation functions such as addition, subtraction, multiplication, and division. Correspondingly, it can be parsed into multiple sub-instructions by using the scheduling sub-module, and each sub-instruction can be dispatched to the corresponding verification sub-module to process.

The bottom layer can be used to store the basic functions of the encapsulated scoreboard, that is, some basic operations/basic functions can be encapsulated, such as: direct programming interface call, register/memory model instantiation, register/memory read and write operations, communication interface Instantiation and analysis of received data, etc.

FIG. 5 is a schematic diagram of the composition and structure of the scoreboard embodiment 500 of the present disclosure. As shown in Figure 5, it includes: M functional layers, as shown in the figure, functional layer 1 to functional layer M, where M is a positive integer greater than 1, and different functional layers are used to implement different scoreboard functions.

In an embodiment of the present disclosure, the value of M can be 3, and correspondingly, the three different functional layers can be respectively: the bottom layer, the middle layer and the top layer.

The bottom layer can be used to store the underlying functionality of the encapsulated scoreboard. In an embodiment of the present disclosure, the bottom layer may include: a basic function library, and correspondingly, different functional instruction verification modules in the middle layer may inherit the basic functions in the basic function library.

For the specific work flow of the embodiments shown in FIG. 4 and FIG. 5 , reference may be made to relevant descriptions in the foregoing method embodiments.

In short, using the solution described in the above-mentioned embodiment, the complex scoreboard function is decomposed, and different levels are used to realize different scoreboard functions. It can support hierarchical nesting, support rapid development and optimization iterations of design, and design update and optimization of different functions only needs to optimize the corresponding levels, which improves the verification efficiency, etc.

The solution described in the present disclosure can be applied to the field of artificial intelligence, and particularly relates to fields such as artificial intelligence chips and intelligent voice. Artificial intelligence is a discipline that studies how to make computers simulate certain human thinking processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.). It includes both hardware-level technology and software-level technology. Artificial intelligence hardware technology generally includes such Sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing and other technologies, artificial intelligence software technology mainly includes computer vision technology, speech recognition technology, natural language processing technology and machine learning/deep learning, big data processing technology, Several major directions such as knowledge graph technology.

In the technical solution of this disclosure, the collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved are all in compliance with relevant laws and regulations, and do not violate public order and good customs.

According to the embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

FIG. 6 shows a schematic block diagram of an electronic device 600 that may be used to implement embodiments of the present disclosure. Electronic device is intended to represent various forms of digital computers, such as laptops, desktops, workstations, servers, blade servers, mainframes, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are by way of example only, and are not intended to limit implementations of the disclosure described and/or claimed herein.

As shown in FIG. 6, the device 600 includes a computing unit 601 that can execute according to a computer program stored in a read-only memory (ROM) 602 or loaded from a storage unit 608 into a random-access memory (RAM) 603. Various appropriate actions and treatments. In the RAM 603, various programs and data necessary for the operation of the device 600 can also be stored. The computing unit 601, ROM 602, and RAM 603 are connected to each other through a bus 604. An input/output (I/O) interface 605 is also connected to the bus 604 .

Multiple components in the device 600 are connected to the I/O interface 605, including: an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a magnetic disk, an optical disk, etc. ; and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 609 allows the device 600 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.

Computing unit 601 may be various general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of computing units 601 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc. The calculation unit 601 executes the various methods and processes described above, such as the methods described in this disclosure. For example, in some embodiments, the methods described in the present disclosure may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 608 . In some embodiments, part or all of the computer program may be loaded and/or installed on the device 600 via the ROM 602 and/or the communication unit 609. When a computer program is loaded into RAM 603 and executed by computing unit 601, one or more steps of the methods described in this disclosure may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured in any other appropriate way (for example, by means of firmware) to execute the methods described in the present disclosure.

Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips Implemented in a system of systems (SOC), complex programmable logic device (CPLD), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include being implemented in one or more computer programs executable and/or interpreted on a programmable system including at least one programmable processor, the programmable processor Can be special-purpose or general-purpose programmable processor, can receive data and instruction from storage system, at least one input device, and at least one output device, and transmit data and instruction to this storage system, this at least one input device, and this at least one output device an output device.

Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

To provide for interaction with the user, the systems and techniques described herein can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user. ); and a keyboard and pointing device (eg, a mouse or a trackball) through which a user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and can be in any form (including Acoustic input, speech input or, tactile input) to receive input from the user.

The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., as a a user computer having a graphical user interface or web browser through which a user can interact with embodiments of the systems and techniques described herein), or including such backend components, middleware components, Or any combination of front-end components in a computing system. The components of the system can be interconnected by any form or medium of digital data communication, eg, a communication network. Examples of communication networks include: Local Area Network (LAN), Wide Area Network (WAN) and the Internet.

A computer system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

It should be understood that steps may be reordered, added or deleted using the various forms of flow shown above. For example, each step described in the present disclosure may be executed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in the present disclosure can be achieved, no limitation is imposed herein.

The specific implementation manners described above do not limit the protection scope of the present disclosure. It should be apparent to those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made depending on design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

A method for implementing a scoreboard, comprising:

Construct M functional layers respectively, M is a positive integer greater than one, and different functional layers are used to realize different scoreboard functions;

The scoreboard is composed of the M functional layers.
The method according to claim 1, wherein,

The M functional layers include: bottom layer, middle layer and top layer;

The bottom layer is used to store the basic functions of the packaged scoreboard;

The top layer is used to realize the scheduling management of functional instructions;

The middle layer is used to inherit the basic functions and complete the verification of the dispatched function instructions.
The method according to claim 2, wherein the top layer adopts a tree-structured step-by-step scheduling method.
The method according to claim 2 or 3, wherein,

The middle layer includes N functional instruction verification modules, where N is a positive integer. When N is greater than 1, different functional instruction verification modules are used to verify different types of functional instructions.
The method according to claim 4, wherein,

The functional instruction verification module includes: a scheduling submodule and P verification submodules, where P is a positive integer greater than one;

The scheduling sub-module is used to parse the scheduled functional instruction into at least two sub-instructions, and dispatch each sub-instruction to the corresponding verification sub-module;

The verification sub-module is used to complete the verification of the dispatched sub-instructions.
The method according to claim 4, wherein,

The bottom layer includes: a basic function library, and different functional instruction verification modules inherit the basic functions in the basic function library;

Alternatively, the bottom layer includes: L basic function libraries, where L is a positive integer greater than one, and different functional instruction verification modules inherit the basic functions in the corresponding basic function libraries.
A scoreboard implementation device, comprising: a first processing unit and a second processing unit;

The first processing unit is used to construct M functional layers respectively, where M is a positive integer greater than one, and different functional layers are respectively used to realize different scoreboard functions;

The second processing unit is configured to use the M functional layers to form the scoreboard.
The apparatus according to claim 7, wherein,

The M functional layers include: bottom layer, middle layer and top layer;

The bottom layer is used to store the basic functions of the packaged scoreboard;

The top layer is used to realize the scheduling management of functional instructions;

The middle layer is used to inherit the basic functions and complete the verification of the dispatched function instructions.
The device according to claim 8, wherein the top layer adopts a tree-structured step-by-step scheduling method.
Apparatus according to claim 8 or 9, wherein,

The middle layer includes N functional instruction verification modules, where N is a positive integer. When N is greater than 1, different functional instruction verification modules are used to verify different types of functional instructions.
The apparatus of claim 10, wherein,

The functional instruction verification module includes: a scheduling submodule and P verification submodules, where P is a positive integer greater than one;

The scheduling sub-module is used to parse the scheduled functional instruction into at least two sub-instructions, and dispatch each sub-instruction to the corresponding verification sub-module;

The verification sub-module is used to complete the verification of the dispatched sub-instructions.
The apparatus of claim 10, wherein,

The bottom layer includes: a basic function library, and different functional instruction verification modules inherit the basic functions in the basic function library;

Alternatively, the bottom layer includes: L basic function libraries, where L is a positive integer greater than one, and different functional instruction verification modules inherit the basic functions in the corresponding basic function libraries.
A scoreboard includes: M functional layers, where M is a positive integer greater than one, and different functional layers are used to realize different functions of the scoreboard.
The scoreboard of claim 13, wherein:

The M functional layers include: bottom layer, middle layer and top layer;

The bottom layer is used to store the basic functions of the packaged scoreboard;

The top layer is used to realize the scheduling management of functional instructions;

The middle layer is used to inherit the basic functions and complete the verification of the dispatched function instructions.
The scoreboard according to claim 14, wherein the top layer adopts a tree-structured scheduling method step by step.
A scoreboard according to claim 14 or 15, wherein:

The middle layer includes N functional instruction verification modules, where N is a positive integer. When N is greater than 1, different functional instruction verification modules are used to verify different types of functional instructions.
The scoreboard of claim 16, wherein:

The functional instruction verification module includes: a scheduling submodule and P verification submodules, where P is a positive integer greater than one;

The scheduling sub-module is used to parse the scheduled functional instruction into at least two sub-instructions, and dispatch each sub-instruction to the corresponding verification sub-module;

The verification sub-module is used to complete the verification of the dispatched sub-instructions.
The scoreboard of claim 16, wherein:

The bottom layer includes: a basic function library, and different functional instruction verification modules inherit the basic functions in the basic function library;

Alternatively, the bottom layer includes: L basic function libraries, where L is a positive integer greater than one, and different functional instruction verification modules inherit the basic functions in the corresponding basic function libraries.
An electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can perform any one of claims 1-6. Methods.
A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method according to any one of claims 1-6.
A computer program product, comprising computer programs/instructions, when the computer program/instructions are executed by a processor, the method according to any one of claims 1-6 is implemented.