WO2023142546A1

WO2023142546A1 - Method and device for adjusting interface parameter of storage medium

Info

Publication number: WO2023142546A1
Application number: PCT/CN2022/126617
Authority: WO
Inventors: 李由; 徐奎
Original assignee: 华为技术有限公司
Priority date: 2022-01-27
Filing date: 2022-10-21
Publication date: 2023-08-03
Also published as: CN116560486A

Abstract

The present application provides a method for adjusting an interface parameter of a storage medium and a controller for the storage medium, capable of avoiding the delay of service transmission. The method comprises: a control circuit determines, according to a target interface rate, an interface parameter of a storage medium matching the target interface rate, the control circuit being a control circuit corresponding to the storage medium; and when a connection bus between an interface of the control circuit and an interface of the storage medium is in an idle state, the control circuit sends to the interface of the storage medium the interface parameter of the storage medium matching the target interface rate.

Description

Method and device for adjusting interface parameters of storage medium

This application claims the priority of the patent application submitted to the China Patent Office on January 27, 2022, with the application number 202210102365.X, and the title of the invention is "Method and device for adjusting interface parameters of storage media", the entire content of which is incorporated by reference in this application.

technical field

The present application relates to the communication field, and more specifically, relates to a method and a device for adjusting interface parameters of a storage medium.

Background technique

With the development of cloud/computing/server business, the performance requirements of the system for storage media are increasing year by year. In order to match the performance requirements of the system, the input/output (input/output, IO) interface rate of the storage medium itself and the corresponding controller The IO interface rate is also getting higher and higher. In order to match the high-speed IO interface rate and meet the corresponding signal integrity (SI) requirements of data communication, the driving capability of the IO interface is continuously improved, the size of the driving resistance of the IO interface is continuously reduced, and the corresponding IO interface Power consumption also continues to rise.

In actual business applications, the performance requirements of the system are different in different time periods; for example, during the day and night, due to the different activity of users, the performance requirements of the system will be very different. In scenarios with low performance requirements, the IO interface rate of the storage medium and the IO interface rate of the controller corresponding to the storage medium are low; in scenarios with high performance requirements, the IO interface rate of the storage medium and the IO interface rate of the controller corresponding to the storage medium The rate is higher.

Since adjusting the interface parameters of the storage medium will change the integrity of the signal transmitted by the IO interface, when adjusting the interface parameters of the IO interface of the storage medium according to the IO interface rate of the storage medium, the current storage medium will be stopped. Service transmission of the IO interface. The memory firmware (firmware, FW) waits for the service transmission of the IO interface to stop before adjusting the interface parameters of the IO interface. However, if the service transmission is stopped for a period of time, it will cause the delay fluctuation of the service access of the system. In the scene where the interface parameters need to be continuously adjusted, it cannot adapt to the actual application.

Contents of the invention

The present application provides a method for adjusting interface parameters of a storage medium and a controller of the storage medium, which can avoid service transmission delays.

In a first aspect, a method for adjusting interface parameters of a storage medium is provided, including: a control circuit determines, according to a target interface rate, an interface parameter of the storage medium that matches the target interface rate, and the control circuit is the storage medium A control circuit corresponding to the medium; when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, the control circuit sends the interface parameters to the interface of the storage medium.

Based on the above solution, the control circuit corresponding to the storage medium can determine the interface parameters of the storage medium matching the target interface rate according to the target interface rate. When the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, The interface parameter is sent to the interface of the storage medium. Compared with adjusting the interface parameters of the interface of the memory at the time of stopping the service transmission in the prior art, this application adjusts the interface parameters when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, without stopping the ongoing business transmission, so as to avoid the delay of business transmission.

In a possible implementation manner, the interface parameters include the size of a drive resistor of the interface of the storage medium, the size of an on-chip termination resistor ODT, and a working clock signal.

In a possible implementation manner, the control circuit determines, according to the target interface rate, the interface parameters of the storage medium that match the target interface rate, including: the control circuit determines, according to the target interface rate, the The size of the drive resistance, the size of the ODT, and the operating frequency of the interface of the storage medium that the target interface rate matches; the control circuit sends a clock adjustment request to the clock generation circuit, and the clock adjustment request includes The working frequency and the clock adjustment request are used to request the clock generating circuit to generate the working clock signal of the working frequency; the control circuit receives the working clock signal generated by the clock generating circuit.

In a possible implementation, when the rate of the target interface increases, the control circuit reduces the size of the driving resistor, connects the ODT, or reduces the size of the ODT; when the target interface When the rate decreases, the control circuit increases the size of the driving resistor, does not connect the ODT, or increases the size of the ODT.

It should be understood that the higher the rate of the target interface, the higher the requirement for signal integrity, and reducing the size of the driving resistance and the size of the ODT of the interface can enhance the integrity of the signal transmitted by the interface. The lower the rate of the target interface, the lower the requirements for signal integrity. Increasing the size of the driving resistance and ODT of the interface can reduce the power consumption of the interface, thereby reducing the power consumption of the storage system.

In a possible implementation manner, the method further includes: the control circuit determining the target interface rate according to the current system performance requirement, and the current system performance requirement includes at least one of the following: accessing the storage The bandwidth of the medium and the access latency to access said storage medium.

In a possible implementation manner, the method further includes: a system performance sensing circuit sensing the current system performance requirement; the system performance sensing circuit sending the current system performance requirement to the control circuit.

In a possible implementation manner, the memory includes multiple storage particles, and the storage medium is one or more of the multiple storage particles.

It should be understood that each storage particle corresponds to an interface, and the interface of each storage particle is connected to the interface of the control circuit through a connection bus. In the prior art, it is necessary to adjust the interface parameters of all storage particles in the memory during the period of stopping the service transmission of the interfaces corresponding to all storage particles on the memory. In the embodiment of the present application, a certain (or some ) When the connection bus between the interfaces of the storage granules is in an idle state, adjusting the interface parameters of the corresponding storage granules will not affect the service transmission on the interfaces of other storage granules in the memory.

In a second aspect, a controller for a storage medium is provided, including: a control circuit, configured to determine an interface parameter of the storage medium that matches the target interface rate according to a target interface rate, and the control circuit is the storage medium A control circuit corresponding to the medium; the control circuit is also used to send the interface parameters to the interface of the storage medium when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state .

In a possible implementation manner, the controller further includes a clock generation circuit; the control circuit is specifically configured to: determine, according to the target interface rate, the clock speed of the interface of the storage medium that matches the target interface rate The size of the drive resistor, the size of the ODT, and the operating frequency; sending a clock adjustment request to the clock generation circuit, the clock adjustment request includes the operating frequency, and the clock adjustment request is used to request the clock The generating circuit generates the working clock signal of the working frequency; and receives the working clock signal generated by the clock generating circuit.

In a possible implementation manner, the control circuit is specifically configured to: reduce the size of the driving resistor, connect the ODT, or reduce the size of the ODT when the target interface rate increases; When the rate of the target interface decreases, the size of the driving resistor is increased, the ODT is not connected, or the size of the ODT is increased.

In a possible implementation manner, the control circuit is further configured to determine the target interface rate according to the current system performance requirement, where the current system performance requirement includes at least one of the following: Bandwidth and access latency to access the storage medium.

In a possible implementation manner, the controller further includes a system performance sensing circuit; the system performance sensing circuit is configured to sense the current system performance requirement; the system performance sensing circuit is also configured to provide The control circuit sends the current system performance requirement.

In a third aspect, a communication device is provided, including a processor and a transceiver, the transceiver is used to receive computer codes or instructions, and transmit them to the processor, and the processor runs the computer codes or instructions to implement The method in any possible implementation manner of the first aspect above.

In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a communication device, the communication device implements the method in any possible implementation manner in any of the above aspects .

In a fifth aspect, a computer program product including instructions is provided, and when the instructions are executed by a computer, the communication device implements the method in any possible implementation manner in any one of the above aspects.

Description of drawings

FIG. 1 is a schematic block diagram of an FW statically adjusting interface parameters of an IO interface of a storage medium.

FIG. 2 is a schematic flowchart of a method for adjusting interface parameters of a storage medium according to an embodiment of the present application.

Fig. 3 is an example of a method for adjusting an interface parameter of a storage medium according to an embodiment of the present application.

Fig. 4 is another example of the method for adjusting an interface parameter of a storage medium according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a controller of a storage medium provided by an embodiment of the present application.

FIG. 6 is an example of a controller of a storage medium provided in an embodiment of the present application.

Fig. 7 is a schematic block diagram of a communication device according to an embodiment of the present application.

Detailed ways

The technical solution in this application will be described below with reference to the accompanying drawings.

The embodiments of the present application may be applied to various flash (flash) storage devices. For example: solid state disk (solid state disk, SSD), secure digital card (secure digital card, SD Card), embedded multimedia card (embedded multi media card, eMMC), universal flash storage (universal flash storage, UFS) and custom state and other flash memory devices. Take the embedded multimedia card as an example, which includes digital camera memory card, MP3 player memory card, and compact U disk.

With the development of cloud/computing/server business, the performance requirements of the system for storage media are increasing year by year. In order to match the performance requirements of the system, the IO interface rate of the storage medium itself and the IO interface rate of the corresponding controller are also getting higher and higher. In order to match the high-speed IO interface rate and meet the corresponding signal integrity (SI) requirements of data communication, the driving capability of the IO interface is continuously improved, the size of the driving resistance of the IO interface is continuously reduced, and the corresponding IO interface Power consumption also continues to rise.

In actual business applications, the performance requirements of the system are different in different time periods. For example, during the day and night, due to the different user activity, the performance requirements of the system will be very different. In scenarios with low performance requirements or low performance requirements, the IO interface rate of the storage medium and the IO interface rate of the controller corresponding to the storage medium are low; in scenarios with high performance requirements or high performance requirements, the IO interface rate of the storage medium The rate and the IO interface rate of the controller corresponding to the storage medium are relatively high.

At present, in the power-on stage of the system, the IO interface of the storage medium and the IO interface of the controller corresponding to the storage medium can be matched according to the IO interface of the current storage medium and the interface rate that the IO interface of the controller corresponding to the storage medium needs to support. The operating frequency, the size of the drive resistor, the size of the on-die termination (ODT) and the size of the reference voltage (voltage reference, Vref) and other parameters.

In the process of switching from a high-performance requirement scenario to a low-performance requirement scenario or from a low-performance requirement scenario to a high-performance requirement scenario, the service transmission of the current IO interface will be stopped; and the IO of the storage medium will be adjusted according to the interface rate that the IO interface needs to support. The interface and the size of the driving resistance of the IO interface of the controller corresponding to the storage medium, the size of the ODT, the working clock signal, Vref, and interface parameters such as process, voltage, temperature (process, voltage, temperature, PVT).

Since adjusting the interface parameters of the IO interface will change the integrity of the signal transmitted by the IO interface, when adjusting the interface parameters of the IO interface, the current service transmission of the IO interface will be stopped. The FW waits for the service transmission of the IO interface to stop before adjusting the interface parameters of the IO interface. However, if the transmission of business data stops for a period of time, it will cause delay fluctuations in the system's access to the business; in the scenario where the interface parameters need to be continuously adjusted, it cannot adapt to the actual application. As shown in Figure 1, it shows a schematic block diagram of the FW statically adjusting the interface parameters of the IO interface of the memory, wherein, taking the flash memory as an example, the FW statically adjusts the interface parameters of the IO interface of the flash memory using a full software method. .

For this reason, the embodiment of the present application proposes a method for adjusting interface parameters of a storage medium, which can avoid service transmission delay.

As shown in FIG. 2 , a schematic flowchart of a method 200 for adjusting an interface parameter of a storage medium according to an embodiment of the present application is shown.

210. The control circuit determines the interface parameters of the storage medium matching the target interface rate according to the target interface rate. The control circuit is the control circuit corresponding to the storage medium, that is to say, the control circuit is a circuit in the controller corresponding to the storage medium . The target interface rate is determined by the control circuit according to the system performance requirements of the current storage system; the system performance requirements include at least one of the following: bandwidth for accessing the storage medium, access delay for accessing the storage medium, etc. Bandwidth, the access delay of the central processing unit to access the storage medium, etc., such as the bandwidth of the SSD disk/UFS card/eMMC card and the IO per second (IO per second, IOPS) requirement, etc.

Optionally, the system performance sensing circuit senses the current system performance requirement, and sends the current system performance requirement to the control circuit. Correspondingly, the control circuit receives the current system performance requirement sent by the system performance sensing circuit, and determines the target interface rate to be supported by the interface of the storage medium and the interface of the controller corresponding to the storage medium according to the current system performance requirement. For different system performance requirements, the interface of the storage medium and the interface of the controller corresponding to the storage medium need to support the same target interface rate, and the interface parameters of the interface of the storage medium and the interface of the controller corresponding to the storage medium The interface parameters may also be the same.

Exemplarily, the interface parameters of the storage medium include the size of the drive resistance of the interface of the storage medium, the size of the on-chip termination resistor, and the working clock signal. Optionally, the interface parameters of the storage medium may also include interface parameters such as Vref and PVT of the interface of the storage medium. It should be understood that the interface parameters of the interface of the storage medium may also be different from the interface parameters of the interface of the controller corresponding to the storage medium. For example, the size of the drive resistance and the size of the ODT of the interface of the storage medium may be different from the size of the drive resistance of the interface of the controller corresponding to the storage medium and the size of the ODT, but the working clock signal of the interface of the storage medium is different from the size of the ODT of the interface of the storage medium. The working clock signal of the interface of the controller corresponding to the storage medium is the same. In this case, the size of the drive resistance and the ODT of the interface of the storage medium are the same as the size of the drive resistance and ODT of the interface of the controller corresponding to the storage medium. The size is one-to-one correspondence.

Exemplarily, the control circuit may determine, according to the target interface rate, the size of the drive resistance, the size of the ODT, and the operating frequency of the interface of the storage medium that match the target interface rate. The control circuit sends a clock adjustment request to the clock generation circuit, and the clock adjustment request includes the operating frequency determined by the control circuit; the clock generation circuit generates an operating clock signal of the operating frequency, and sends the operating clock signal to the control circuit; the control circuit The working clock signal generated by the clock generating circuit is received. Wherein, the clock generation circuit is also a circuit in the controller corresponding to the storage medium.

Exemplarily, when the target interface rate increases, the control circuit reduces the size of the drive resistance of the interface of the storage medium, connects the ODT or reduces the size of the ODT of the interface of the storage medium, and increases the working frequency of the working clock signal; Wherein, connecting the ODT can be understood as connecting an ODT with a smaller resistance value or a designated ODT. When the target interface rate decreases, the control circuit increases the size of the drive resistance of the interface of the storage medium, disconnects the ODT or increases the size of the ODT of the interface of the storage medium, and reduces the size of the operating frequency of the operating clock signal; wherein, Disconnecting the ODT can be understood as connecting an ODT with a large resistance value. Since the connected ODT has a large resistance value, the ODT is equivalent to a suspended or disconnected state.

It should be understood that the higher the rate of the target interface, the higher the requirements for signal integrity. Reducing the size of the drive resistance and ODT of the interface can enhance the integrity of the signal transmitted by the interface. At the same time, the power consumption of the interface is also reduced. increase accordingly. The lower the rate of the target interface, the lower the requirements for signal integrity. Increasing the size of the driving resistance and ODT of the interface can reduce the power consumption of the interface, thereby reducing the power consumption of the storage system.

220. When the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, the control circuit sends an interface parameter to the interface of the storage medium. When the connection bus between the interface of the control circuit and the interface of the storage medium is not in an idle state, there is no need to stop the service transmission, and wait for the completion of the service transmission. It should be understood that since all read and write commands and service transmissions are initiated by the controller, the control circuit in the controller can accurately predict the behavior on the connection bus between the interface of the control circuit and the interface of the storage medium . Specifically, the control circuit can dynamically acquire the use right of the connection bus and the control right of the storage medium according to the type of the currently transmitted service and the transmission stage of the service currently transmitted on the connection bus.

Wherein, the connecting bus between the interface of the control circuit and the interface of the storage medium is in an idle state, it can be understood that the control circuit does not access the storage medium, or the control circuit does not access the bus operation of the storage medium. When the connection bus between the interface of the control circuit and the interface of the storage medium is not in an idle state, there may be data transmission, command transmission, address transmission or timing control state related to the transmission process on the connection bus, that is to say, the There is traffic transmission on the connection bus.

Correspondingly, the control circuit determines the interface parameters of the interface of the control circuit matching the target interface rate according to the target interface rate, and the control circuit can also quickly adjust the interface parameters of the interface of the control circuit, wherein the interface of the control circuit The interface parameters of the storage medium may be the same as the interface parameters of the storage medium.

Exemplarily, when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, the control circuit sends to the interface of the storage medium the size of the drive resistance of the interface of the storage medium, the size of the on-chip termination resistor and Working clock signal. Optionally, the control circuit may also send parameters such as Vref and PVT of the interface of the storage medium to the interface of the storage medium.

Exemplarily, the memory includes multiple storage particles, and the storage medium in the embodiment of the present application may be one or more storage particles in the memory, that is to say, the storage medium is a part of the multiple storage particles. Taking the memory as flash as an example, the control circuit is connected to one or more groups of flash dies at the same time, each group of flash dies includes 8 flash dies, and each flash die corresponds to an interface. The storage particle can be one or more flash dies in the flash, and when the connection bus between the interface of the control circuit and the interface of one or more flash dies is in an idle state, an interface is sent to the interface of the one or more flash dies parameter. That is to say, when the connection bus between the interface of the control circuit and the interface of a certain (or some) storage particles in the memory is in an idle state, adjusting the interface parameters of the corresponding storage particles will not affect other storage particles in the memory Service transmission on the interface.

In the technical solution provided by the embodiment of this application, the control circuit corresponding to the storage medium can determine the interface parameters of the storage medium matching the target interface rate according to the target interface rate, when the interface between the control circuit and the storage medium interface When the connection bus is in an idle state, the interface parameters are sent to the interface of the storage medium. Compared with adjusting the interface parameters of the interface of the memory at the time of stopping the service transmission in the prior art, this application adjusts the interface parameters when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, without stopping the ongoing business transmission, so as to avoid the delay of business transmission.

As shown in FIG. 3 , an example of a method for adjusting an interface parameter of a storage medium according to an embodiment of the present application is shown. The operating frequency applicable to the interface is switched from high frequency to low frequency.

301. A system performance sensing circuit senses a change in a current system performance requirement, and the system performance sensing circuit sends the current system performance requirement to a control circuit in a controller. Optionally, the control circuit may include a power consumption control circuit and an IO control circuit. The interface of the IO control circuit is the interface of the control circuit. The system performance sensing circuit may be a circuit in the controller, or a circuit connected to the controller outside the controller.

Exemplarily, the system performance sensing circuit may send the current system performance requirement to the power consumption control circuit in the controller.

302. The power consumption control circuit receives the current system performance requirement sent by the system performance sensing circuit, and starts system power consumption control.

Specifically, the power consumption control circuit determines the target interface rate matching the current system performance requirement according to the current system performance requirement; the power consumption control circuit determines the storage medium rate matching the target interface rate according to the target interface rate Parameters such as the size of the driving resistance of the interface, the size of the ODT, and the operating frequency.

The operating frequency of the interface is switched from high frequency to low frequency, that is, the target interface rate is switched from high rate to low rate. Because the target interface rate decreases, the power consumption control circuit increases the size of the drive resistance of the interface of the storage medium, does not connect the ODT or increases the size of the ODT of the interface of the storage medium, and reduces the operating frequency of the operating clock signal, which can The power consumption of the interface is reduced, so that the power consumption of the storage system can be reduced.

The power consumption control circuit sends an IO power consumption control request to the IO control circuit, and the IO power consumption control request includes parameters such as the size of the driving resistance of the interface of the storage medium that matches the rate of the target interface, the size of the ODT, and the operating frequency.

303. The IO control circuit receives the IO power consumption control request sent by the power consumption control circuit.

The IO control circuit sends a clock adjustment request to the clock generation circuit in the controller. The clock adjustment request includes the operating frequency of the interface of the storage medium that matches the rate of the target interface. The clock adjustment request is used to request the clock generation circuit to generate the work frequency. frequency of the operating clock signal.

The IO control circuit receives the working clock signal of the working frequency generated by the clock generating circuit.

304. The IO control circuit predicts a behavior on the connection bus between the interface of the IO control circuit/control circuit/controller and the interface of the storage medium. When the connection bus between the interface of the IO control circuit/control circuit/controller and the interface of the storage medium is in an idle state, the IO control circuit/control circuit/controller sends the storage data matched with the rate of the target interface to the interface of the storage medium Interface parameters such as the size of the driving resistance of the interface of the medium, the size of the ODT, and the working clock signal. Optionally, the interface parameters of the storage medium may also include interface parameters such as Vref and PVT of the interface of the storage medium.

When the connection bus between the interface of the IO control circuit/controller/control circuit and the interface of the storage medium is not in an idle state, there is no need to stop the current service transmission and wait for the completion of service data transmission.

Exemplarily, when the connection bus between the interface of the IO control circuit/control circuit/controller and the interface of the storage medium is in an idle state, the IO control circuit/control circuit/controller sends a first indication to the interface of the storage medium The information/first instruction, the first instruction information/first instruction includes interface parameters such as the size of the driving resistance of the interface of the storage medium that matches the rate of the target interface, the size of the ODT, and the working clock signal.

305. The IO control circuit adjusts the interface parameters of the interface of the IO control circuit/control circuit/controller, where the interface parameters of the interface of the IO control circuit/control circuit/controller may be the same as the interface parameters of the interface of the storage medium.

It should be understood that the IO control circuit and the power consumption control circuit may be integrated circuits, which are collectively referred to as control circuits. The IO control circuit and the power consumption control circuit may also be independent and different hardware circuits.

305 and 304 may be in no particular order, 305 may be before 304, and 305 and 304 may be performed simultaneously. This application does not specifically limit it.

As shown in FIG. 4 , another example of the method for adjusting an interface parameter of a storage medium according to the embodiment of the present application is shown. The operating frequency applicable to the interface is switched from low frequency to high frequency.

401. A system performance sensing circuit senses a change in a current system performance requirement, and the system performance sensing circuit sends the current system performance requirement to a control circuit in a controller. Optionally, the control circuit may include a power consumption control circuit and an IO control circuit. The interface of the IO control circuit is the interface of the control circuit. The system performance sensing circuit may be a circuit in the controller, or a circuit connected to the controller outside the controller.

402. The power consumption control circuit receives the current system performance requirement sent by the system performance sensing circuit, and starts system power consumption control.

The operating frequency of the interface is switched from low frequency to high frequency, that is, the target interface rate is switched from low rate to high rate. Because the rate of the target interface increases, the power consumption control circuit reduces the size of the drive resistance of the interface of the storage medium, connects the ODT or reduces the size of the ODT of the interface of the storage medium, and increases the working frequency of the working clock signal. The higher the rate of the target interface, the higher the requirements for signal integrity. Reducing the size of the drive resistance and ODT of the interface can enhance the integrity of the signal transmitted by the interface.

403. The IO control circuit receives the IO power consumption control request sent by the power consumption control circuit.

404. The IO control circuit predicts a behavior on the connection bus between the interface of the IO control circuit/control circuit/controller and the interface of the storage medium. When the connection bus between the interface of the IO control circuit/control circuit/controller and the interface of the storage medium is in an idle state, the IO control circuit/control circuit/controller sends the storage data matched with the rate of the target interface to the interface of the storage medium Interface parameters such as the size of the driving resistance of the interface of the medium, the size of the ODT, and the working clock signal. Optionally, the interface parameters of the storage medium may also include interface parameters such as Vref and PVT of the interface of the storage medium.

405. The IO control circuit adjusts the interface parameters of the interface of the IO control circuit/control circuit/controller, where the interface parameters of the interface of the IO control circuit/control circuit/controller may be the same as the interface parameters of the interface of the storage medium.

405 and 404 can be in no particular order, 405 can be before 404, and 405 and 404 can also be performed simultaneously. This application does not specifically limit it.

As shown in FIG. 5 , a schematic diagram of a controller 500 of a storage medium provided in an embodiment of the present application is shown, and the controller 500 includes:

The control circuit 510 is configured to determine the interface parameters of the storage medium matching the target interface rate according to the target interface rate, the control circuit is a control circuit corresponding to the storage medium;

The control circuit 510 is further configured to send the interface parameters to the interface of the storage medium when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state.

Optionally, the interface parameters include the size of the driving resistance of the interface of the storage medium, the size of the on-chip termination resistor ODT, and the working clock signal.

Optionally, the controller further includes a clock generation circuit 520;

The control circuit 510 is specifically used for:

According to the target interface rate, determine the size of the drive resistance, the size of the ODT, and the operating frequency of the interface of the storage medium that match the target interface rate;

Sending a clock adjustment request to the clock generation circuit 520, where the clock adjustment request includes the operating frequency, and the clock adjustment request is used to request the clock generation circuit 520 to generate the operating clock signal of the operating frequency;

The working clock signal generated by the clock generating circuit 520 is received.

Optionally, the control circuit 510 is specifically used for:

When the target interface rate increases, reduce the size of the driving resistor, connect the ODT or reduce the size of the ODT;

When the rate of the target interface decreases, the size of the driving resistor is increased, the ODT is not connected, or the size of the ODT is increased.

Optionally, the control circuit 510 is further configured to determine the target interface rate according to the current system performance requirement, and the current system performance requirement includes at least one of the following: the bandwidth for accessing the storage medium and the bandwidth for accessing the The access delay of the storage medium mentioned above.

Optionally, the controller further includes a system performance sensing circuit 530;

The system performance sensing circuit 530 is configured to sense the current system performance requirements;

The system performance sensing circuit 530 is further configured to send the current system performance requirement to the control circuit;

The control circuit 510 is further configured to receive the current system performance requirement from the system performance sensing circuit 530 . It should be understood that the system performance sensing circuit 530 may also be a circuit other than the controller connected to the controller. Optionally, the memory includes multiple storage particles, and the storage medium is one or more storage particles.

As shown in FIG. 6 , an example of a controller 600 for a storage medium provided in the embodiment of the present application is shown.

The controller includes: an IO control circuit 611 , a power consumption control circuit 612 , a clock generation circuit 620 , a system performance sensing circuit 630 and an adjustment recording circuit 640 . The IO control circuit 611 and the power consumption control circuit 612 may be collectively referred to as a control circuit. The IO control circuit 611 and the power consumption control circuit 612 may be the control circuit 510 in FIG. 5 .

The system performance sensing circuit 630 is configured to sense changes in current system performance requirements, where the current system performance requirements include at least one of the following: bandwidth for accessing the storage medium and access delay for accessing the storage medium;

The system performance sensing circuit 630 is also configured to send the current system performance requirement to the power consumption control circuit 612 in the controller. It should be understood that the system performance sensing circuit 630 may also be a circuit other than the controller connected to the controller.

The power consumption control circuit 612 is used for:

receiving the current system performance requirements sent by the system performance sensing circuit 630;

According to the current system performance requirements, determine the target interface rate that matches the current system performance requirements;

According to the target interface rate, parameters such as the size of the driving resistance of the interface of the storage medium matching the target interface rate, the size of the ODT, and the operating frequency are determined. Optionally, the memory includes multiple storage particles, and the storage medium may be one or more of the multiple storage particles.

The power consumption control circuit 612 is also used to send an IO power consumption control request to the IO control circuit 611, the IO power consumption control request includes the size of the drive resistance of the interface of the storage medium matching the target interface rate, the size of the ODT and the working parameters such as frequency.

IO control circuit 611, for:

receiving the IO power consumption control request sent by the power consumption control circuit 612;

Send a clock adjustment request to the clock generation circuit 620, the clock adjustment request includes the operating frequency of the interface of the storage medium matched with the target interface rate, and the clock adjustment request is used to request the clock generation circuit 620 to generate a working clock signal of the operating frequency .

The clock generating circuit 620 is configured to generate a working clock signal of the working frequency, and send the working clock signal of the working frequency to the IO control circuit 611 .

The IO control circuit 611 is also used to predict the behavior on the connection bus between the interface of the IO control circuit and the interface of the storage medium. When the connection bus between the interface of the IO control circuit and the interface of the storage medium is in an idle state, the IO control circuit sends to the interface of the storage medium the size of the driving resistance and the ODT of the interface of the storage medium matched with the target interface rate and working clock signal and other interface parameters. Optionally, the interface parameters of the storage medium may also include interface parameters such as Vref and PVT of the interface of the storage medium.

The IO control circuit 611 is further configured to adjust an interface parameter of an interface of the IO control circuit. The interface parameter of the interface of the IO control circuit may be the same as the interface parameter of the interface of the storage medium.

The adjustment recording circuit 640 is configured to record which storage media in the memory have interface parameters whose interface parameters have been adjusted and/or which storage media in the memory whose interface parameters have not been adjusted yet. Optionally, the adjustment record circuit 640 may also be integrated in the IO control circuit 611 .

An embodiment of the present application provides a communication device 700 , as shown in FIG. 7 , which shows a schematic block diagram of the communication device 700 according to the embodiment of the present application.

The device 700 includes: a processor 710 and a transceiver 720, the transceiver 720 is used to receive computer codes or instructions and transmit them to the processor 710, and the processor 710 runs the computer codes or instructions, as described herein The method in any possible implementation manner in the application embodiment.

The above-mentioned processor 710 may be an integrated circuit chip, which has a signal processing capability. In the implementation process, each step of the above-mentioned method embodiments may be completed by an integrated logic circuit of hardware in a processor or instructions in the form of software. The above-mentioned processor can be a general-purpose processor, a digital signal processor (digital signal processor, DSP), an application specific integrated circuit (application specific integrated circuit, ASIC), an off-the-shelf programmable gate array (field programmable gate array, FPGA) or other available Program logic devices, discrete gate or transistor logic devices, discrete hardware components. Various methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register. The storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.

The embodiment of the present application also provides a computer-readable storage medium, on which a computer program for implementing the method in the above method embodiment is stored. When the computer program runs on the computer or the processor, the computer or the processor can implement the methods in the above method embodiments.

The embodiment of the present application also provides a computer program product, the computer program product includes computer program code, and when the computer program code is run on the computer, the method in the above method embodiment is executed.

The embodiment of the present application also provides a chip, including a processor, the processor is connected to a memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the The chip executes the method in the above method embodiment.

In addition, the term "and/or" in this application is only an association relationship describing associated objects, indicating that there may be three relationships, for example, A and/or B may indicate: A exists alone, and A and B exist simultaneously , there are three cases of B alone. In addition, the character "/" in this article generally means that the contextual objects are an "or" relationship; the term "at least one" in this application can mean "one" and "two or more", for example, A , B and C, can mean: A alone exists, B exists alone, C exists alone, A and B exist simultaneously, A and C exist simultaneously, C and B exist simultaneously, A, B and C exist simultaneously, these seven kinds Condition.

Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may implement the described functionality using different methods for each particular application, but such implementation should not be considered as exceeding the scope of the present application.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, and will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A method for adjusting an interface parameter of a storage medium, comprising:

The control circuit determines the interface parameters of the storage medium matching the target interface rate according to the target interface rate, and the control circuit is a control circuit corresponding to the storage medium;

When the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, the control circuit sends the interface parameter to the interface of the storage medium.
The method according to claim 1, characterized in that,

The interface parameters include the size of the driving resistance of the interface of the storage medium, the size of the on-chip termination resistor ODT and the working clock signal.
The method according to claim 2, wherein the control circuit determines the interface parameters of the storage medium matching the target interface rate according to the target interface rate, including:

The control circuit determines the size of the driving resistance, the size of the ODT and the operating frequency of the interface of the storage medium that match the target interface rate according to the target interface rate;

The control circuit sends a clock adjustment request to the clock generation circuit, the clock adjustment request includes the operating frequency, and the clock adjustment request is used to request the clock generation circuit to generate the operating clock signal of the operating frequency;

The control circuit receives the working clock signal generated by the clock generating circuit.
The method according to claim 2 or 3, characterized in that,

When the target interface rate increases, the control circuit reduces the size of the driving resistor, connects the ODT or reduces the size of the ODT;

When the target interface rate decreases, the control circuit increases the size of the driving resistor, turns off the ODT, or increases the size of the ODT.
The method according to any one of claims 1 to 4, wherein the method further comprises:

The control circuit determines the target interface rate according to the current system performance requirements, and the current system performance requirements include at least one of the following:

The bandwidth for accessing the storage medium or the access delay for accessing the storage medium.
The method according to any one of claims 1 to 5, wherein the method further comprises:

The system performance sensing circuit senses the current system performance requirement;

The system performance sensing circuit sends the current system performance requirement to the control circuit.
A method according to any one of claims 1 to 6, characterized in that,

The memory includes multiple storage particles, and the storage medium is one or more of the multiple storage particles.
A storage medium controller, characterized in that it comprises:

A control circuit, configured to determine an interface parameter of the storage medium matching the target interface rate according to a target interface rate, the control circuit being a control circuit corresponding to the storage medium;

The control circuit is further configured to, when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, send the interface parameter to the interface of the storage medium.
The controller according to claim 8, characterized in that,

The interface parameters include the size of the driving resistance of the interface of the storage medium, the size of the on-chip termination resistor ODT and the working clock signal.
The controller according to claim 9, wherein the controller further comprises a clock generation circuit;

The control circuit is specifically used for:

According to the target interface rate, determine the size of the drive resistance, the size of the ODT, and the operating frequency of the interface of the storage medium that match the target interface rate;

sending a clock adjustment request to the clock generation circuit, where the clock adjustment request includes the operating frequency, and the clock adjustment request is used to request the clock generation circuit to generate the operating clock signal of the operating frequency;

The working clock signal generated by the clock generating circuit is received.
The controller according to claim 9 or 10, wherein the control circuit is specifically used for:

When the target interface rate increases, reduce the size of the driving resistor, connect the ODT or reduce the size of the ODT;

When the rate of the target interface decreases, the size of the driving resistor is increased, the ODT is not connected, or the size of the ODT is increased.
A controller according to any one of claims 8 to 11, characterized in that,

The control circuit is further configured to determine the target interface rate according to a current system performance requirement, where the current system performance requirement includes at least one of the following:

Bandwidth for accessing the storage medium and access latency for accessing the storage medium.
The controller according to any one of claims 8 to 12, wherein the controller further comprises a system performance sensing circuit;

The system performance sensing circuit is configured to sense the current system performance requirements;

The system performance sensing circuit is further configured to send the current system performance requirement to the control circuit.
A controller according to any one of claims 8 to 13, characterized in that,

The memory includes multiple storage particles, and the storage medium is one or more of the multiple storage particles.
A communication device, characterized in that it includes: a processor and a transceiver, the transceiver is used to receive computer codes or instructions and transmit them to the processor, and the processor runs the computer codes or instructions to implement the following: The method according to any one of claims 1 to 7.
A computer-readable storage medium, comprising:

A computer program is stored in the computer-readable storage medium;

When the computer program is run on a computer or a processor, the computer or the processor is executed to perform the method according to any one of claims 1 to 7.
A computer program product, characterized by comprising a computer program, when the computer program is executed, the method according to any one of claims 1 to 7 is realized.