WO2023073802A1 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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Publication number
WO2023073802A1
WO2023073802A1 PCT/JP2021/039441 JP2021039441W WO2023073802A1 WO 2023073802 A1 WO2023073802 A1 WO 2023073802A1 JP 2021039441 W JP2021039441 W JP 2021039441W WO 2023073802 A1 WO2023073802 A1 WO 2023073802A1
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Prior art keywords
voltage
current
circuit
output
semiconductor integrated
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PCT/JP2021/039441
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French (fr)
Japanese (ja)
Inventor
理 錦戸
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三菱電機株式会社
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Priority to PCT/JP2021/039441 priority Critical patent/WO2023073802A1/en
Priority to JP2023555927A priority patent/JPWO2023073802A1/ja
Publication of WO2023073802A1 publication Critical patent/WO2023073802A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Definitions

  • the present disclosure relates to semiconductor integrated circuit devices.
  • IC Integrated Circuit
  • checking whether the voltage is correctly output from the analog circuit to the internal node is an important factor in detecting failures.
  • the voltage of the internal node can be measured via the external terminal.
  • the voltages of the plurality of internal nodes can be measured by sharing the external terminal.
  • Patent Document 1 discloses that a voltage comparator is provided inside an IC to detect a DC voltage at a specific circuit node of an analog integrated circuit. is within a certain range, and the determination result is output to the outside of the IC.
  • the present disclosure has been made to solve such problems, and an object of the present disclosure is to speed up the normality determination of the voltage of the internal node of a semiconductor integrated circuit device with a simple circuit configuration. is.
  • the current comparator when switching between a plurality of voltage-to-current converters, can compare the measured voltage with the judgment voltage by comparing the output current obtained by voltage-to-current conversion of the measured voltage with the reference current. , the time required to stabilize the output current input to the current comparator can be shortened. As a result, it is possible to speed up the normality judgment of the voltage of the internal node of the semiconductor integrated circuit device with a simple circuit configuration.
  • FIG. 1 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a first embodiment
  • FIG. 2 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 1
  • FIG. FIG. 2 is a circuit diagram for explaining an internal configuration of each block shown in FIG. 1 according to Modification 1 of Embodiment 1
  • FIG. 10 is a circuit diagram illustrating a configuration of a voltage-current conversion circuit according to Modification 1 of Embodiment 1
  • FIG. 10 is a circuit diagram illustrating the configuration of a reference current source according to Modification 1 of Embodiment 1
  • 3 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a second embodiment
  • FIG. 7 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 6;
  • FIG. 7 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 6;
  • FIG. 3 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a third embodiment
  • FIG. 9 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 8
  • FIG. 12 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a fourth embodiment
  • FIG. 11 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 10
  • FIG. FIG. 11 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a fifth embodiment
  • 13 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 12
  • FIG. FIG. 11 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a sixth embodiment
  • 15 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 14;
  • the suffixes a to d will be omitted and, for example, the internal circuit 10, the internal node NT, the voltage current It will be described like the conversion circuit 20 .
  • the gate of the NMOS transistor 201a is connected to the internal node NTa, which is the measurement node. That is, the measurement voltage Vout is input to the gate of the NMOS transistor 201a.
  • the selection circuit 30 has switches 301a to 301d. Switches 301a-301d are connected between nodes N1a-N1d and node N2 of current comparator 50, respectively. Nodes N1a-N1d are connected to internal nodes NTa-NTd via voltage-current conversion circuits 20a-20d, respectively, as shown in FIG.
  • the voltage-to-current conversion circuits 20b to 20d are configured similarly to the voltage-to-current conversion circuit 20a, and have series circuits of NMOS transistors and resistance elements between the nodes N1b to N1c and the ground line NL. .
  • Current comparator 50 includes P-type MOS transistors (hereinafter referred to as PMOS transistors) 501 and 502 and NMOS transistors 503 and 504, which constitute two sets of current mirrors. It is connected between the power supply line NP transmitting VDD and the node N2, and the PMOS transistor 502 is connected between the power supply line NP and the node N3.
  • the PMOS transistors 501 and 502 form a current mirror by having their gates commonly connected to the node N2 (that is, the drain of the PMOS transistor 501). Assume that the current ratio of the current mirror is 1:1.
  • NMOS transistor 503 is connected between the node N3 and the ground line NL
  • the NMOS transistor 504 is connected between the node N4 and the ground line NL.
  • NMOS transistors 503 and 504 form a current mirror by having their gates commonly connected to node N4 (that is, the drain of NMOS transistor 504). In the following, it is assumed that the current ratio of the current mirror is 1:1.
  • the reference current source 40 has resistance elements 401 , 402 and 404 , an NMOS transistor 403 and PMOS transistors 405 and 406 .
  • the PMOS transistor 406 is connected between the power supply line NP and the node N4, and the PMOS transistor 405 is connected between the power supply line NP and the node N5.
  • PMOS transistors 405 and 406 form a current mirror by having their gates commonly connected to node N5 (that is, the drain of PMOS transistor 405). Assume that the current ratio of the current mirror is 1:1.
  • the resistance element 401 is connected between the power supply line NP and the node N6, and the resistance element 402 is connected between the ground line NL and the node N6. Therefore, a reference voltage Vref obtained by dividing the power supply voltage VDD by the resistance elements 401 and 402 is generated at the node N6.
  • the selection circuit 30 turns on one of the switches 301a to 301d corresponding to the internal node to be measured, and turns off the remaining switches.
  • the switch 301a is turned on. This creates a path for output current Iout from power supply line NP to ground line NL, including PMOS transistor 501, switch 301a (node N1a), NMOS transistor 201a, and resistance element 202a.
  • the output current Iout is expressed by the following formula (1) using the measured voltage Vout, the electrical resistance value RO of the resistive element 202a, and the gate-source voltage Vgs2 of the NMOS transistor 201a. That is, the voltage-current conversion circuit 20 converts the measured voltage Vout into the output current Iout according to the conversion gain according to Equation (1).
  • (1/RO) corresponds to an example of "first conversion gain”.
  • the output current Iout (Vout ⁇ Vgs2)/RO (1)
  • the output current Iout is copied by a current mirror (1:1 current ratio) by PMOS transistors 501 and 502 .
  • the PMOS transistor 502 supplies a current corresponding to the output current Iout to the node N3.
  • the reference current Iref is expressed by the following equation (2) using the reference voltage Vref of the node N6, the electrical resistance value RP of the resistance element 404, and the gate-source voltage Vgs4 of the NMOS transistor 403. That is, the reference current source 40 converts the reference voltage Vref into the reference current Iref according to the conversion gain according to equation (2).
  • (1/RP) corresponds to an example of "second conversion gain".
  • Iref (Vref ⁇ Vgs4)/RP (2)
  • the reference current Iref is copied by a current mirror by PMOS transistors 405 and 406 (current ratio 1:1) and by NMOS transistors 504 and 503 (current ratio 1:1).
  • the NMOS transistor 503 extracts a current corresponding to the reference current Iref from the node N3.
  • a voltage V3 is generated at the node N3 by amplifying the current difference between the output current Iout and the reference current Iref. Specifically, when Iout>Iref, the voltage V3 becomes a high-level voltage (hereinafter also simply referred to as "H level”) corresponding to the power supply voltage VDD. On the other hand, when Iout ⁇ Iref, the voltage V3 becomes a low level voltage (hereinafter also simply referred to as "L level”) corresponding to the ground voltage GND.
  • the voltage V3 of the node N3 is output as the determination signal Sjd to the terminal 6 that can be contacted from the outside of the semiconductor integrated circuit device 5a.
  • RO (Vto ⁇ Vgs2)/(Vref ⁇ Vgs4) ⁇ RP (4)
  • the voltage stabilization time of the node N3 when the selection circuit 30 switches the measurement voltage Vout in the present embodiment is described in Patent Document 1. Compared with the settling time of the input voltage of the voltage comparison circuit that compares the voltages, it is greatly shortened. In particular, in a configuration in which the circuit scale is suppressed by sharing the current comparator 50 among a plurality of internal nodes, the effect of shortening the test time is great.
  • the reference current Iref which is fixed in the reference current source 40, is used to determine the determination voltage Vout to be compared with the measurement voltage Vout.
  • Vto can be changed equivalently. That is, by changing the conversion gain according to the electrical resistance value RO of the resistance element 202a in the voltage-to-current conversion circuit 20, the reference current Iref is fixed and the normal range of the measured voltage Vout at each internal node NT is adjusted. , the determination voltage Vto can be freely changed. That is, the electrical resistance value RO (that is, the conversion gain) in the voltage-current conversion circuit 20 is determined by reflecting at least the determination voltage Vto, and is preferably set according to Equation (4). This makes it possible to switch the determination voltage for a plurality of measurement voltages with a simple configuration. As a result, the manufacturing cost of the semiconductor integrated circuit device can be reduced.
  • Vgs2 and Vgs4 can be set to the same value by matching the current and transistor size (W/L) ratios between the NMOS transistor 201a and the NMOS transistor 403. can.
  • FIG. 2 shows an example in which the voltage-to-current conversion circuit 20 is configured using NMOS transistors, it is also possible to adopt a configuration that performs voltage-to-current conversion using PMOS transistors.
  • the determination voltage Vto is low, it is preferable to increase the voltage applied to the resistance element 202a (electric resistance value RO) in order to reduce the influence of Vgs2 in equation (1).
  • FIG. 3 shows a circuit diagram for explaining the internal configuration of each block in FIG. 1, according to a modification in which voltage-to-current conversion is performed using PMOS transistors.
  • the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • FIG. 1 shows a circuit diagram for explaining the internal configuration of each block in FIG. 1, according to a modification in which voltage-to-current conversion is performed using PMOS transistors.
  • the voltage-current conversion circuit 20pa has a PMOS transistor 201pa and a resistance element 202a.
  • Resistance element 202a (electric resistance value RO) is connected between power supply line NP and PMOS transistor 201pa.
  • PMOS transistor 201pa is connected between resistance element 202a and node N1a.
  • the gate of PMOS transistor 201pa is connected to internal node NTa to be measured, like NMOS transistor 201 (FIG. 2).
  • the configuration of the selection circuit 30 is the same as in FIG.
  • the current comparator 50p includes NMOS transistors 501p and 502p and PMOS transistors 503p and 504p that form two sets of current mirrors.
  • NMOS transistor 501p is connected between node N2 and ground line NL
  • NMOS transistor 502p is connected between node N3 and ground line NL.
  • NMOS transistors 501p and 501n form a current mirror similar to PMOS transistors 501 and 502 (FIG. 2).
  • the output current Iout is the voltage-current conversion of the measured voltage Vout according to the following equation (5) instead of the equation (1) in FIG. From Equation (5), the conversion gain of the voltage-to-current conversion circuit 20pa is also (1/RO).
  • the reference current source 40 has resistance elements 401, 402, 404, a POS transistor 403p, and NMOS transistors 405p, 406p.
  • NMOS transistor 406p is connected between ground line NL and node N4, and NMOS transistor 405p is connected between ground line NL and node N7.
  • NMOS transistors 405p and 406p form a current mirror similar to PMOS transistors 405 and 406 (FIG. 2).
  • the PMOS transistor 403p is connected between the node N5 and the node N7, and the resistance element 404 (electrical resistance value RP) is connected between the node N5 and the power supply line NP.
  • a path of the reference current Iref corresponding to the reference voltage Vref is generated from the power supply line NP to the ground line NL, including the resistance element 404, the PMOS transistor 403p, and the NMOS transistor 405p.
  • the reference current Iref is expressed by the following formula (6) instead of formula (2) in FIG. From equation (6), the conversion gain at the reference current source 40p is also (1/RP).
  • reference current Iref (VDD ⁇ Vref ⁇ Vgs4)/RP (6)
  • reference current Iref is copied by a current mirror (1:1 current ratio) by PMOS transistors 503p and 504p.
  • the PMOS transistor 503p supplies a current corresponding to the reference current Iref to the node N3, contrary to FIG.
  • the output current Iout generated in the voltage-current conversion circuit 20p is copied by a current mirror (current ratio 1:1) by the NMOS transistors 501p and 502p.
  • a current corresponding to the output current Iout is drawn from the node N3 by the NMOS transistor 502p.
  • a voltage V3 is generated at N3 by amplifying the current difference between the output current Iout and the reference current Iref. Specifically, when the polarity is opposite to that of the current comparator 50 (FIG. 2) and Iref>Iout, the voltage V3 becomes H level (VDD). On the other hand, when Iout>Iref, the voltage V3 becomes L level (GND). Voltage V3 of node N3 is output from current comparator 50p as determination signal Sjd.
  • the ratio between the electrical resistance value RO of the resistor element 202a and the electrical resistance value RP of the resistor element 404 is determined according to the following equation (7).
  • the measured voltage Vout can be compared with the determination voltage Vto by comparing the output current Iout obtained by current-converting the measured voltage Vout with the reference current Iref.
  • the modified example of FIG. 3 when the determination voltage Vto is low, the same effect as described with reference to FIG. 2 can be obtained.
  • FIG. 4 is a circuit diagram illustrating a modification of the voltage-current conversion circuit 20a shown in FIG. Voltage-current conversion circuit 20a# according to Modification 2 of FIG. 4 further includes an operational amplifier buffer 230a in addition to NMOS transistor 201a and resistance element 202a similar to voltage-current conversion circuit 20a (FIG. 2).
  • the operational amplifier buffer 230a has PMOS transistors 2033a and 2034a, NMOS transistors 2031a, 2032a and 2035a, and current sources 2036a and 2037a.
  • the PMOS transistors 2033a and 2034a are connected between the power supply line NP and the nodes N10 and N11, respectively, and the NMOS transistors 2031a and 2032a are connected between the nodes N10 and N11, respectively, and the node N12.
  • Current source 2036a is connected between node N12 and ground line NL. Furthermore, the gates of PMOS transistors 2033a and 2034a are connected to node N10.
  • the PMOS transistors 2033a and 2034a, the NMOS transistors 2031a and 2032a, and the current source 2036a form a current mirror type differential amplifier.
  • the gate of NMOS transistor 2031a is connected to internal node NTa corresponding to the measurement node.
  • the NMOS transistor 2035a is connected between the power supply line NP and the node N13 connected to the gate of the NMOS transistor 2032a.
  • Current source 2037a is connected between node N13 and ground line NL.
  • the gate of NMOS transistor 2035a is connected to node N11.
  • the NMOS transistor 2035a, the NMOS transistor 201a, and the NMOS transistor 403 (reference current source 40) are designed with the same characteristics (transistor size).
  • the gate voltage of the NMOS transistor 2032a becomes equal to the gate voltage of the NMOS transistor 2031a, that is, the measurement voltage Vout. Furthermore, if the current of the current source 2037a is made equal to the reference current Iref, the gate-to-source voltage of the NMOS transistor 2035a becomes equal to Vgs4 in FIG. Therefore, the gate voltage of the NMOS transistor 2035a, that is, the voltage of the node N11, is equivalent to Vout+Vg4.
  • the same gate-source voltage Vgs2 as in FIG. 2 is generated in the NMOS transistor 201a.
  • the voltage applied to the resistance element 202a is Vout+Vgs4-Vg2.
  • FIG. 5 is a circuit diagram illustrating a modification of reference current source 40 shown in FIG.
  • Reference current source 40# according to Modification 2 of FIG. 2 in that an operational amplifier buffer 407 is further included.
  • the operational amplifier buffer 407 is configured similarly to the operational amplifier buffer 230a of FIG.
  • NMOS transistor 4071 The gate of NMOS transistor 4071 is connected to node N6 where reference voltage Vref is generated.
  • NMOS transistor 4075 is connected between power supply line NP and node N14, and current source 4077 is connected between node N14 and ground line NL.
  • the gate of the NMOS transistor 4075 is connected to the node N15, which is the connection point between the PMOS transistor 4074 and the NMOS transistor 4072 .
  • the gate of NMOS transistor 403 is also connected to node N15.
  • the NMOS transistor 4075 is designed with the same characteristics (transistor size and threshold voltage) as the NMOS transistor 403 (reference current source 40).
  • the gate voltage of the NMOS transistor 4072 becomes equal to the gate voltage of the NMOS transistor 4071, that is, the reference voltage Vref. Furthermore, if the current of the current source 4077 is made equal to the current flowing through the resistance element 404 , that is, the reference current Iref, the gate-source voltage of the NMOS transistor 4075 becomes equal to the gate-source voltage Vgs4 of the NMOS transistor 403 . Therefore, the gate voltage of the NMOS transistor 4075, that is, the voltage of the node N15 is equivalent to Vout+Vg4.
  • semiconductor integrated circuit device 5b has N voltage-current conversion circuits 21 instead of N voltage-current conversion circuits 20, as compared with semiconductor integrated circuit device 5a according to the first embodiment. and a selection circuit 31 instead of the selection circuit 30 .
  • Each selection circuit 21 has a node that generates two output currents with different conversion gains for the measurement voltage Vout at the internal node NT corresponding to the measurement node of the corresponding internal circuit 10 . Accordingly, the selection circuit 31 is configured to select one of the (2 ⁇ N) nodes of the N voltage-to-current conversion circuits 21 and connect it to the current comparator 50 .
  • the measured voltage Vout can be compared with two types of determination voltages. For example, by comparing the determination voltage Vtl corresponding to the lower limit of the normal range of the measured voltage Vout and the determination voltage Vtu corresponding to the upper limit of the normal range with the measured voltage Vout, the measured voltage Vout is within the normal range. It is possible to determine whether or not there is
  • voltage-current conversion circuit 21a includes NMOS transistors 203a and 205a and resistance elements 204a and 206a.
  • the gates of NMOS transistors 203a and 205a are commonly connected to internal node NTa. That is, the gate voltages of NMOS transistors 203a and 205a are the measured voltage Vout.
  • the NMOS transistor 203a is connected between the node N1ax and the resistance element 204a, and the resistance element 204a is connected between the NMOS transistor 203a and the ground line NL.
  • Resistive element 204a has an electrical resistance value RU.
  • the NMOS transistor 205a is connected between the node N1ay and the resistance element 206a, and the resistance element 206a is connected between the NMOS transistor 205a and the ground line NL.
  • the resistive element 206a has an electrical resistance value RL.
  • the voltage-current conversion circuit 21a is provided with two "voltage-current conversion units" corresponding to the series circuit of the NMOS transistor 201a and the resistance element 202a in FIG.
  • the number of nodes where Iout is generated is increased to two, nodes N1xa and N1ya. Due to the different electrical resistance values of resistive elements 204a and 206a, the two voltage-to-current conversion units convert a common measured voltage Vout to output currents with different conversion gains.
  • the voltage-to-current conversion circuits 21b to 21d are configured in the same manner as the voltage-to-current conversion circuit 21a.
  • a series circuit (voltage-to-current conversion unit) is arranged respectively.
  • the selection circuit 31 has switches 302a to 302d and 303a to 303d.
  • Switches 303a-303d are connected between one of two nodes of voltage-current conversion circuit 21 (node N1ax in FIG. 7) and node N2, respectively.
  • Switches 302a-302d are connected between the other of the two nodes of voltage-current conversion circuit 21 (node N1ay in FIG. 7) and node N2, respectively.
  • the configuration after the node N2 that is, the configurations of the current comparator 50 and the reference current source 40 are the same as in FIG. 2, so detailed description will not be repeated.
  • the selection circuit 31 turns on one of the switches 302a to 302d and 303a to 303d, and turns off the remaining switches.
  • the output current (Iou) generated at the node N1ax and the output current (Iol ) are sequentially input to the current comparator 50 one by one.
  • the measured voltage Vout can be sequentially compared with the two determination voltages Vtu and Vtl.
  • the switch 302a While the switch 302a is turned on, the remaining switches are turned off. As a result, the path of the output current Iol from the power supply line NP to the ground line NL, including the PMOS transistor 501, the switch 302a (node N1ay), the NMOS transistor 205a, and the resistance element 206a, changes from the output current Iout in FIG. It occurs in the same way as the path.
  • the voltage-to-current conversion circuit 21 can generate a plurality of output currents Iol and Iou with different conversion gains for the common measurement voltage Vout.
  • the respective conversion gains of the output currents Iol and Iou with respect to the measured voltage Vout are adjusted by the electrical resistance values RL and RL.
  • Vtl corresponding to the lower limit of the normal range of the measurement voltage Vout described above
  • Vgs22 in equation (9) indicates the gate-source voltage of the NMOS transistor 205a.
  • Modification 1 and Modification 2 described in Embodiment 1 can also be applied to Embodiment 2. That is, in the voltage-to-current conversion circuit 21, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged, so that the PMOS transistor is replaced. It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 21 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
  • operational amplifier buffers FIGS. 4 and 5
  • Embodiment 3 In the third embodiment, as in the second embodiment, another example of a configuration for comparing the measured voltage Vout with a plurality of determination voltages will be described.
  • FIG. 8 is a block diagram showing the configuration of a semiconductor integrated circuit device 5c according to the third embodiment.
  • semiconductor integrated circuit device 5c has N voltage-current conversion circuits 22 instead of N voltage-current conversion circuits 20, as compared with semiconductor integrated circuit device 5a according to the first embodiment. The difference is that the A control signal Schg for switching the conversion gain is input to each voltage-current conversion circuit 22 .
  • FIG. 9 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 9 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • FIG. 9 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 9 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • the voltage-current conversion circuit 22a has series-connected resistance elements 209a and 201a instead of the resistance element 202a between the source of the NMOS transistor 201a and the ground line NL. It has a connected configuration.
  • Transistor switch 208a is connected in parallel with resistive element 210a. Transistor switch 208a is turned on when control signal Schg is at H level, and turned off when it is at L level.
  • the configuration after the nodes N1a to N1d that is, the configuration of the selection circuit 30, the current comparator 50, and the reference current source 40 is the same as that of FIG. 2, so the detailed description will be repeated. do not have.
  • RO1+RO2 (Vtu ⁇ Vgs2)/(Vref ⁇ Vgs4) ⁇ RP (12)
  • current comparator 50 a current equivalent to reference current Iref is drawn from node N3 by NMOS transistor 503, as in FIG. Therefore, at the node N3, a voltage V3 is generated by amplifying the current difference between the output current Iout whose conversion gain is switched according to the control signal Schg and the reference current Iref.
  • one set of the reference current source 40 and the current comparator 50 is used to suppress an increase in circuit size.
  • the measured voltage Vout can be compared with a plurality of decision voltages.
  • the configuration of the third embodiment it is possible to determine the measured voltage Vout in the same manner as in the second embodiment without using the selection circuit 31 that doubles the number of switches. That is, the same effect as in the second embodiment can be obtained, and the circuit scale can be suppressed as compared with the second embodiment.
  • Modification 1 and Modification 2 described in Embodiment 1 can be applied. That is, in the voltage-current conversion circuit 22, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged to replace the PMOS transistor. It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 22 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
  • operational amplifier buffers FIGS. 4 and 5
  • Embodiment 4 a configuration capable of simultaneously comparing the measurement voltage Vout and a plurality of determination voltages (for example, Vtu and Vtl) described in the second and third embodiments will be described.
  • FIG. 10 is a block diagram showing the configuration of a semiconductor integrated circuit device 5d according to the fourth embodiment.
  • a semiconductor integrated circuit device 5d differs from the semiconductor integrated circuit device 5b (FIG. 6) according to the second embodiment in that a selection circuit 32 is arranged instead of the selection circuit 31. It differs in that a current comparator 51 is arranged instead of the current comparator 50 and that a decision logic circuit 60 is further arranged.
  • the voltage-current conversion circuit 21 and the reference current source 40 are the same as those in the second embodiment (FIG. 6).
  • FIG. 11 shows a circuit diagram for explaining the internal configuration of each block shown in FIG.
  • the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • FIG. 11 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 11 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • the node N1ax of the voltage-current conversion circuit 21a is connected to the node N2x of the current comparator 51 via the switch 305a of the selection circuit 32, and the node N1ay of the voltage-current conversion circuit 21a connects the switch 304a of the selection circuit 32. It is connected to the node N2y of the current comparator 51 via.
  • the selection circuit 32 connects the two nodes (corresponding to Niax and N1ay) of one of the voltage-to-current conversion circuits 21a to 21d to the nodes N2x and N2y of the current comparator 51, respectively. Controlled to connect.
  • the current comparator 51 has PMOS transistors 505 to 508 and NMOS transistors 509 to 511 that form four sets of current mirrors.
  • the PMOS transistors 507 and 508 are connected between the power line NP and the nodes N2y and N3y, respectively.
  • the PMOS transistors 507 and 508 form a current mirror (current ratio is 1:1) by commonly connecting the gates to the node N2y (that is, the drain of the PMOS transistor 507).
  • the switch 305a creates a path for the output current Ioutx from the power supply line NP to the ground line NL, including the PMOS transistor 505, the switch 305a (node N1ax), the NMOS transistor 203a, and the resistance element 204a.
  • the output current Ioutx is equivalent to the output current Iou in FIG.
  • the switch 304a turns on the switch 304a creates a path for the output current Iouty from the power supply line NP to the ground line NL, including the PMOS transistor 507, the switch 304a (node N1ay), the NMOS transistor 205a, and the resistance element 206a.
  • the output current Iouty is equivalent to the output current Iol in FIG.
  • the output currents Ioutx and Iouty respectively corresponding to the output currents Iou and Iol in FIG. 7 are generated at the same time. That is, a plurality of output currents Ioutx and Iouty with different conversion ratios generated by the voltage-current conversion circuit 22 are input in parallel to the current comparator 50 .
  • the output current Ioutx is copied by a current mirror (current ratio 1:1) by PMOS transistors 505 and 506.
  • the output current Iouty is copied by a current mirror (1:1 current ratio) by PMOS transistors 507 and 508 .
  • PMOS transistor 506 supplies a current equivalent to output current Ioutx to node N3x
  • PMOS transistor 508 supplies a current equivalent to output current Iouty to node N3y.
  • the reference current Iref supplied from the reference current source 40 to the node N4 is a current mirror by the NMOS transistors 511 and 509 (current ratio 1:1) and a current mirror by the NMOS transistors 511 and 510 (current ratio 1:1). 1).
  • the PMOS transistor 509 extracts a current equivalent to the reference current Iref from the node N3x.
  • a current equivalent to reference current Iref is drawn from node N3y by PMOS transistor 510 .
  • the voltage V3x is set to a voltage level indicating the comparison result between the measured voltage Vout and the determination voltage Vtu (on the upper limit side).
  • Vout ⁇ Vtu, Iout ⁇ Iref so the determination signal Sidx corresponding to the voltage V3x is set to L level.
  • the voltage V3y is set to a voltage level indicating the comparison result between the measured voltage Vout and the determination voltage Vtl (lower limit side).
  • the determination signal Sidy corresponding to the voltage V3y is set to H level.
  • the decision logic circuit 60 has an inverter 601 and a NAND (negative logical product) gate 602 .
  • Inverter 601 inverts and outputs determination signal Sidx.
  • the output voltage of the inverter 610 and the determination signal Sidy are input to the NAND gate 602 to output the determination signal Sjd.
  • the determination signal Sjd from the determination logic circuit 60 can be output to the terminal 6 that can be contacted from the outside of the semiconductor integrated circuit device 5f.
  • the measured voltage Vout is in the voltage range (normal range) of Vtl ⁇ Vout ⁇ Vtu.
  • the determination signal Sjd is set to L level.
  • the determination signal Sjd H level.
  • the current comparator 52 compares the measured voltage Vout and the determination voltage Vtl (lower limit side), and compares the measured voltage Vout and the determination voltage Vtu (upper limit side). side) can be performed at the same time.
  • the measured voltage Vout can be compared with only one judgment voltage, so that the measured voltage Vout falls within the normal range defined by the upper and lower limits. It is necessary to use the determination signal Sjd at different timings to determine whether or not it will be possible.
  • the measured voltage Vout obtained by comparing the same measured voltage Vout as in the second embodiment with a plurality of judgment voltages, for example, the lower limit value and the upper limit value of the normal range is It is possible to determine whether or not it is within the normal range at a higher speed than in the second embodiment. That is, in the semiconductor integrated circuit device according to the fourth embodiment, in addition to the effect described in the second embodiment, it is possible to further shorten the test time.
  • Modification 1 and Modification 2 described in Embodiment 1 can also be applied to Embodiment 4. That is, in the voltage-current conversion circuit 21, the current comparator 51, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged, so that the PMOS transistor is It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 21 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
  • operational amplifier buffers FIGS. 4 and 5
  • FIG. 12 is a block diagram showing the configuration of a semiconductor integrated circuit device 5e according to the fifth embodiment.
  • a semiconductor integrated circuit device 5e is different from the semiconductor integrated circuit device 5d (FIG. 10) according to the fourth embodiment in that the arrangement of the selection circuit 32 is omitted, and voltage-current conversion is performed.
  • the difference is that a voltage-current conversion circuit 23 is arranged instead of the circuit 21 .
  • An enable signal EN is input to each voltage-current conversion circuit 21 .
  • One of enable signals ENa-ENd is set to H level to select internal nodes NTa-NTd of internal circuits 10a-10d to be measured.
  • the remaining three enable signals ENa-ENd are set to L level.
  • FIG. 13 shows a circuit diagram for explaining the internal configuration of each block shown in FIG.
  • the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • FIG. 13 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 13 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • the two nodes of each voltage-to-current conversion circuit 23 are connected to the nodes N2x and N2y of the current comparator 51 and through switches. connected without For example, nodes N1ax and N1ay of the voltage-current conversion circuit 23a are connected to nodes N2x and N2y of the current comparator 51, respectively, without switches.
  • Embodiment 5 can be combined with Embodiments 1 to 3 and configurations obtained by applying Modification 1 and/or Modification 2 to Embodiments 1 to 3. Specifically, by connecting the enable switch 207a in series with the resistance element 202a in the voltage-current conversion circuit 20a (FIG. 2) and the voltage-current conversion circuit 20a# (FIG. 4), the first embodiment or the modified example 1 Applied Embodiment 1 and Embodiment 5 can be combined. Similarly, by connecting the enable switch 207a in series with the resistance element 202pa in the voltage-current conversion circuit 20pa (FIG. 3), it is possible to combine the first embodiment to which the modification 2 is applied and the fifth embodiment. can.
  • Embodiment 6 In a sixth embodiment, an abnormality handling configuration using the determination results in the fourth and fifth embodiments will be described.
  • FIG. 14 is a block diagram showing the configuration of a semiconductor integrated circuit device 5f according to the sixth embodiment.
  • a semiconductor integrated circuit device 5f includes N internal circuits 10 each composed of an internal circuit (hereinafter also referred to as "first internal circuit") 11 having the same function and an internal circuit (hereinafter also referred to as " 12, and each internal circuit 10 has an abnormality response configuration that switches to the second internal circuit 12 when a failure is detected in the first internal circuit 11.
  • first internal circuit an internal circuit having the same function
  • 12 an internal circuit (hereinafter also referred to as "12”
  • each internal circuit 10 has an abnormality response configuration that switches to the second internal circuit 12 when a failure is detected in the first internal circuit 11.
  • the semiconductor integrated circuit device 5f includes voltage-to-current conversion circuits 21a to 21d, a selection circuit 32, a reference current source 40, a current comparator 51, and a decision logic circuit 60 similar to the semiconductor integrated circuit device 5d (FIG. 10). Further, selection circuits 15a to 15d, a judgment result selection circuit 70, recording devices 80a to 80d, and control logic circuits 9a to 9d are further provided for the above-described abnormality handling configuration.
  • FIG. 15 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 15 as well, the structure corresponding to internal circuit 10a is indicated with a suffix a, and the same structure is arranged corresponding to each internal circuit 10. As shown in FIG. 15
  • the selection circuit 15 has switches 1001a to 1004a.
  • the switches 1001a and 1002a connect the first internal circuit 11a, the second internal circuit 12a, and another actual circuit (not shown) mounted on the semiconductor integrated circuit device 5f to which the output voltage of the internal circuit 10a is input. connected between Switch 1001a is turned on and off according to control signal Aa, while switch 1001a is turned on and off according to control signal /Aa (inverted signal of Aa). As a result, the output voltage of one of the first internal circuit 11a and the second internal circuit 12a is input to the actual circuit.
  • the switch 1003a is connected between the internal node NT1a corresponding to the output node of the first internal circuit 11a and the voltage-current conversion circuit 21a.
  • Switch 1004a is connected between internal node NT2a corresponding to the output node of second internal circuit 12a and voltage-current conversion circuit 21a.
  • the switch 1003a When the switch 1003a is turned on, the voltage of the internal node NT1a, that is, the output voltage of the first internal circuit 11a is input to the voltage-current conversion circuit 21a as the measurement voltage Vout.
  • the switch 1004a when the switch 1004a is turned on, the voltage of the internal node NT2a, that is, the output voltage of the second internal circuit 12a is input to the voltage-current conversion circuit 21a as the measurement voltage Vout.
  • a determination signal Sjd indicating whether the voltage (Vout) is within the range of Vtl ⁇ Vout ⁇ Vtu (normal range) can be obtained at the node N20.
  • the determination result selection circuit 70 has switches 701a to 701d and 702a to 702d.
  • a recording device 80a corresponding to the internal circuit 10a has a first latch circuit 801a, a second latch circuit 802a, and a NAND gate 803a.
  • the switch 701a is connected between the node N20 and the first latch circuit 801a.
  • the first latch circuit 801a is arranged to store the determination signal Sjd for the first internal circuit 11a included in the internal circuit 10a. Therefore, the switch 701a is provided with an ON period in conjunction with the switch 1003a.
  • the switch 702a is connected between the node N20 and the second latch circuit 802a.
  • Second latch circuit 802a is arranged to store determination signal Sjd for second internal circuit 12a included in internal circuit 10a. Therefore, the switch 702a is provided with an ON period in conjunction with the switch 1004a.
  • each of the recording devices 80b to 80d arranged corresponding to each of the internal circuits 10b to 10d also has a first latch circuit 801 for storing the judgment result of the first internal circuit 11, and , and a second latch circuit 802 for storing the determination result of the second internal circuit 12 .
  • a switch 701 leading to the first latch circuit and a second latch circuit are provided.
  • a switch 702 is provided.
  • the NAND gate 803a receives the latch data S11a of the first latch circuit 801a and the latch data S12a of the second latch circuit 802a, and outputs the internal circuit normal signal /Ea.
  • the control logic circuit 9a has a NAND gate 901a and an inverter 902a.
  • the NAND gate 901a receives the latch data S11a and the inverted data of the latch data S12a as inputs, and outputs a control signal Aa for the switch 1001a.
  • Inverter 902a inverts the output signal of NAND gate 901a to output control signal /Aa for switch 1002a.
  • the output voltage of the first internal circuit 11a and the output voltage of the second internal circuit 12a are determined in order.
  • the determination signal Sjd indicating whether the output voltage (Vout) of the first internal circuit 11a is within the range of Vtl ⁇ Vout ⁇ Vtu (normal range) is output to the first It is input to the latch circuit 801a. If the determination result of the first internal circuit 11a is normal, the latch data S11a of the first latch circuit 801a becomes L level.
  • the determination signal Sjd indicating whether the output voltage (Vout) of the second internal circuit 12a is within the range of Vtl ⁇ Vout ⁇ Vtu (normal range) is generated. 2 is input to the latch circuit 802a. If the determination result of the first internal circuit 11a is normal, the latch data S12a of the second latch circuit 802a becomes L level.
  • the first latch circuit 801a corresponds to an example of "first storage circuit”
  • the latch data S11a corresponds to an example of "first information”.
  • the second latch circuit 802a corresponds to an example of the "second storage circuit”
  • the latch data S12a corresponds to an example of the "second information”.
  • the switches 1003a and 1004a in the selection circuit 15a can constitute an embodiment of the "measurement selection circuit”.
  • switches 1003b, 1004b, 304b, 305b, and 701b corresponding to the internal circuit 10b are selected so that the output voltage of the first internal circuit 11b and the output voltage of the second internal circuit 12b are sequentially determined.
  • 702b are turned on and off in the same manner as switches 1003a, 1004a, 304a, 305a, 701a and 702a at the test timing of internal circuit 10a.
  • FIG. 17 shows a chart for explaining the operation of the abnormality detection configuration with respect to the judgment results of the first and second internal circuits. As shown in FIG. 17, there are cases 1 to 4 in combination of determination results of the first and second internal circuits.
  • control signal Aa is set to H level
  • control signal /Aa is set to L level. That is, the output of the first internal circuit 11a is transmitted to the actual circuit by the switch 1001a.
  • the internal circuit abnormality signal /Ea is set to H level.
  • the first internal circuit 11a is used as the default circuit for actual use, and when the first internal circuit 11a fails, the second internal circuit 12a for backup is used as the circuit for actual use on condition that the determination result is normal.
  • An abnormality handling configuration that automatically switches to .
  • the operation of semiconductor integrated circuit device 5e can be continued even when a failure occurs in the internal circuit.
  • the internal circuit abnormality signal /Ea is set to L level, thereby notifying that the internal circuit 10a cannot be used.
  • the semiconductor integrated circuit device As described above, according to the semiconductor integrated circuit device according to the sixth embodiment, it is possible to automatically detect a failure in the internal circuit 10 and switch over to the backup circuit when a failure occurs. In addition to the effect described in Embodiment 4, it is possible to improve the reliability of circuit operation continuation. Further, by monitoring the control signals Aa, /Aa and the internal circuit abnormality signal /Ea from the outside of the semiconductor integrated circuit device 5f, the failure state of each internal circuit 10 can also be grasped. That is, the control signals Aa, /Aa and the internal circuit error signal /Ea can be output to terminals (not shown) that can be contacted from the outside of the semiconductor integrated circuit device 5f, similarly to the terminal 6. FIG.
  • FIG. 15 illustrates an example in which the abnormality handling configuration of the sixth embodiment is applied to the semiconductor integrated circuit device of the fourth embodiment.
  • modifications 1 and 2 it is possible to further combine the sixth embodiment.
  • the number of latch circuits of the recording device 80 and the content of the logic operation in the control logic circuit 9 can be changed as needed.
  • Embodiments 1 to 3 in order to determine normality and ⁇ using the same determination result related to the voltage range (Vtl ⁇ Vout ⁇ Vtu) as in Embodiment 4, the determination voltages Vtl and Vtu Four latch circuits are required in each recording device 80 in order to hold the determination signal Sjd for comparison with each other.
  • the logic in the control logic circuit 9 is adjusted so that the control signals Aa and /Aa and the internal circuit abnormality signal /Ea similar to those in FIG. It is necessary to change the operation.
  • Embodiment 7 In the seventh embodiment, a configuration will be described in which two voltage differences (voltage differences) relating to measurement nodes of an internal circuit are used as measurement voltages, ie, determination targets.
  • FIG. 18 is a block diagram showing the configuration of a semiconductor integrated circuit device 5g according to the seventh embodiment.
  • a semiconductor integrated circuit device 5g differs from the semiconductor integrated circuit device 5b according to the fourth embodiment (FIG. 10) in that two voltages Vout1 and Vout2 are applied from the internal circuit 10a. It differs in that Vout2 is output and in that a voltage-current conversion circuit 24a is arranged instead of the voltage-current conversion circuit 21a. Further, an upper peak detector 13a and a lower peak detector 14a are provided for the internal node NTa (output voltage Vout) of the internal circuit 10a, which corresponds to the "measurement node".
  • the upper peak detector 13a extracts the maximum value (upper peak value) of the output voltage Vout and outputs it as the first voltage Vout1.
  • the lower peak detector 14a extracts the minimum value (lower peak value) of the output voltage Vout and outputs it as the second voltage Vout2.
  • Vout1-Vout2 represents the peak-to-peak value of the AC voltage.
  • a first voltage Vout1 and a second voltage Vout2 are input to the voltage-current conversion circuit 24a.
  • the voltage-current conversion circuit 24a converts the voltage difference (Vout1-Vout2) between the first voltage Vout1 and the second voltage Vout2 into output currents Ioutx and Iouty in FIG. 11 with different conversion gains.
  • the selection circuit 32, the current comparator 50, the reference current source 40, and the decision logic circuit 60, which are shared by the N internal circuits 10, are the same as in the fourth embodiment (FIG. 10).
  • the structure corresponding to internal circuit 10a is representatively shown with the suffix a.
  • FIG. 19 shows a circuit diagram for explaining the configuration of the voltage-current conversion circuit according to Embodiment 7, that is, the voltage-current conversion circuit 24a of FIG.
  • the NMOS transistor 2301a is connected between the power supply line NP and the node N31, and the current source 2302a is connected between the node N31 and the ground line NL.
  • a second voltage Vout2 is input to the gate of the NMOS transistor 2301a.
  • a current source 2303a is connected between the power supply line NP and the node N32, and a PMOS transistor 2304a is connected between the node N32 and the ground line NL.
  • a first voltage Vout1 is input to the gate of the PMOS transistor 2304a.
  • the NMOS transistor 2305a is connected between the node N1ax and the node N33.
  • Resistive element 2306a is connected between node N33 and PMOS transistor 2307a, and PMOS transistor 2307a is connected between resistive element 2306a and ground line NL.
  • Resistive element 2306a has an electrical resistance value RDU.
  • the NMOS transistor 2308a is connected between the node N1ay and the node N34.
  • Resistive element 2309a is connected between node N34 and PMOS transistor 2310a, and PMOS transistor 2310a is connected between resistive element 2309a and ground line NL.
  • Resistance element 2309a has an electrical resistance value RDL.
  • NMOS transistors 2305a and 2038a are commonly connected to node N32.
  • PMOS transistors 2307a and 2310a are commonly connected to node N31.
  • the NMOS transistor 2308a, the resistance element 2309a, and the PMOS transistor 2310a are omitted from the voltage-current conversion circuit 24a of FIG. 19, and the NMOS transistor 2305a is connected between the node N1a and the node N33.
  • the electrical resistance value of the resistive element 2306a at that time can be obtained by replacing the determination voltage Vtu with the determination voltage Vdt in the equation (15).
  • the first voltage Vout1 and the second voltage Vout2 related to the measurement node of the internal circuit 10 are two voltages at different timings of the same node. It is also possible to take the voltages as the first voltage Vout1 and the second voltage Vout2 and the voltage difference between the two internal nodes as the measured voltage Vout.
  • the circuits subsequent to the nodes N1ax and N1ay can be the same as those of any one of the first to sixth embodiments.
  • the difference between the two voltages (voltage difference) associated with the internal circuit 10 can be determined in the same manner as in the first to sixth embodiments, or an abnormality handling configuration based on the determination result can be performed.
  • the voltage-to-current conversion circuit 25a further includes a PMOS transistor 2312a, an NMOS transistor 2313a, and current sources 2311a and 2314a compared to the voltage-to-current conversion circuit 24a shown in FIG. and that the connection destinations of the gates of the NMOS transistor 2308a and the PMOS transistor 2310a are changed.
  • the current source 2311a is connected between the power supply line NP and the node N35, and the PMOS transistor 2312a is connected between the node N35 and the ground line NL.
  • a second voltage Vout2 is input to the gate of the PMOS transistor 2312a in common with the gate of the NMOS transistor 2301a.
  • the NMOS 2313a is connected between the power supply line NP and the node N36, and the current source 2314a is connected between the node N36 and the ground line NL.
  • a first voltage Vout1 is input to the gate of the NMOS transistor 2313a in common with the gate of the PMOS transistor 2304a.
  • the gate of the NMOS transistor 2308 is connected to the node N35 generating a voltage according to the second voltage Vout2, and the gate of the PMOS transistor 2310a is connected to the node N36 generating a voltage according to the first voltage Vout1. Therefore, a voltage according to the voltage difference (Vout2-Vout1) is applied across the resistance element 2309a. As a result, the output current Iouty becomes a current obtained by converting the voltage difference (Vout2-Vout1) by the conversion gain according to the electrical resistance value RDL.
  • the polarity (positive/negative) of the conversion gain of the output current Iouty is inverted with respect to the voltage-current conversion circuit 24a. Therefore, as a whole, it can be understood that the polarity (positive/negative) of the determination voltage Vdl can be reversed and compared with the voltage difference (Vout1-Vout2) as compared with the case of using the voltage-current conversion circuit 24a.
  • the voltage-current conversion circuit 25a shown in FIG. 20 even if the lower limit of the normal range of the voltage difference (Vout1-Vout2) is a negative voltage, the same as in the first to sixth embodiments , the voltage difference between the first voltage Vout1 and the second voltage Vout2 can be compared with the determination voltage as the measurement voltage Vout.
  • the current ratio of each current mirror is 1:1, but other current ratios are also possible.
  • the current ratio A of the output current Iout generated in the current comparator 50 transistors, 51 (nodes N3, N3x, N3y) to the output currents Iout, Ioutx, Iouty of the voltage-current conversion circuit 20, etc., and the reference (A /B) Multiplication is required.
  • two NMOS transistors having a transistor size equivalent to that of the NMOS transistor 403 are connected in parallel to configure the NMOS transistor 201a, so that the ratio of current and transistor size can be made uniform between the NMOS transistor 201a and the NMOS transistor 403. can be done.

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Abstract

A voltage-current conversion circuit (20a) generates an output current (Iout) by converting a measured voltage (Vout) at a measurement node (NTa) inside a semiconductor integrated circuit device in accordance with a conversion gain dependent on an electric resistance value (RO) determined to reflect a determination voltage. A reference current source (40) outputs a predetermined reference current (Iref). A current comparator (50) outputs a determination signal (Sjd) indicating the result of comparing the output current (Iout) and the reference current (Iref).

Description

半導体集積回路装置Semiconductor integrated circuit device
　本開示は、半導体集積回路装置に関する。 The present disclosure relates to semiconductor integrated circuit devices.
　半導体集積回路に代表されるＩＣ（Integrated　Circuit）では、アナログ回路から内部ノードに対して電圧が正しく出ているかを確認することが、故障を検出するために重要な要素である。最もシンプルには、電圧モニタ用の外部端子を設けるとともに、測定対象の内部ノードと当該外部端子とを接続することによって、外部端子を介して、内部ノードの電圧を測定することができる。この際には、外部端子を、複数の内部ノードと順々に接続することで、外部端子を共有して複数の内部ノードの電圧を測定することができる。 In an IC (Integrated Circuit) represented by a semiconductor integrated circuit, checking whether the voltage is correctly output from the analog circuit to the internal node is an important factor in detecting failures. Most simply, by providing an external terminal for voltage monitoring and connecting the internal node to be measured to the external terminal, the voltage of the internal node can be measured via the external terminal. In this case, by sequentially connecting the external terminal to the plurality of internal nodes, the voltages of the plurality of internal nodes can be measured by sharing the external terminal.
　ＩＣの大規模化に伴い、電圧を確認したい内部ノードが増大すると、内部ノードの電圧確認のためのテスト時間が増大する。この様なテストを効率化するための技術として、特開２００６－２３４５７７号公報（特許文献１）には、ＩＣ内部に電圧比較器を設けて、アナログ集積回路のある特定の回路ノードのＤＣ電圧が、ある範囲に入っているどうかを判定して、当該判定結果をＩＣ外部に出力する構成が記載されている。 As the size of the IC increases, the number of internal nodes whose voltages need to be checked increases, and the test time for checking the voltages of the internal nodes increases. As a technique for improving the efficiency of such a test, Japanese Patent Application Laid-Open No. 2006-234577 (Patent Document 1) discloses that a voltage comparator is provided inside an IC to detect a DC voltage at a specific circuit node of an analog integrated circuit. is within a certain range, and the determination result is output to the outside of the IC.
特開２００６－２３４５７７号公報JP-A-2006-234577
　特許文献１では、測定対象の内部ノード数が多い場合には、複数の内部ノードと電圧比較器との間に切替スイッチ（選択回路）を配置して、複数の内部ノードで電圧比較器を共有する構成がチップサイズの面から求められる。 In Patent Document 1, when the number of internal nodes to be measured is large, a changeover switch (selection circuit) is arranged between a plurality of internal nodes and a voltage comparator, and the voltage comparator is shared by the plurality of internal nodes. A configuration that does so is required from the aspect of chip size.
　しかしながら、この構成では切替スイッチによって電圧比較器と接続される内部ノードを切り替えた場合に、電圧比較器への入力電圧が静定するまでの時間が、正確な判定結果を得るために必要となる。この結果、測定対象が多くなると、テスト時間が長くなることが懸念される。 However, in this configuration, when the changeover switch switches the internal node connected to the voltage comparator, it takes time for the input voltage to the voltage comparator to stabilize in order to obtain an accurate determination result. . As a result, it is feared that the more objects to be measured, the longer the test time.
　又、内部ノード毎に規格値、即ち、正常と判定すべきで電圧範囲が異なるため、電圧比較器側において、内部ノードの電圧と比較される基準電圧も切り替えることが必要になる。この結果、基準電圧を切替えるための構成を追加することによる回路規模の増大が懸念される他、基準電圧の切替についても静定時間が必要になることで、テスト時間が更に長くなることも懸念される。 In addition, since the standard value, that is, the voltage range that should be determined as normal differs for each internal node, it is necessary to switch the reference voltage to be compared with the voltage of the internal node on the voltage comparator side. As a result, there is concern that adding a configuration for switching the reference voltage will increase the circuit size, and that switching the reference voltage will also require a settling time, further lengthening the test time. be done.
　本開示は、このような問題点を解決するためになされたものであって、本開示の目的は、半導体集積回路装置の内部ノードの電圧の正常判定を、簡易な回路構成で高速化することである。 The present disclosure has been made to solve such problems, and an object of the present disclosure is to speed up the normality determination of the voltage of the internal node of a semiconductor integrated circuit device with a simple circuit configuration. is.
　本開示のある局面では、半導体集積回路装置が提供される。半導体集積回路装置は、複数の電圧電流変換回路と、基準電流源と、電流比較器とを備える。各電圧電流変換回路は、半導体集積回路装置の内部の少なくとも１つの測定ノードの電圧に従う測定電圧を第１変換ゲインに従って電圧電流変換して少なくとも１つの出力電流を生成する。基準電流源は、予め定められた基準電流を出力する。電流比較器は、複数の電圧電流変換回路のうちの選択された電圧電流変換回路から入力された少なくとも１つの出力電流のそれぞれと基準電流との比較結果に従う少なくとも１つの判定信号を出力する。 A semiconductor integrated circuit device is provided in one aspect of the present disclosure. A semiconductor integrated circuit device includes a plurality of voltage-current conversion circuits, a reference current source, and a current comparator. Each voltage-to-current converter circuit voltage-to-current converts a measured voltage according to the voltage of at least one measurement node inside the semiconductor integrated circuit device according to a first conversion gain to generate at least one output current. A reference current source outputs a predetermined reference current. The current comparator outputs at least one determination signal according to the comparison result between each of at least one output current input from a voltage-current conversion circuit selected from among the plurality of voltage-current conversion circuits and a reference current.
　本開示によれば、測定電圧を電圧電流変換した出力電流と基準電流とを電流比較器によって比較することで測定電圧を判定電圧と比較できる、複数の電圧電流変換器の選択の切替の際に、電流比較器に入力される出力電流の静定に要する時間を短くすることができる。この結果、半導体集積回路装置の内部ノードの電圧の正常判定を、簡易な回路構成で高速化することができる。 According to the present disclosure, when switching between a plurality of voltage-to-current converters, the current comparator can compare the measured voltage with the judgment voltage by comparing the output current obtained by voltage-to-current conversion of the measured voltage with the reference current. , the time required to stabilize the output current input to the current comparator can be shortened. As a result, it is possible to speed up the normality judgment of the voltage of the internal node of the semiconductor integrated circuit device with a simple circuit configuration.
実施の形態１に係る半導体集積回路装置の構成を示すブロック図である。1 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a first embodiment; FIG. 図１に記載された各ブロックの内部構成を説明するための回路図である。2 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 1; FIG. 図１に記載された各ブロックの実施の形態１の変形例１に係る内部構成を説明するための回路図である。FIG. 2 is a circuit diagram for explaining an internal configuration of each block shown in FIG. 1 according to Modification 1 of Embodiment 1; 実施の形態１の変形例１に係る電圧電流変換回路の構成を説明する回路図である。FIG. 10 is a circuit diagram illustrating a configuration of a voltage-current conversion circuit according to Modification 1 of Embodiment 1; 実施の形態１の変形例１に係る基準電流源の構成を説明する回路図である。FIG. 10 is a circuit diagram illustrating the configuration of a reference current source according to Modification 1 of Embodiment 1; 実施の形態２に係る半導体集積回路装置の構成を示すブロック図である。3 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a second embodiment; FIG. 図６に記載された各ブロックの内部構成を説明するための回路図である。7 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 6; FIG. 実施の形態３に係る半導体集積回路装置の構成を示すブロック図である。3 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a third embodiment; FIG. 図８に記載された各ブロックの内部構成を説明するための回路図である。9 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 8; FIG. 実施の形態４に係る半導体集積回路装置の構成を示すブロック図である。12 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a fourth embodiment; FIG. 図１０に記載された各ブロックの内部構成を説明するための回路図である。11 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 10; FIG. 実施の形態５に係る半導体集積回路装置の構成を示すブロック図である。FIG. 11 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a fifth embodiment; 図１２に記載された各ブロックの内部構成を説明するための回路図である。13 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 12; FIG. 実施の形態６に係る半導体集積回路装置の構成を示すブロック図である。FIG. 11 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a sixth embodiment; 図１４に記載された各ブロックの内部構成を説明するための回路図である。15 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 14; FIG. 実施の形態６に係る半導体集積回路装置の動作を説明するための信号波形図である。FIG. 13 is a signal waveform diagram for explaining the operation of the semiconductor integrated circuit device according to the sixth embodiment; 第１及び第２内部回路の判定結果に対する異常検出構成の動作を説明する図表である。4 is a diagram for explaining the operation of the abnormality detection configuration with respect to the judgment results of the first and second internal circuits; 実施の形態７に係る半導体集積回路装置の構成を示すブロック図である。FIG. 14 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a seventh embodiment; 実施の形態７に係る電圧電流変換回路の構成を説明する回路図である。FIG. 12 is a circuit diagram illustrating the configuration of a voltage-current conversion circuit according to Embodiment 7; 実施の形態７の変形例に係る電圧電流変換回路の構成を説明する回路図である。FIG. 20 is a circuit diagram illustrating a configuration of a voltage-current conversion circuit according to a modification of Embodiment 7;
　以下に、本開示の実施の形態について、図面を参照して詳細に説明する。なお、以下では、図中の同一又は相当部分には同一符号を付して、その説明は原則的に繰返さないものとする。 Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following description, the same reference numerals are given to the same or corresponding parts in the drawings, and the description thereof will not be repeated in principle.
　実施の形態１．
　図１は、実施の形態１に係る半導体集積回路装置５ａの構成を示すブロック図である。 Embodiment 1.
FIG. 1 is a block diagram showing the configuration of a semiconductor integrated circuit device 5a according to the first embodiment.
　図１を参照して、半導体集積回路装置５ａは、Ｎ個（Ｎ：２以上の整数）の内部回路１０と、Ｎ個の電圧電流変換回路２０と、選択回路３０と、基準電流源４０と、電流比較器５０とを備える。以下では、Ｎ＝４の例を説明するので、半導体集積回路装置５ａは、４個の内部回路１０ａ～１０ｄと、電圧電流変換回路２０ａ～２０ｄを備えている。 Referring to FIG. 1, semiconductor integrated circuit device 5a includes N internal circuits 10 (where N is an integer equal to or greater than 2), N voltage-current conversion circuits 20, a selection circuit 30, and a reference current source 40. , and a current comparator 50 . Since an example of N=4 will be described below, the semiconductor integrated circuit device 5a includes four internal circuits 10a to 10d and voltage-to-current conversion circuits 20a to 20d.
　内部回路１０ａ～１０ｄは、内部ノードＮＴａ～ＮＴｄに電圧を生成する。即ち、内部ノードＮＴａ～ＮＴｄが「測定ノード」であり、電流比較器５０からは、測定ノードの電圧（図１では、内部回路１０ａの出力電圧Ｖｏｕｔ）と、予め定められた判定電圧Ｖｔｏとの比較結果に従う、２値の判定信号Ｓｊｄが出力される。実施の形態１では、判定信号Ｓｊｄによって、出力電圧Ｖｏｕｔが、予め定められた判定電圧よりも高い範囲及び低い範囲のいずれに含まれるか否かが示される。判定電圧Ｖｔｏは、出力電圧（測定電圧）Ｖｏｕｔの正常範囲の境界値に設定することができる。 The internal circuits 10a-10d generate voltages at the internal nodes NTa-NTd. That is, the internal nodes NTa to NTd are "measurement nodes", and the current comparator 50 outputs voltages of the measurement nodes (in FIG. 1, the output voltage Vout of the internal circuit 10a) and a predetermined determination voltage Vto. A binary determination signal Sjd is output according to the comparison result. In the first embodiment, the determination signal Sjd indicates whether the output voltage Vout is included in a range higher or lower than a predetermined determination voltage. The determination voltage Vto can be set to a boundary value of the normal range of the output voltage (measurement voltage) Vout.
　図２には、図１に記載された各ブロックの内部構成を説明するための回路図が示される。内部回路１０ａ～１０ｄ（内部ノードＮＴａ～ＮＴｄ）に対する測定構成は同様であるので、図２では、内部回路１０ａ（内部ノードＮＴａ）に対応する構成が添字ａを付して代表的に示されるが、同様の構成が、内部回路１０ｂ～１０ｄに対応して配置されている。 FIG. 2 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. Since the measurement configuration for the internal circuits 10a to 10d (internal nodes NTa to NTd) is the same, FIG. , similar configurations are arranged corresponding to the internal circuits 10b to 10d.
　又、以下では、内部回路１０ａ～１０ｄにそれぞれ対応する要素を区別せずに包括的に表記する場合には、添字ａ～ｄを省略して、例えば、内部回路１０、内部ノードＮＴ、電圧電流変換回路２０の様に記載することとする。 Further, in the following description, when the elements corresponding to the internal circuits 10a to 10d are not distinguished, the suffixes a to d will be omitted and, for example, the internal circuit 10, the internal node NT, the voltage current It will be described like the conversion circuit 20 .
　図２では、電圧電流変換回路２０ａ～２０ｄのうちの電圧電流変換回路２０ａが選択されて、電圧電流変換回路２０ａによって生成された出力電流Ｉｏｕｔが電流比較器５０に入力される例が示されている。このとき、測定ノードである内部ノードＮＴａには、内部回路１０ａからの出力電圧Ｖｏｕｔが現れる。以下では、判定電圧と比較される電圧を測定電圧と称する。従って、出力電圧Ｖｏｕｔについて、以下では、測定電圧Ｖｏｕｔとも称する。 FIG. 2 shows an example in which the voltage-current conversion circuit 20a is selected from among the voltage-current conversion circuits 20a to 20d, and the output current Iout generated by the voltage-current conversion circuit 20a is input to the current comparator 50. there is At this time, the output voltage Vout from the internal circuit 10a appears at the internal node NTa, which is the measurement node. Hereinafter, the voltage to be compared with the determination voltage is referred to as measurement voltage. Therefore, the output voltage Vout is hereinafter also referred to as the measured voltage Vout.
　電圧電流変換回路２０ａは、Ｎ型のＭＯＳ（Metal-oxide　Semiconductor）トランジスタ（以下、ＮＭＯＳトランジスタと表記する）２０１ａと、抵抗素子２０２ａとを含む。ＮＭＯＳトランジスタ２０１ａは、ノードＮ１ａ及び抵抗素子２０２ａの間に接続される。抵抗素子２０２ａは、ＮＭＯＳトランジスタ２０１ａと、接地電圧ＧＮＤを伝達する接地ラインＮＬとの間に接続される。抵抗素子２０２ａは、電気抵抗値ＲＯを有する。 The voltage-current conversion circuit 20a includes an N-type MOS (Metal-oxide Semiconductor) transistor (hereinafter referred to as an NMOS transistor) 201a and a resistance element 202a. NMOS transistor 201a is connected between node N1a and resistance element 202a. Resistance element 202a is connected between NMOS transistor 201a and ground line NL transmitting ground voltage GND. The resistive element 202a has an electrical resistance value RO.
　ＮＭＯＳトランジスタ２０１ａのゲートは、測定ノードである内部ノードＮＴａと接続される。即ち、ＮＭＯＳトランジスタ２０１ａのゲートには、測定電圧Ｖｏｕｔが入力される。 The gate of the NMOS transistor 201a is connected to the internal node NTa, which is the measurement node. That is, the measurement voltage Vout is input to the gate of the NMOS transistor 201a.
　選択回路３０は、スイッチ３０１ａ～３０１ｄを有する。スイッチ３０１ａ～３０１ｄは、ノードＮ１ａ～Ｎ１ｄと、電流比較器５０のノードＮ２との間にそれぞれ接続される。ノードＮ１ａ～Ｎ１ｄは、図１に示される様に、電圧電流変換回路２０ａ～２０ｄを介して、内部ノードＮＴａ～ＮＴｄとそれぞれ接続される。電圧電流変換回路２０ｂ～２０ｄについても、電圧電流変換回路２０ａと同様に構成されており、ノードＮ１ｂ～Ｎ１ｃと、接地ラインＮＬとの間に、ＮＭＯＳトランジスタ及び抵抗素子の直列回路を有している。 The selection circuit 30 has switches 301a to 301d. Switches 301a-301d are connected between nodes N1a-N1d and node N2 of current comparator 50, respectively. Nodes N1a-N1d are connected to internal nodes NTa-NTd via voltage-current conversion circuits 20a-20d, respectively, as shown in FIG. The voltage-to-current conversion circuits 20b to 20d are configured similarly to the voltage-to-current conversion circuit 20a, and have series circuits of NMOS transistors and resistance elements between the nodes N1b to N1c and the ground line NL. .
　電流比較器５０は、２組のカレントミラーを構成する、Ｐ型のＭＯＳトランジスタ（以下、ＰＭＯＳトランジスタと表記する）５０１，５０２と、ＮＭＯＳトランジスタ５０３，５０４とを含む、ＰＭＯＳトランジスタ５０１は、電源電圧ＶＤＤを伝達する電源ラインＮＰと、ノードＮ２の間に接続され、ＰＭＯＳトランジスタ５０２は、電源ラインＮＰ及びノードＮ３の間に接続される。ＰＭＯＳトランジスタ５０１及び５０２は、ゲートがノードＮ２（即ち、ＰＭＯＳトランジスタ５０１のドレイン）と共通接続されることでカレントミラーを構成する。当該カレントミラーの電流比は１：１であるものとする。 Current comparator 50 includes P-type MOS transistors (hereinafter referred to as PMOS transistors) 501 and 502 and NMOS transistors 503 and 504, which constitute two sets of current mirrors. It is connected between the power supply line NP transmitting VDD and the node N2, and the PMOS transistor 502 is connected between the power supply line NP and the node N3. The PMOS transistors 501 and 502 form a current mirror by having their gates commonly connected to the node N2 (that is, the drain of the PMOS transistor 501). Assume that the current ratio of the current mirror is 1:1.
　ＮＭＯＳトランジスタ５０３は、ノードＮ３及び接地ラインＮＬの間に接続され、ＮＭＯＳトランジスタ５０４は、ノードＮ４及び接地ラインＮＬの間に接続される。ＮＭＯＳトランジスタ５０３及び５０４は、ゲートがノードＮ４（即ち、ＮＭＯＳトランジスタ５０４のドレイン）と共通接続されることでカレントミラーを構成する。以下では、当該カレントミラーの電流比は１：１であるものとする。 The NMOS transistor 503 is connected between the node N3 and the ground line NL, and the NMOS transistor 504 is connected between the node N4 and the ground line NL. NMOS transistors 503 and 504 form a current mirror by having their gates commonly connected to node N4 (that is, the drain of NMOS transistor 504). In the following, it is assumed that the current ratio of the current mirror is 1:1.
　基準電流源４０は、抵抗素子４０１，４０２，４０４と、ＮＭＯＳトランジスタ４０３と、ＰＭＯＳトランジスタ４０５，４０６とを有する。 The reference current source 40 has resistance elements 401 , 402 and 404 , an NMOS transistor 403 and PMOS transistors 405 and 406 .
　ＰＭＯＳトランジスタ４０６は、電源ラインＮＰ及びノードＮ４の間に接続され、ＰＭＯＳトランジスタ４０５は、電源ラインＮＰ及びノードＮ５の間に接続される。ＰＭＯＳトランジスタ４０５及び４０６は、ゲートがノードＮ５（即ち、ＰＭＯＳトランジスタ４０５のドレイン）と共通接続されることでカレントミラーを構成する。当該カレントミラーの電流比は１：１であるものとする。 The PMOS transistor 406 is connected between the power supply line NP and the node N4, and the PMOS transistor 405 is connected between the power supply line NP and the node N5. PMOS transistors 405 and 406 form a current mirror by having their gates commonly connected to node N5 (that is, the drain of PMOS transistor 405). Assume that the current ratio of the current mirror is 1:1.
　ＮＭＯＳトランジスタ４０３は、ノードＮ５及びノードＮ７の間に接続され、抵抗素子４０４は、ノードＮ７及び接地ラインＮＬの間に接続される。抵抗素子４０４は、電気抵抗値ＲＰを有する。 The NMOS transistor 403 is connected between the node N5 and the node N7, and the resistive element 404 is connected between the node N7 and the ground line NL. Resistive element 404 has an electrical resistance value RP.
　抵抗素子４０１は、電源ラインＮＰ及びノードＮ６の間に接続され、抵抗素子４０２は、接地ラインＮＬ及びノードＮ６の間に接続される。従って、ノードＮ６には、電源電圧ＶＤＤを抵抗素子４０１及び４０２で分圧した基準電圧Ｖｒｅｆが発生する。 The resistance element 401 is connected between the power supply line NP and the node N6, and the resistance element 402 is connected between the ground line NL and the node N6. Therefore, a reference voltage Vref obtained by dividing the power supply voltage VDD by the resistance elements 401 and 402 is generated at the node N6.
　次に、図２に示された回路の動作を説明する。
　選択回路３０は、スイッチ３０１ａ～３０１ｄのうちの、測定対象の内部ノードに対応する１つのスイッチをオンする一方で、残りのスイッチをオフする。図２の例では、スイッチ３０１ａがオンされる。これにより、電源ラインＮＰから接地ラインＮＬへ、ＰＭＯＳトランジスタ５０１、スイッチ３０１ａ（ノードＮ１ａ）、ＮＭＯＳトランジスタ２０１ａ、及び、抵抗素子２０２ａを含む、出力電流Ｉｏｕｔの経路が生じる。 The operation of the circuit shown in FIG. 2 will now be described.
The selection circuit 30 turns on one of the switches 301a to 301d corresponding to the internal node to be measured, and turns off the remaining switches. In the example of FIG. 2, the switch 301a is turned on. This creates a path for output current Iout from power supply line NP to ground line NL, including PMOS transistor 501, switch 301a (node N1a), NMOS transistor 201a, and resistance element 202a.
　出力電流Ｉｏｕｔは、測定電圧Ｖｏｕｔ、抵抗素子２０２ａの電気抵抗値ＲＯ、及び、ＮＭＯＳトランジスタ２０１ａのゲートソース間電圧Ｖｇｓ２を用いて、下記の式（１）で示される。即ち、電圧電流変換回路２０は、式（１）に従う変換ゲインに従って、測定電圧Ｖｏｕｔを出力電流Ｉｏｕｔに変換する。式（１）では、（１／ＲＯ）が「第１変換ゲイン」の一実施例に相当する。 The output current Iout is expressed by the following formula (1) using the measured voltage Vout, the electrical resistance value RO of the resistive element 202a, and the gate-source voltage Vgs2 of the NMOS transistor 201a. That is, the voltage-current conversion circuit 20 converts the measured voltage Vout into the output current Iout according to the conversion gain according to Equation (1). In Equation (1), (1/RO) corresponds to an example of "first conversion gain".
　Ｉｏｕｔ＝（Ｖｏｕｔ－Ｖｇｓ２）／ＲＯ　　…（１）
　出力電流Ｉｏｕｔは、ＰＭＯＳトランジスタ５０１及び５０２によるカレントミラー（電流比１：１）によってコピーされる。この結果、電流比較器５０では、ＰＭＯＳトランジスタ５０２によって、出力電流Ｉｏｕｔ相当の電流が、ノードＮ３に供給される。 Iout=(Vout−Vgs2)/RO (1)
The output current Iout is copied by a current mirror (1:1 current ratio) by PMOS transistors 501 and 502 . As a result, in the current comparator 50, the PMOS transistor 502 supplies a current corresponding to the output current Iout to the node N3.
　これに対して、基準電流源４０では、電源ラインＮＰから接地ラインＮＬへ、ＰＭＯＳトランジスタ４０５、ＮＭＯＳトランジスタ４０３、及び、抵抗素子４０４を含む、基準電流Ｉｒｅｆの経路が生じる。 On the other hand, in the reference current source 40, a reference current Iref path is generated from the power supply line NP to the ground line NL, including the PMOS transistor 405, the NMOS transistor 403, and the resistance element 404.
　基準電流Ｉｒｅｆは、ノードＮ６の基準電圧Ｖｒｅｆ、抵抗素子４０４の電気抵抗値ＲＰ、及び、ＮＭＯＳトランジスタ４０３のゲートソース間電圧Ｖｇｓ４を用いて、下記の式（２）で示される。即ち、基準電流源４０は、式（２）に従う変換ゲインに従って、基準電圧Ｖｒｅｆを基準電流Ｉｒｅｆに変換する。式（２）では、（１／ＲＰ）が「第２変換ゲイン」の一実施例に相当する。 The reference current Iref is expressed by the following equation (2) using the reference voltage Vref of the node N6, the electrical resistance value RP of the resistance element 404, and the gate-source voltage Vgs4 of the NMOS transistor 403. That is, the reference current source 40 converts the reference voltage Vref into the reference current Iref according to the conversion gain according to equation (2). In Equation (2), (1/RP) corresponds to an example of "second conversion gain".
　Ｉｒｅｆ＝（Ｖｒｅｆ－Ｖｇｓ４）／ＲＰ　　…（２）
　基準電流Ｉｒｅｆは、ＰＭＯＳトランジスタ４０５及び４０６によるカレントミラー（電流比１：１）、及び、ＮＭＯＳトランジスタ５０４及び５０３によるカレントミラー（電流比１：１）によってコピーされる。これにより、電流比較器５０では、ＮＭＯＳトランジスタ５０３によって、基準電流Ｉｒｅｆ相当の電流が、ノードＮ３から引き抜かれる。 Iref=(Vref−Vgs4)/RP (2)
The reference current Iref is copied by a current mirror by PMOS transistors 405 and 406 (current ratio 1:1) and by NMOS transistors 504 and 503 (current ratio 1:1). As a result, in the current comparator 50, the NMOS transistor 503 extracts a current corresponding to the reference current Iref from the node N3.
　この結果、電流比較器５０において、ノードＮ３には、出力電流Ｉｏｕｔ及び基準電流Ｉｒｅｆの電流差を増幅した電圧Ｖ３が発生する。具体的には、Ｉｏｕｔ＞Ｉｒｅｆの場合には、電圧Ｖ３は、電源電圧ＶＤＤ相当のハイレベル電圧（以下、単に「Ｈレベル」とも表記する）となる。一方で、Ｉｏｕｔ＜Ｉｒｅｆの場合には、電圧Ｖ３は、接地電圧ＧＮＤ相当のローレベル電圧（以下、単に「Ｌレベル」とも表記する）となる。ノードＮ３の電圧Ｖ３は、判定信号Ｓｊｄとして、半導体集積回路装置５ａの外部からコンタクト可能な端子６に出力される。 As a result, in the current comparator 50, a voltage V3 is generated at the node N3 by amplifying the current difference between the output current Iout and the reference current Iref. Specifically, when Iout>Iref, the voltage V3 becomes a high-level voltage (hereinafter also simply referred to as "H level") corresponding to the power supply voltage VDD. On the other hand, when Iout<Iref, the voltage V3 becomes a low level voltage (hereinafter also simply referred to as "L level") corresponding to the ground voltage GND. The voltage V3 of the node N3 is output as the determination signal Sjd to the terminal 6 that can be contacted from the outside of the semiconductor integrated circuit device 5a.
　この際に、測定電圧Ｖｏｕｔと比較されるべき判定電圧Ｖｔｏを用いて、Ｖｏｕｔ＝Ｖｔｏのときに、Ｉｏｕｔ＝Ｉｒｅｆとなる様に設計することで、判定を高速化することができる。 At this time, by using the determination voltage Vto to be compared with the measured voltage Vout, and designing so that Iout=Iref when Vout=Vto, it is possible to speed up the determination.
　式（１），（２）より、この様な条件は、下記の式（３）を解くことで求めることができる。 From formulas (1) and (2), such conditions can be obtained by solving formula (3) below.
　（Ｖｔｏ－Ｖｇｓ２）／ＲＯ＝（Ｖｒｅｆ－Ｖｇｓ４）／ＲＰ　　…（３）
　従って、式（３）を変形した式（４）に従って、抵抗素子２０２ａの電気抵抗値ＲＯ、を決めることで、Ｖｏｕｔ＝Ｖｔｏのときに、Ｉｏｕｔ＝Ｉｒｅｆとすることができる。 (Vto-Vgs2)/RO=(Vref-Vgs4)/RP (3)
Therefore, by determining the electric resistance value RO of the resistance element 202a according to the modified expression (4) of the expression (3), Iout=Iref can be established when Vout=Vto.
　ＲＯ＝（Ｖｔｏ－Ｖｇｓ２）／（Ｖｒｅｆ－Ｖｇｓ４）・ＲＰ　　…（４）
　この様に、実施の形態１に係る半導体集積回路装置によれば、測定電圧Ｖｏｕｔを電流変換した出力電流Ｉｏｕｔと、基準電流Ｉｒｅｆとの比較によって、測定電圧Ｖｏｕｔを判定電圧Ｖｔｏと比較することができる。 RO=(Vto−Vgs2)/(Vref−Vgs4)·RP (4)
As described above, according to the semiconductor integrated circuit device according to the first embodiment, it is possible to compare the measured voltage Vout with the determination voltage Vto by comparing the output current Iout obtained by current-converting the measured voltage Vout with the reference current Iref. can.
　電流比較器５０の入力は本質的に低インピーダンス特性を有するため、本実施の形態において、選択回路３０による測定電圧Ｖｏｕｔの切替の際における、ノードＮ３の電圧の静定時間は、特許文献１において電圧同士を比較する電圧比較回路の入力電圧の静定時間と比較して、大幅に短縮される。特に、電流比較器５０を複数の内部ノード間で共有することで回路規模が抑制された構成において、テスト時間を短縮する効果が大きい。 Since the input of the current comparator 50 essentially has low impedance characteristics, the voltage stabilization time of the node N3 when the selection circuit 30 switches the measurement voltage Vout in the present embodiment is described in Patent Document 1. Compared with the settling time of the input voltage of the voltage comparison circuit that compares the voltages, it is greatly shortened. In particular, in a configuration in which the circuit scale is suppressed by sharing the current comparator 50 among a plurality of internal nodes, the effect of shortening the test time is great.
　更に、式（４）から理解される通り、抵抗素子２０２ａの電気抵抗値ＲＯを変えることで、基準電流源４０での固定された基準電流Ｉｒｅｆを用いて、測定電圧Ｖｏｕｔと比較される判定電圧Ｖｔｏを等価的に変化することができる。即ち、電圧電流変換回路２０での、抵抗素子２０２ａの電気抵抗値ＲＯに従う変換ゲインを変えることで、基準電流Ｉｒｅｆを固定した上で、各内部ノードＮＴでの測定電圧Ｖｏｕｔの正常範囲に対応させて、判定電圧Ｖｔｏを自由に変えることができる。即ち、電圧電流変換回路２０での電気抵抗値ＲＯ（即ち、変換ゲイン）は、少なくとも判定電圧Ｖｔｏを反映して決定され、好ましくは、式（４）に従って設定される。これにより、複数の測定電圧に対する判定電圧の切替えを簡素な構成で実現することができる。これらの結果、半導体集積回路装置の製造コストを低減することができる。 Furthermore, as understood from the equation (4), by changing the electrical resistance value RO of the resistive element 202a, the reference current Iref, which is fixed in the reference current source 40, is used to determine the determination voltage Vout to be compared with the measurement voltage Vout. Vto can be changed equivalently. That is, by changing the conversion gain according to the electrical resistance value RO of the resistance element 202a in the voltage-to-current conversion circuit 20, the reference current Iref is fixed and the normal range of the measured voltage Vout at each internal node NT is adjusted. , the determination voltage Vto can be freely changed. That is, the electrical resistance value RO (that is, the conversion gain) in the voltage-current conversion circuit 20 is determined by reflecting at least the determination voltage Vto, and is preferably set according to Equation (4). This makes it possible to switch the determination voltage for a plurality of measurement voltages with a simple configuration. As a result, the manufacturing cost of the semiconductor integrated circuit device can be reduced.
　尚、式（１）～（４）において、Ｖｇｓ２及びＶｇｓ４は、ＮＭＯＳトランジスタ２０１ａ及びＮＭＯＳトランジスタ４０３の間で、電流及びトランジスタサイズ（Ｗ／Ｌ）の比を合わせることで同等の値とすることができる。これにより、式（４）に従って電気抵抗値ＲＯ，ＲＰが決定された下で、Ｉｏｕｔ＝Ｉｒｅｆのときに、Ｖｇｓ２＝Ｖｇｓ４として、測定電圧Ｖｏｕｔと上記判定電圧Ｖｔｏとの比較を行うことができる。 In equations (1) to (4), Vgs2 and Vgs4 can be set to the same value by matching the current and transistor size (W/L) ratios between the NMOS transistor 201a and the NMOS transistor 403. can. As a result, when Iout=Iref and Vgs2=Vgs4, the measured voltage Vout and the determination voltage Vto can be compared with the electrical resistance values RO and RP determined according to the equation (4).
　但し、トランジスタの製造ばらつき（主に、閾値電圧ばらつき）、及び、温度変化に伴って、Ｖｇｓ２及びＶｇｓ４が変動すると、判定結果が影響を受けることが懸念される。従って、電圧電流変換回路２０及び基準電流源４０に使用するＮＭＯＳトランジスタ２０１ａ，４０３には、閾値電圧（Ｖｔｈ）が判定電圧Ｖｔｏ及び基準電圧Ｖｒｅｆよりも十分に小さな素子を適用することが好ましい。例えば、原理的にはＶｔｈ＝０（Ｖ）であるネイティブＭＯＳを用いて、ＮＭＯＳトランジスタ２０１ａ，４０３を構成することが好ましい。 However, if Vgs2 and Vgs4 fluctuate due to transistor manufacturing variations (mainly threshold voltage variations) and temperature changes, there is concern that the determination results may be affected. Therefore, for the NMOS transistors 201a and 403 used in the voltage-current conversion circuit 20 and the reference current source 40, it is preferable to use elements whose threshold voltage (Vth) is sufficiently lower than the determination voltage Vto and the reference voltage Vref. For example, in principle, it is preferable to construct the NMOS transistors 201a and 403 using native MOS with Vth=0 (V).
　図２では、ＮＭＯＳトランジスタを用いて電圧電流変換回路２０を構成する例を示したが、ＰＭＯＳトランジスタを用いて電圧電流変換を行う構成とすることも可能である。特に、判定電圧Ｖｔｏが低い場合には、式（１）中でのＶｇｓ２の影響を軽減するために、抵抗素子２０２ａ（電気抵抗値ＲＯ）に印加される電圧を大きくことが好ましい。 Although FIG. 2 shows an example in which the voltage-to-current conversion circuit 20 is configured using NMOS transistors, it is also possible to adopt a configuration that performs voltage-to-current conversion using PMOS transistors. In particular, when the determination voltage Vto is low, it is preferable to increase the voltage applied to the resistance element 202a (electric resistance value RO) in order to reduce the influence of Vgs2 in equation (1).
　（変形例１）
　図３には、ＰＭＯＳトランジスタを用いて電圧電流変換を行う変形例に係る、図１の各ブロックの内部構成を説明する回路図が示される。図３においても、内部回路１０ａに対応する構成が添字ａを付して代表的に示されるが、同様の構成が、各内部回路１０に対応して配置されている。 (Modification 1)
FIG. 3 shows a circuit diagram for explaining the internal configuration of each block in FIG. 1, according to a modification in which voltage-to-current conversion is performed using PMOS transistors. In FIG. 3 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10. FIG.
　図３を参照して、変形例１では、図２における電圧電流変換回路２０ａ、電流比較器５０、及び、基準電流源４０が、電圧電流変換回路２０ｐａ、電流比較器５０ｐ、及び、基準電流源４０ｐに置換される。 3, in modification 1, the voltage-current conversion circuit 20a, the current comparator 50, and the reference current source 40 in FIG. 40p is substituted.
　電圧電流変換回路２０ｐａは、ＰＭＯＳトランジスタ２０１ｐａと、抵抗素子２０２ａを有する。抵抗素子２０２ａ（電気抵抗値ＲＯ）は、電源ラインＮＰと、ＰＭＯＳトランジスタ２０１ｐａとの間に接続される。ＰＭＯＳトランジスタ２０１ｐａは、抵抗素子２０２ａ及びノードＮ１ａの間に接続される。ＰＭＯＳトランジスタ２０１ｐａのゲートは、ＮＭＯＳトランジスタ２０１（図２）と同様に、測定対象とされる内部ノードＮＴａと接続される。選択回路３０の構成は、図２と同様である。 The voltage-current conversion circuit 20pa has a PMOS transistor 201pa and a resistance element 202a. Resistance element 202a (electric resistance value RO) is connected between power supply line NP and PMOS transistor 201pa. PMOS transistor 201pa is connected between resistance element 202a and node N1a. The gate of PMOS transistor 201pa is connected to internal node NTa to be measured, like NMOS transistor 201 (FIG. 2). The configuration of the selection circuit 30 is the same as in FIG.
　電流比較器５０ｐは、２組のカレントミラーを構成する、ＮＭＯＳトランジスタ５０１ｐ，５０２ｐと、ＰＭＯＳトランジスタ５０３ｐ，５０４ｐとを含む。ＮＭＯＳトランジスタ５０１ｐは、ノードＮ２及び接地ラインＮＬの間に接続され、ＮＭＯＳトランジスタ５０２ｐは、ノードＮ３及び接地ラインＮＬの間に接続される。ＮＭＯＳトランジスタ５０１ｐ及び５０１ｎは、ＰＭＯＳトランジスタ５０１及び５０２（図２）と同様にカレントミラーを構成する。 The current comparator 50p includes NMOS transistors 501p and 502p and PMOS transistors 503p and 504p that form two sets of current mirrors. NMOS transistor 501p is connected between node N2 and ground line NL, and NMOS transistor 502p is connected between node N3 and ground line NL. NMOS transistors 501p and 501n form a current mirror similar to PMOS transistors 501 and 502 (FIG. 2).
　この結果、スイッチ３０１ａのオンに応じて、電源ラインＮＰから接地ラインＮＬへ、抵抗素子２０２ａ、ＰＭＯＳトランジスタ２０１ｐａ、スイッチ３０１ａ（ノードＮ１ａ）、及び、ＮＭＯＳトランジスタ５０１ｐを含む、出力電流Ｉｏｕｔの経路が生じる。出力電流Ｉｏｕｔは、図２での式（１）に代わる下記の式（５）に従って、測定電圧Ｖｏｕｔを電圧電流変換したものである。式（５）より、電圧電流変換回路２０ｐａの変換ゲインも、（１／ＲＯ）である。 As a result, when the switch 301a is turned on, a path of the output current Iout is generated from the power supply line NP to the ground line NL, including the resistance element 202a, the PMOS transistor 201pa, the switch 301a (node N1a), and the NMOS transistor 501p. . The output current Iout is the voltage-current conversion of the measured voltage Vout according to the following equation (5) instead of the equation (1) in FIG. From Equation (5), the conversion gain of the voltage-to-current conversion circuit 20pa is also (1/RO).
　Ｉｏｕｔ＝（ＶＤＤ－Ｖｏｕｔ－Ｖｇｓ２）／ＲＯ　　…（５）
　基準電流源４０は、抵抗素子４０１，４０２，４０４と、ＰＯＳトランジスタ４０３ｐと、ＮＭＯＳトランジスタ４０５ｐ，４０６ｐとを有する。ＮＭＯＳトランジスタ４０６ｐは、接地ラインＮＬ及びノードＮ４の間に接続され、ＮＭＯＳトランジスタ４０５ｐは、接地ラインＮＬ及びノードＮ７の間に接続される。ＮＭＯＳトランジスタ４０５ｐ及び４０６ｐは、ＰＭＯＳトランジスタ４０５及び４０６（図２）と同様にカレントミラーを構成する。ＰＭＯＳトランジスタ４０３ｐは、ノードＮ５及びノードＮ７の間に接続され、抵抗素子４０４（電気抵抗値ＲＰ）は、ノードＮ５及び電源ラインＮＰの間に接続される。 Iout=(VDD−Vout−Vgs2)/RO (5)
The reference current source 40 has resistance elements 401, 402, 404, a POS transistor 403p, and NMOS transistors 405p, 406p. NMOS transistor 406p is connected between ground line NL and node N4, and NMOS transistor 405p is connected between ground line NL and node N7. NMOS transistors 405p and 406p form a current mirror similar to PMOS transistors 405 and 406 (FIG. 2). The PMOS transistor 403p is connected between the node N5 and the node N7, and the resistance element 404 (electrical resistance value RP) is connected between the node N5 and the power supply line NP.
　この結果、基準電流源４０ｐでは、電源ラインＮＰから接地ラインＮＬへ、抵抗素子４０４、ＰＭＯＳトランジスタ４０３ｐ、及び、ＮＭＯＳトランジスタ４０５ｐを含む、基準電圧Ｖｒｅｆに応じた基準電流Ｉｒｅｆの経路が生じる。 As a result, in the reference current source 40p, a path of the reference current Iref corresponding to the reference voltage Vref is generated from the power supply line NP to the ground line NL, including the resistance element 404, the PMOS transistor 403p, and the NMOS transistor 405p.
　基準電流Ｉｒｅｆは、図２での式（２）に代わる下記の式（６）によって示される。式（６）より、基準電流源４０ｐでの変換ゲインも（１／ＲＰ）である。 The reference current Iref is expressed by the following formula (6) instead of formula (2) in FIG. From equation (6), the conversion gain at the reference current source 40p is also (1/RP).
　Ｉｒｅｆ＝（ＶＤＤ－Ｖｒｅｆ－Ｖｇｓ４）／ＲＰ　　…（６）
　図３の電流比較器５０ｐにおいて、基準電流Ｉｒｅｆは、ＰＭＯＳトランジスタ５０３ｐ及び５０４ｐによるカレントミラー（電流比１：１）によってコピーされる。これにより、ＰＭＯＳトランジスタ５０３ｐは、図２と反対に、基準電流Ｉｒｅｆ相当の電流を、ノードＮ３へ供給する。 Iref=(VDD−Vref−Vgs4)/RP (6)
In current comparator 50p of FIG. 3, reference current Iref is copied by a current mirror (1:1 current ratio) by PMOS transistors 503p and 504p. As a result, the PMOS transistor 503p supplies a current corresponding to the reference current Iref to the node N3, contrary to FIG.
　一方で、電圧電流変換回路２０ｐに生じる出力電流Ｉｏｕｔは、ＮＭＯＳトランジスタ５０１ｐ及び５０２ｐによるカレントミラー（電流比１：１）によってコピーされる。この結果、電流比較器５０ｐでは、ＮＭＯＳトランジスタ５０２ｐによって、出力電流Ｉｏｕｔ相当の電流が、ノードＮ３から引き抜かれる。 On the other hand, the output current Iout generated in the voltage-current conversion circuit 20p is copied by a current mirror (current ratio 1:1) by the NMOS transistors 501p and 502p. As a result, in the current comparator 50p, a current corresponding to the output current Iout is drawn from the node N3 by the NMOS transistor 502p.
　従って、電流比較器５０ｐにおいても、Ｎ３には、出力電流Ｉｏｕｔ及び基準電流Ｉｒｅｆの電流差を増幅した電圧Ｖ３が発生する。具体的には、電流比較器５０（図２）とは逆の極性で、Ｉｒｅｆ＞Ｉｏｕｔの場合には、電圧Ｖ３は、Ｈレベル（ＶＤＤ）となる。一方で、Ｉｏｕｔ＞Ｉｒｅｆの場合には、電圧Ｖ３は、Ｌレベル（ＧＮＤ）となる。ノードＮ３の電圧Ｖ３は、判定信号Ｓｊｄとして、電流比較器５０ｐから出力される。 Therefore, also in the current comparator 50p, a voltage V3 is generated at N3 by amplifying the current difference between the output current Iout and the reference current Iref. Specifically, when the polarity is opposite to that of the current comparator 50 (FIG. 2) and Iref>Iout, the voltage V3 becomes H level (VDD). On the other hand, when Iout>Iref, the voltage V3 becomes L level (GND). Voltage V3 of node N3 is output from current comparator 50p as determination signal Sjd.
　尚、上述の式（５），（６）から理解される様に、図３の変形例では、測定電圧Ｖｏｕｔに対する判定電圧Ｖｔｏを用いて、Ｖｏｕｔ＝Ｖｔｏのときに、Ｉｏｕｔ＝Ｉｒｅｆとなる様に設計するためには、下記の式（７）に従って、抵抗素子２０２ａの電気抵抗値ＲＯ、及び、抵抗素子４０４の電気抵抗値ＲＰの比が決められる。 As can be understood from the above equations (5) and (6), in the modified example of FIG. , the ratio between the electrical resistance value RO of the resistor element 202a and the electrical resistance value RP of the resistor element 404 is determined according to the following equation (7).
　ＲＯ＝（ＶＤＤ－Ｖｔｏ－Ｖｇｓ２）／（ＶＤＤ－Ｖｒｅｆ－Ｖｇｓ４）・ＲＰ　　　…（７）
　この様に、変形例１の構成では、図２の構成例に対して、電源ラインＮＰ及び接地ラインＮＬの位置の入れ替え、並びに、ＮＭＯＳトランジスタ及びＰＭＯＳトランジスタの入れ替えを行うことにより、ＰＭＯＳトランジスタを用いて電圧電流変換を行うことが可能となる。 RO=(VDD−Vto−Vgs2)/(VDD−Vref−Vgs4)·RP (7)
As described above, in the configuration of Modification 1, the positions of the power supply line NP and the ground line NL are interchanged with respect to the configuration example of FIG. 2, and the NMOS transistor and the PMOS transistor are interchanged. voltage-to-current conversion can be performed.
　変形例１の構成によっても、図２の構成と同様に、測定電圧Ｖｏｕｔを電流変換した出力電流Ｉｏｕｔと、基準電流Ｉｒｅｆとの比較によって、測定電圧Ｖｏｕｔを判定電圧Ｖｔｏと比較することができる。これにより、判定電圧Ｖｔｏが低い場合に図３の変形例を用いることで、図２で説明したのと同様の効果を得ることができる。 Also with the configuration of Modification 1, similarly to the configuration of FIG. 2, the measured voltage Vout can be compared with the determination voltage Vto by comparing the output current Iout obtained by current-converting the measured voltage Vout with the reference current Iref. As a result, by using the modified example of FIG. 3 when the determination voltage Vto is low, the same effect as described with reference to FIG. 2 can be obtained.
　（変形例２）
　更に、式（１），（２）等でのＶｇｓ２，Ｖｇｓ４の影響をキャンセルするための変形例について説明する。 (Modification 2)
Furthermore, a modified example for canceling the effects of Vgs2 and Vgs4 in equations (1) and (2) will be described.
　図４は、図２に示された電圧電流変換回路２０ａの変形例を説明する回路図である。
　図４の変形例２に係る電圧電流変換回路２０ａ♯は、電圧電流変換回路２０ａ（図２）と同様のＮＭＯＳトランジスタ２０１ａ及び抵抗素子２０２ａに加えて、オペアンプバッファ２３０ａを更に含む。 FIG. 4 is a circuit diagram illustrating a modification of the voltage-current conversion circuit 20a shown in FIG.
Voltage-current conversion circuit 20a# according to Modification 2 of FIG. 4 further includes an operational amplifier buffer 230a in addition to NMOS transistor 201a and resistance element 202a similar to voltage-current conversion circuit 20a (FIG. 2).
　オペアンプバッファ２３０ａは、ＰＭＯＳトランジスタ２０３３ａ，２０３４ａと、ＮＭＯＳトランジスタ２０３１ａ，２０３２ａ，２０３５ａと、電流源２０３６ａ，２０３７ａとを有する。 The operational amplifier buffer 230a has PMOS transistors 2033a and 2034a, NMOS transistors 2031a, 2032a and 2035a, and current sources 2036a and 2037a.
　ＰＭＯＳトランジスタ２０３３ａ及び２０３４ａは、電源ラインＮＰと、ノードＮ１０及びノードＮ１１の間にそれぞれ接続され、ＮＭＯＳトランジスタ２０３１ａ及び２０３２ａは、ノードＮ１０及びノードＮ１１と、ノードＮ１２との間にそれぞれ接続される。電流源２０３６ａは、ノードＮ１２及び接地ラインＮＬの間に接続される。更に、ＰＭＯＳトランジスタ２０３３ａ及び２０３４ａのゲートがノードＮ１０と接続される。 The PMOS transistors 2033a and 2034a are connected between the power supply line NP and the nodes N10 and N11, respectively, and the NMOS transistors 2031a and 2032a are connected between the nodes N10 and N11, respectively, and the node N12. Current source 2036a is connected between node N12 and ground line NL. Furthermore, the gates of PMOS transistors 2033a and 2034a are connected to node N10.
　この様に、ＰＭＯＳトランジスタ２０３３ａ，２０３４ａと、ＮＭＯＳトランジスタ２０３１ａ，２０３２ａと、電流源２０３６ａとによって、カレントミラー型の差動アンプが構成される。ＮＭＯＳトランジスタ２０３１ａのゲートは、測定ノードに相当する内部ノードＮＴａと接続される。 Thus, the PMOS transistors 2033a and 2034a, the NMOS transistors 2031a and 2032a, and the current source 2036a form a current mirror type differential amplifier. The gate of NMOS transistor 2031a is connected to internal node NTa corresponding to the measurement node.
　更に、ＮＭＯＳトランジスタ２０３５ａは、電源ラインＮＰと、ＮＭＯＳトランジスタ２０３２ａのゲートと接続されるノードＮ１３との間に接続される。電流源２０３７ａは、ノードＮ１３及び接地ラインＮＬの間に接続される。ＮＭＯＳトランジスタ２０３５ａのゲートは、ノードＮ１１と接続される。尚、ＮＭＯＳトランジスタ２０３５ａ、ＮＭＯＳトランジスタ２０１ａ、及び、ＮＭＯＳトランジスタ４０３（基準電流源４０）は、同じ特性（トランジスタサイズ）で設計される。 Furthermore, the NMOS transistor 2035a is connected between the power supply line NP and the node N13 connected to the gate of the NMOS transistor 2032a. Current source 2037a is connected between node N13 and ground line NL. The gate of NMOS transistor 2035a is connected to node N11. The NMOS transistor 2035a, the NMOS transistor 201a, and the NMOS transistor 403 (reference current source 40) are designed with the same characteristics (transistor size).
　これにより、オペアンプバッファ２３０ａでは、ＮＭＯＳトランジスタ２０３２ａのゲート電圧は、ＮＭＯＳトランジスタ２０３１ａのゲート電圧、即ち、測定電圧Ｖｏｕｔと同等となる。更に、電流源２０３７ａの電流を基準電流Ｉｒｅｆと同等すると、ＮＭＯＳトランジスタ２０３５ａのゲートソース間電圧は、図２でのＶｇｓ４と同等となる。従って、ＮＭＯＳトランジスタ２０３５ａのゲート電圧、即ち、ノードＮ１１の電圧は、Ｖｏｕｔ＋Ｖｇ４相当となる。 As a result, in the operational amplifier buffer 230a, the gate voltage of the NMOS transistor 2032a becomes equal to the gate voltage of the NMOS transistor 2031a, that is, the measurement voltage Vout. Furthermore, if the current of the current source 2037a is made equal to the reference current Iref, the gate-to-source voltage of the NMOS transistor 2035a becomes equal to Vgs4 in FIG. Therefore, the gate voltage of the NMOS transistor 2035a, that is, the voltage of the node N11, is equivalent to Vout+Vg4.
　一方で、ＮＭＯＳトランジスタ２０１ａには、図２と同様のゲートソース間電圧Ｖｇｓ２が生じる。この結果、抵抗素子２０２ａに印加される電圧は、Ｖｏｕｔ＋Ｖｇｓ４－Ｖｇ２となることが理解される。 On the other hand, the same gate-source voltage Vgs2 as in FIG. 2 is generated in the NMOS transistor 201a. As a result, the voltage applied to the resistance element 202a is Vout+Vgs4-Vg2.
　更に、変形例２では、基準電流源側にも同様のオペアンプバッファが配置される。
　図５は、図２に示された基準電流源４０の変形例を説明する回路図である。 Furthermore, in Modification 2, a similar operational amplifier buffer is arranged on the side of the reference current source.
FIG. 5 is a circuit diagram illustrating a modification of reference current source 40 shown in FIG.
　図５の変形例２に係る基準電流源４０♯は、基準電流源４０（図２）と比較すると、抵抗素子４０１及び４０２の接続点であるのノードＮ６と、ＮＭＯＳトランジスタ４０３のゲートとの間に、オペアンプバッファ４０７を更に含む点で異なる。 Reference current source 40# according to Modification 2 of FIG. 2 in that an operational amplifier buffer 407 is further included.
　オペアンプバッファ４０７は、図４のオペアンプバッファ２３０ａと同様に構成されており、ＮＭＯＳトランジスタ４０７１，４０７２，４０７５と、ＮＭＯＳトランジスタ４０７３，４０７４と、電流源４０７６，４０７７とを有する。 The operational amplifier buffer 407 is configured similarly to the operational amplifier buffer 230a of FIG.
　ＮＭＯＳトランジスタ４０７１のゲートは、基準電圧Ｖｒｅｆが生成されるノードＮ６と接続される。ＮＭＯＳトランジスタ４０７５は、電源ラインＮＰ及びノードＮ１４の間に接続され、電流源４０７７は、ノードＮ１４及び接地ラインＮＬの間に接続される。ＮＭＯＳトランジスタ４０７５のゲートは、ＰＭＯＳトランジスタ４０７４及びＮＭＯＳトランジスタ４０７２の接続点であるノードＮ１５と接続される。ＮＭＯＳトランジスタ４０３のゲートも、ノードＮ１５と接続される。尚、ＮＭＯＳトランジスタ４０７５は、ＮＭＯＳトランジスタ４０３（基準電流源４０）と同じ特性（トランジスタサイズ及び閾値電圧）で設計される。 The gate of NMOS transistor 4071 is connected to node N6 where reference voltage Vref is generated. NMOS transistor 4075 is connected between power supply line NP and node N14, and current source 4077 is connected between node N14 and ground line NL. The gate of the NMOS transistor 4075 is connected to the node N15, which is the connection point between the PMOS transistor 4074 and the NMOS transistor 4072 . The gate of NMOS transistor 403 is also connected to node N15. The NMOS transistor 4075 is designed with the same characteristics (transistor size and threshold voltage) as the NMOS transistor 403 (reference current source 40).
　これにより、オペアンプバッファ４０７では、ＮＭＯＳトランジスタ４０７２のゲート電圧は、ＮＭＯＳトランジスタ４０７１のゲート電圧、即ち、基準電圧Ｖｒｅｆと同等となる。更に、電流源４０７７の電流を、抵抗素子４０４を流れる電流、即ち、基準電流Ｉｒｅｆと同等すると、ＮＭＯＳトランジスタ４０７５のゲートソース間電圧は、ＮＭＯＳトランジスタ４０３のゲートソース間電圧Ｖｇｓ４と同等となる。従って、ＮＭＯＳトランジスタ４０７５のゲート電圧、即ち、ノードＮ１５の電圧は、Ｖｏｕｔ＋Ｖｇ４相当となる。 As a result, in the operational amplifier buffer 407, the gate voltage of the NMOS transistor 4072 becomes equal to the gate voltage of the NMOS transistor 4071, that is, the reference voltage Vref. Furthermore, if the current of the current source 4077 is made equal to the current flowing through the resistance element 404 , that is, the reference current Iref, the gate-source voltage of the NMOS transistor 4075 becomes equal to the gate-source voltage Vgs4 of the NMOS transistor 403 . Therefore, the gate voltage of the NMOS transistor 4075, that is, the voltage of the node N15 is equivalent to Vout+Vg4.
　この結果、抵抗素子４０４に印加される電圧は、基準電圧Ｖｒｅｆと同等になることが理解される。従って、基準電流Ｉｒｅｆは、Ｉｒｅｆ＝Ｖｒｅｆ／ＲＳで示される。 As a result, it is understood that the voltage applied to the resistance element 404 becomes equivalent to the reference voltage Vref. Therefore, the reference current Iref is given by Iref=Vref/RS.
　上述の様に、電圧電流変換回路２０ａ♯において、抵抗素子２０２ａに印加される電圧は、Ｖｏｕｔ＋Ｖｇｓ４－Ｖｇ２である。従って、測定電圧Ｖｏｕｔが判定電圧Ｖｔｏであるとき（Ｖｏｕｔ＝Ｖｔｏ）に、出力電流Ｉｏｕｔと基準電流Ｉｒｅｆが等しくなる様に設計すると、Ｖｇｓ４＝Ｖｇｓ２となるので、出力電流Ｉｏｕｔは、Ｉｏｕｔ＝Ｖｏｕｔ／ＲＯで示される。 As described above, in the voltage-current conversion circuit 20a#, the voltage applied to the resistance element 202a is Vout+Vgs4-Vg2. Therefore, when the measured voltage Vout is the judgment voltage Vto (Vout=Vto), if the output current Iout and the reference current Iref are designed to be equal, Vgs4=Vgs2, so the output current Iout is Iout=Vout/ Denoted by RO.
　従って、オペアンプバッファを含む電圧電流変換回路２０ａ♯及び基準電流源４０♯を適用した変形例では、測定電圧Ｖｏｕｔに対する判定電圧Ｖｔｏを用いて、Ｖｏｕｔ＝Ｖｔｏのときに、Ｉｏｕｔ＝Ｉｒｅｆとなる様に設計するためには、下記の式（８）に従って、抵抗素子２０２ａの電気抵抗値ＲＯ、及び、抵抗素子４０４の電気抵抗値ＲＰの比を決めることができる。尚、式（８）は、図２及び図３の電圧電流変換回路２０，２０ｐにおいても、Ｖｇｓ２＝Ｖｇｓ４とすることで成立する。 Therefore, in the modification using the voltage-to-current conversion circuit 20a# including an operational amplifier buffer and the reference current source 40#, the judgment voltage Vto for the measurement voltage Vout is used so that Iout=Iref when Vout=Vto. For design purposes, the ratio between the electrical resistance value RO of the resistor element 202a and the electrical resistance value RP of the resistor element 404 can be determined according to the following equation (8). Equation (8) is established by setting Vgs2=Vgs4 in the voltage-to-current conversion circuits 20 and 20p of FIGS. 2 and 3 as well.
　ＲＯ＝（Ｖｔｏ／Ｖｒｅｆ）・ＲＰ　　　…（８）
　式（８）から理解される様に、オペアンプバッファを用いることによって、トランジスタの製造ばらつき（主に、閾値電圧ばらつき）、及び、温度変化が生じても、式（４），（７）中でのＶＧｓ２，Ｖｇｓ４の依存性をキャンセルすることができる。この結果、測定電圧Ｖｏｕｔと判定電圧Ｖｔｏとの比較判定を高精度化することができる。 RO=(Vto/Vref)·RP (8)
As can be understood from the equation (8), the use of the operational amplifier buffer makes it possible to produce can cancel the dependence of VGs2 and Vgs4. As a result, it is possible to improve the accuracy of comparison and determination between the measured voltage Vout and the determination voltage Vto.
　尚、オペアンプバッファ２３０ａ（図４）及びオペアンプバッファ４０７（図５）は、図３に示された変形例１での電圧電流変換回路２０ｐａ及び基準電流源４０ｐに対しても、それぞれ適用することが可能である。この場合は、図２から図３へのアレンジと同様にして、オペアンプバッファ２３０ａ及びオペアンプバッファ４０７の各々において、電源ラインＮＰ及び接地ラインＮＬの位置の入れ替え、並びに、ＮＭＯＳトランジスタ及びＰＭＯＳトランジスタの入れ替えを行うことが必要である。 The operational amplifier buffer 230a (FIG. 4) and the operational amplifier buffer 407 (FIG. 5) can also be applied to the voltage-current conversion circuit 20pa and the reference current source 40p in Modification 1 shown in FIG. It is possible. In this case, similar to the arrangement from FIG. 2 to FIG. 3, in each of the operational amplifier buffer 230a and the operational amplifier buffer 407, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistors and PMOS transistors are exchanged. it is necessary to
　実施の形態２．
　図６は、実施の形態２に係る半導体集積回路装置５ｂの構成を示すブロック図である。 Embodiment 2.
FIG. 6 is a block diagram showing the configuration of a semiconductor integrated circuit device 5b according to the second embodiment.
　図６に示される様に、半導体集積回路装置５ｂは、実施の形態１に係る半導体集積回路装置５ａと比較して、Ｎ個の電圧電流変換回路２０に代えてＮ個の電圧電流変換回路２１を備える点と、選択回路３０に代えて選択回路３１とを備える点で異なる。図６でもＮ＝４の場合の構成例が示される。 As shown in FIG. 6, semiconductor integrated circuit device 5b has N voltage-current conversion circuits 21 instead of N voltage-current conversion circuits 20, as compared with semiconductor integrated circuit device 5a according to the first embodiment. and a selection circuit 31 instead of the selection circuit 30 . FIG. 6 also shows a configuration example when N=4.
　各選択回路２１は、対応の内部回路１０の測定ノードに相当する内部ノードＮＴでの測定電圧Ｖｏｕｔに対する変換ゲインが異なる２つの出力電流を発生されるノードを有している。これに応じて、選択回路３１は、Ｎ個の電圧電流変換回路２１の（２×Ｎ）個のノードのうちの１個を選択して、電流比較器５０と接続する様に構成される。 Each selection circuit 21 has a node that generates two output currents with different conversion gains for the measurement voltage Vout at the internal node NT corresponding to the measurement node of the corresponding internal circuit 10 . Accordingly, the selection circuit 31 is configured to select one of the (2×N) nodes of the N voltage-to-current conversion circuits 21 and connect it to the current comparator 50 .
　実施の形態２では、測定電圧Ｖｏｕｔを、２種類の判定電圧と比較することができる。例えば、測定電圧Ｖｏｕｔの正常範囲の下限値に相当する判定電圧Ｖｔｌと、当該正常範囲の上限値に相当する判定電圧Ｖｔｕとを測定電圧Ｖｏｕｔと比較することで、測定電圧Ｖｏｕｔが正常範囲内であるか否かの判定が可能となる。 In Embodiment 2, the measured voltage Vout can be compared with two types of determination voltages. For example, by comparing the determination voltage Vtl corresponding to the lower limit of the normal range of the measured voltage Vout and the determination voltage Vtu corresponding to the upper limit of the normal range with the measured voltage Vout, the measured voltage Vout is within the normal range. It is possible to determine whether or not there is
　図７には、図６に記載された各ブロックの内部構成を説明するための回路図が示される。図７においても、内部回路１０ａに対応する構成が添字ａを付して代表的に示されるが、同様の構成が、各内部回路１０に対応して配置されている。 FIG. 7 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. In FIG. 7 as well, the structure corresponding to internal circuit 10a is representatively shown with a suffix a, and similar structures are arranged corresponding to each internal circuit 10. In FIG.
　図７を参照して、電圧電流変換回路２１ａは、ＮＭＯＳトランジスタ２０３ａ，２０５ａと、抵抗素子２０４ａ，２０６ａとを含む。ＮＭＯＳトランジスタ２０３ａ及び２０５ａのゲートは、内部ノードＮＴａと共通に接続される。即ち、ＮＭＯＳトランジスタ２０３ａ及び２０５ａのゲート電圧は、測定電圧Ｖｏｕｔである。 Referring to FIG. 7, voltage-current conversion circuit 21a includes NMOS transistors 203a and 205a and resistance elements 204a and 206a. The gates of NMOS transistors 203a and 205a are commonly connected to internal node NTa. That is, the gate voltages of NMOS transistors 203a and 205a are the measured voltage Vout.
　ＮＭＯＳトランジスタ２０３ａは、ノードＮ１ａｘ及び抵抗素子２０４ａの間に接続され、抵抗素子２０４ａは、ＮＭＯＳトランジスタ２０３ａ及び接地ラインＮＬの間に接続される。抵抗素子２０４ａは、電気抵抗値ＲＵを有する。 The NMOS transistor 203a is connected between the node N1ax and the resistance element 204a, and the resistance element 204a is connected between the NMOS transistor 203a and the ground line NL. Resistive element 204a has an electrical resistance value RU.
　同様に、ＮＭＯＳトランジスタ２０５ａは、ノードＮ１ａｙ及び抵抗素子２０６ａの間に接続され、抵抗素子２０６ａは、ＮＭＯＳトランジスタ２０５ａ及び接地ラインＮＬの間に接続される。抵抗素子２０６ａは、電気抵抗値ＲＬを有する。 Similarly, the NMOS transistor 205a is connected between the node N1ay and the resistance element 206a, and the resistance element 206a is connected between the NMOS transistor 205a and the ground line NL. The resistive element 206a has an electrical resistance value RL.
　電圧電流変換回路２１ａでは、図２でのＮＭＯＳトランジスタ２０１ａ及び抵抗素子２０２ａの直列回路に相当する「電圧電流変換ユニット」が２個設けられており、図２でのノードＮ１ａに相当する、出力電流Ｉｏｕｔが生成されるノードが、ノードＮ１ｘａ，Ｎ１ｙａの２個に増加する。抵抗素子２０４ａ及び２０６ａの電気抵抗値が異なるので、２個の電圧電流変換ユニットは、共通の測定電圧Ｖｏｕｔを、異なる変換ゲインで出力電流に変換する。 The voltage-current conversion circuit 21a is provided with two "voltage-current conversion units" corresponding to the series circuit of the NMOS transistor 201a and the resistance element 202a in FIG. The number of nodes where Iout is generated is increased to two, nodes N1xa and N1ya. Due to the different electrical resistance values of resistive elements 204a and 206a, the two voltage-to-current conversion units convert a common measured voltage Vout to output currents with different conversion gains.
　電圧電流変換回路２１ｂ～２１ｄについても、電圧電流変換回路２１ａと同様に構成されており、各電圧電流変換回路２１において、２個のノードと接地ラインＮＬとの間に、ＮＭＯＳトランジスタ及び抵抗素子の直列回路（電圧電流変換ユニット）がそれぞれ配置される。 The voltage-to-current conversion circuits 21b to 21d are configured in the same manner as the voltage-to-current conversion circuit 21a. A series circuit (voltage-to-current conversion unit) is arranged respectively.
　選択回路３１は、スイッチ３０２ａ～３０２ｄ，３０３ａ～３０３ｄを有する。スイッチ３０３ａ～３０３ｄは、電圧電流変換回路２１の２個のノードの一方（図７でのノードＮ１ａｘ）と、ノードＮ２との間にそれぞれ接続される。スイッチ３０２ａ～３０２ｄは、電圧電流変換回路２１の２個のノードの他方（図７でのノードＮ１ａｙ）と、ノードＮ２との間にそれぞれ接続される。 The selection circuit 31 has switches 302a to 302d and 303a to 303d. Switches 303a-303d are connected between one of two nodes of voltage-current conversion circuit 21 (node N1ax in FIG. 7) and node N2, respectively. Switches 302a-302d are connected between the other of the two nodes of voltage-current conversion circuit 21 (node N1ay in FIG. 7) and node N2, respectively.
　実施の形態２において、ノードＮ２よりも後段の構成、即ち、電流比較器５０及び基準電流源４０の構成は、図２と同様であるので、詳細な説明は繰り返さない。 In the second embodiment, the configuration after the node N2, that is, the configurations of the current comparator 50 and the reference current source 40 are the same as in FIG. 2, so detailed description will not be repeated.
　実施の形態２に係る半導体集積回路装置５ｂにおいて、選択回路３１は、スイッチ３０２ａ～３０２ｄ，３０３ａ～３０３ｄのうちの１つをオンする一方で、残りのスイッチをオフする。測定対象の内部回路（内部ノード）に対応する２つのスイッチについて、一方ずつを順番にオンすることで、ノードＮ１ａｘに生成される出力電流（Ｉｏｕ）と、ノードＮ１ａｙに生成される出力電流（Ｉｏｌ）とが、１つずつ順に電流比較器５０に入力される。これにより、測定電圧Ｖｏｕｔを、２個の判定電圧Ｖｔｕ，Ｖｔｌと順番に比較することができる。 In the semiconductor integrated circuit device 5b according to the second embodiment, the selection circuit 31 turns on one of the switches 302a to 302d and 303a to 303d, and turns off the remaining switches. By sequentially turning on two switches corresponding to the internal circuit (internal node) to be measured, the output current (Iou) generated at the node N1ax and the output current (Iol ) are sequentially input to the current comparator 50 one by one. As a result, the measured voltage Vout can be sequentially compared with the two determination voltages Vtu and Vtl.
　まず、スイッチ３０２ａをオンする一方で、残りのスイッチをオフする。これにより、電源ラインＮＰから接地ラインＮＬへ、ＰＭＯＳトランジスタ５０１、スイッチ３０２ａ（ノードＮ１ａｙ）、ＮＭＯＳトランジスタ２０５ａ、及び、抵抗素子２０６ａを含む、出力電流Ｉｏｌの経路が、図２での出力電流Ｉｏｕｔの経路と同様に生じる。このとき、電流比較器５０では、ＰＭＯＳトランジスタ５０１及び５０２によるカレントミラーによって、ＰＭＯＳトランジスタ５０２がノードＮ３へ供給する出力電流Ｉｏｕｔが、出力電流Ｉｏｌと同等となる（Ｉｏｕｔ＝Ｉｏｌ）。 First, while the switch 302a is turned on, the remaining switches are turned off. As a result, the path of the output current Iol from the power supply line NP to the ground line NL, including the PMOS transistor 501, the switch 302a (node N1ay), the NMOS transistor 205a, and the resistance element 206a, changes from the output current Iout in FIG. It occurs in the same way as the path. At this time, in the current comparator 50, the current mirror by the PMOS transistors 501 and 502 makes the output current Iout supplied to the node N3 by the PMOS transistor 502 equal to the output current Iol (Iout=Iol).
　次に、スイッチ３０３ａをオンする一方で、残りのスイッチをオフする。電源ラインＮＰから接地ラインＮＬへ、ＰＭＯＳトランジスタ５０１、スイッチ３０３ａ（ノードＮ１ａｘ）、ＮＭＯＳトランジスタ２０３ａ、及び、抵抗素子２０４ａを含む、出力電流Ｉｏｕの経路が、図２での出力電流Ｉｏｕｔの経路と同様に生じる。このとき、電流比較器５０では、ＰＭＯＳトランジスタ５０２がノードＮ３へ供給する出力電流Ｉｏｕｔが、出力電流Ｉｏｕと同等となる（Ｉｏｕｔ＝Ｉｏｕ）。 Next, while turning on the switch 303a, the remaining switches are turned off. The path of output current Iou from power supply line NP to ground line NL, including PMOS transistor 501, switch 303a (node N1ax), NMOS transistor 203a, and resistance element 204a, is the same as the path of output current Iout in FIG. occurs in At this time, in current comparator 50, output current Iout supplied from PMOS transistor 502 to node N3 becomes equal to output current Iou (Iout=Iou).
　この様に、電圧電流変換回路２１は、共通の測定電圧Ｖｏｕｔに対して、変換ゲインが異なる複数の出力電流Ｉｏｌ，Ｉｏｕを生成することできる。測定電圧Ｖｏｕｔに対する、出力電流Ｉｏｌ及びＩｏｕのそれぞれの変換ゲインは、電気抵抗値ＲＬ及びＲＬによって調整される。 Thus, the voltage-to-current conversion circuit 21 can generate a plurality of output currents Iol and Iou with different conversion gains for the common measurement voltage Vout. The respective conversion gains of the output currents Iol and Iou with respect to the measured voltage Vout are adjusted by the electrical resistance values RL and RL.
　上述した、測定電圧Ｖｏｕｔの正常範囲の下限値に相当する判定電圧Ｖｔｌについて、Ｖｏｕｔ＝Ｖｔｌのときに、Ｉｏｕｔ＝Ｉｏｌ＝Ｉｒｅｆとするための電気抵抗値ＲＵは、式（４）を変形した下記の式（９）によって示される。式（９）中のＶｇｓ２２は、ＮＭＯＳトランジスタ２０５ａのゲートソース間電圧を示す。 Regarding the judgment voltage Vtl corresponding to the lower limit of the normal range of the measurement voltage Vout described above, when Vout=Vtl, the electric resistance value RU for setting Iout=Iol=Iref is obtained by modifying the formula (4) as follows. (9). Vgs22 in equation (9) indicates the gate-source voltage of the NMOS transistor 205a.
　ＲＯ＝（Ｖｔｌ－Ｖｇｓ２２）／（Ｖｒｅｆ－Ｖｇｓ４）・ＲＰ　　…（９）
　測定電圧Ｖｏｕｔの正常範囲の上限値に相当する判定電圧Ｖｔｕについて、Ｖｏｕｔ＝Ｖｔｕのときに、Ｉｏｕｔ＝Ｉｏｕ＝Ｉｒｅｆとするための電気抵抗値ＲＵは、式（４）を変形した下記の式（１０）によって示される。式（１０）中のＶｇｓ２１は、ＮＭＯＳトランジスタ２０３ａのゲートソース間電圧を示す。 RO=(Vtl−Vgs22)/(Vref−Vgs4)·RP (9)
Regarding the judgment voltage Vtu corresponding to the upper limit of the normal range of the measured voltage Vout, the electrical resistance value RU for setting Iout=Iou=Iref when Vout=Vtu is obtained by the following formula ( 10). Vgs21 in equation (10) indicates the gate-source voltage of the NMOS transistor 203a.
　ＲＯ＝（Ｖｔｕ－Ｖｇｓ２１）／（Ｖｒｅｆ－Ｖｇｓ４）・ＲＰ　　…（１０）
　電流比較器５０では、図２と同様に、基準電流Ｉｒｅｆと同等の電流が、ＮＭＯＳトランジスタ５０３によって、ノードＮ３から引き抜かれる。従って、ノードＮ３では、スイッチ３０２ａのオン時には、出力電流Ｉｏｌと基準電流Ｉｒｅｆとの電流差を増幅した電圧Ｖ３が生じる一方で、スイッチ３０３ａのオン時には、出力電流Ｉｏｕと基準電流Ｉｒｅｆとの電流差を増幅した電圧Ｖ３が生じることになる。即ち、Ｉｏｕ又はＩｏｌのいずれかに設定される出力電流Ｉｏｕｔと、基準電流Ｉｒｅｆとの大小に応じて、ノードＮ３に生成される判定信号Ｓｊｄは、Ｈレベル又はＬレベルに設定される。 RO=(Vtu−Vgs21)/(Vref−Vgs4)·RP (10)
In current comparator 50, a current equivalent to reference current Iref is drawn from node N3 by NMOS transistor 503, as in FIG. Therefore, at the node N3, when the switch 302a is turned on, a voltage V3 generated by amplifying the current difference between the output current Iol and the reference current Iref is generated. is amplified to generate a voltage V3. That is, the determination signal Sjd generated at the node N3 is set to H level or L level depending on the magnitude of the output current Iout set to either Iou or Iol and the reference current Iref.
　従って、スイッチ３０２ａのオン時には、Ｖｏｕｔ＞Ｖｔｌのときには、Ｉｏｕｔ＝Ｉｏｕ＞Ｉｒｅｆとなるので、判定信号ＳｊｄはＨレベルに設定される。一方で、スイッチ３０３ａのオン時には、Ｖｏｕｔ＜Ｖｔｕのときには、Ｉｏｕｔ＝Ｉｏｌ＜Ｉｒｅｆとなるので、判定信号ＳｊｄはＬレベルに設定される。この様にして、測定電圧Ｖｏｕｔが、予め定められた電圧範囲（正常範囲）Ｖｔｕ＜Ｖｏｕｔ＜Ｖｔｌに含まれるか否かを判定することができる。 Therefore, when the switch 302a is turned on, Iout=Iou>Iref when Vout>Vtl, and the determination signal Sjd is set to H level. On the other hand, when the switch 303a is turned on, when Vout<Vtu, Iout=Iol<Iref, so the decision signal Sjd is set to L level. In this manner, it is possible to determine whether or not the measured voltage Vout is included in a predetermined voltage range (normal range) Vtu<Vout<Vtl.
　以上説明した様に、実施の形態２に係る半導体集積回路装置によれば、実施の形態１で説明した効果に加えて、１組の基準電流源４０及び電流比較器５０を用いて、回路規模の増大を抑制して、測定電圧Ｖｏｕｔを複数の判定電圧と比較することができる。これにより、正常範囲の下限値及び上限値との比較により、測定電圧Ｖｏｕｔが正常範囲内であるか否かの判定を効率的に実行することができる。 As described above, according to the semiconductor integrated circuit device according to the second embodiment, in addition to the effects described in the first embodiment, a set of the reference current source 40 and the current comparator 50 is used to reduce the circuit scale. can be suppressed, and the measured voltage Vout can be compared with a plurality of judgment voltages. Thus, it is possible to efficiently determine whether or not the measured voltage Vout is within the normal range by comparison with the lower limit value and the upper limit value of the normal range.
　尚、実施の形態２においても、実施の形態１で説明した変形例１及び変形例２を適用することが可能である。即ち、電圧電流変換回路２１、電流比較器５０，及び、基準電流源４０において、電源ラインＮＰ及び接地ラインＮＬの位置の入れ替え、並びに、ＮＭＯＳトランジスタ及びＰＭＯＳトランジスタの入れ替えを行うことにより、ＰＭＯＳトランジスタを用いて電圧電流変換を行うことが可能である。或いは、電圧電流変換回路２１及び基準電流源４０にオペアンプバッファ（図４、図５）を追加することで、ＭＯＳトランジスタのばらつき及び温度変動の影響を抑制して、判定の高精度化を図ることができる。 It should be noted that Modification 1 and Modification 2 described in Embodiment 1 can also be applied to Embodiment 2. That is, in the voltage-to-current conversion circuit 21, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged, so that the PMOS transistor is replaced. It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 21 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
　実施の形態３．
　実施の形態３では、実施の形態２と同様に、測定電圧Ｖｏｕｔを複数の判定電圧と比較する構成の他の一例を説明する。 Embodiment 3.
In the third embodiment, as in the second embodiment, another example of a configuration for comparing the measured voltage Vout with a plurality of determination voltages will be described.
　図８は、実施の形態３に係る半導体集積回路装置５ｃの構成を示すブロック図である。
　図８に示される様に、半導体集積回路装置５ｃは、実施の形態１に係る半導体集積回路装置５ａと比較して、Ｎ個の電圧電流変換回路２０に代えてＮ個の電圧電流変換回路２２を備える点が異なる。各電圧電流変換回路２２には、変換ゲインを切替えるための制御信号Ｓｃｈｇが入力される。 FIG. 8 is a block diagram showing the configuration of a semiconductor integrated circuit device 5c according to the third embodiment.
As shown in FIG. 8, semiconductor integrated circuit device 5c has N voltage-current conversion circuits 22 instead of N voltage-current conversion circuits 20, as compared with semiconductor integrated circuit device 5a according to the first embodiment. The difference is that the A control signal Schg for switching the conversion gain is input to each voltage-current conversion circuit 22 .
　一方で、選択回路３０、基準電流源４０、及び、電流比較器５０については、実施の形態１と同様の構成である。図８でもＮ＝４の場合の構成例が示される。実施の形態３においても、測定電圧Ｖｏｕｔを、実施の形態２と同様の判定電圧Ｖｔｌ，Ｖｔｕと比較するための構成について説明する。 On the other hand, the selection circuit 30, the reference current source 40, and the current comparator 50 have the same configurations as in the first embodiment. FIG. 8 also shows a configuration example when N=4. Also in the third embodiment, a configuration for comparing the measured voltage Vout with the determination voltages Vtl and Vtu similar to those in the second embodiment will be described.
　図９には、図８に記載された各ブロックの内部構成を説明するための回路図が示される。図９においても、内部回路１０ａに対応する構成が添字ａを付して代表的に示されるが、同様の構成が、各内部回路１０に対応して配置されている。 FIG. 9 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. In FIG. 9 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10. In FIG.
　図９を参照して、電圧電流変換回路２２ａは、ＮＭＯＳトランジスタ２０１ａと、抵抗素子２０９ａ，２１０ａと、トランジスタスイッチ２０８ａとを有する。抵抗素子２０９ａは、電気抵抗値ＲＯ１を有し、抵抗素子２１０ａは、電気抵抗値ＲＯ２を有する。 Referring to FIG. 9, voltage-current conversion circuit 22a has NMOS transistor 201a, resistance elements 209a and 210a, and transistor switch 208a. Resistance element 209a has an electrical resistance value RO1, and resistance element 210a has an electrical resistance value RO2.
　電圧電流変換回路２２ａは、図２の電圧電流変換回路２０ａと比較すると、抵抗素子２０２ａに代えて、直列接続された抵抗素子２０９ａ及び２０１ａが、ＮＭＯＳトランジスタ２０１ａのソースと接地ラインＮＬとの間に接続される構成を有する。トランジスタスイッチ２０８ａは、抵抗素子２１０ａに対して並列に接続される。トランジスタスイッチ２０８ａは、制御信号ＳｃｈｇがＨレベルのときにオンされる一方で、Ｌレベルのときにはオフされる。 Compared to the voltage-current conversion circuit 20a of FIG. 2, the voltage-current conversion circuit 22a has series-connected resistance elements 209a and 201a instead of the resistance element 202a between the source of the NMOS transistor 201a and the ground line NL. It has a connected configuration. Transistor switch 208a is connected in parallel with resistive element 210a. Transistor switch 208a is turned on when control signal Schg is at H level, and turned off when it is at L level.
　実施の形態３において、ノードＮ１ａ～Ｎ１ｄよりも後段の構成、即ち、選択回路３０、電流比較器５０、及び、基準電流源４０の構成は、図２と同様であるので、詳細な説明は繰り返さない。 In the third embodiment, the configuration after the nodes N1a to N1d, that is, the configuration of the selection circuit 30, the current comparator 50, and the reference current source 40 is the same as that of FIG. 2, so the detailed description will be repeated. do not have.
　実施の形態３に係る半導体集積回路装置５ｃにおいて、選択回路３０は、図２と同様に、測定ノードに対応するスイッチ３０１ａをオンする。これにより、図２と同様に、電源ラインＮＰから接地ラインＮＬへ、ＰＭＯＳトランジスタ５０１、スイッチ３０１ａ（ノードＮ１ａ）、及び、ＮＭＯＳトランジスタ２０１ａを含む、出力電流Ｉｏｕｔの経路が生じる。 In the semiconductor integrated circuit device 5c according to the third embodiment, the selection circuit 30 turns on the switch 301a corresponding to the measurement node, as in FIG. As a result, as in FIG. 2, a path of the output current Iout is generated from the power supply line NP to the ground line NL, including the PMOS transistor 501, the switch 301a (node N1a), and the NMOS transistor 201a.
　電圧電流変換回路２２ａでは、出力電流Ｉｏｕｔの経路に含まれる、ＮＭＯＳトランジスタ２０１ａのソースと接地ラインＮＬの間の電気抵抗値が、制御信号Ｓｃｈｇに応じて切替えられる。具体的には、制御信号ＳｃｈｇがＨレベルのときには、出力電流Ｉｏｕｔが抵抗素子２１０ａをバイパスするので、電気抵抗値はＲＯ１となる。これに対して、制御信号ＳｃｈｇがＬレベルのときには、出力電流Ｉｏｕｔが抵抗素子２０９ａ及び２１０ａの両方を通過するので、電気抵抗値はＲＯ１＋ＲＯ２となる。 In the voltage-current conversion circuit 22a, the electrical resistance value between the source of the NMOS transistor 201a and the ground line NL included in the path of the output current Iout is switched according to the control signal Schg. Specifically, when the control signal Schg is at the H level, the output current Iout bypasses the resistance element 210a, so the electrical resistance value is RO1. On the other hand, when the control signal Schg is at L level, the output current Iout passes through both the resistive elements 209a and 210a, so the electrical resistance value is RO1+RO2.
　この結果、電圧電流変換回路２２ａでは、実施の形態２（図７）の電圧電流変換回路２１ａと同様に、測定電圧Ｖｏｕｔに対する出力電流Ｉｏｕｔの変換ゲインを２段階に設定できる。それぞれの変換ゲインは、１／ＲＯ１及び１／（ＲＯ１＋ＲＯ２）に相当する。電流比較器５０では、ＰＭＯＳトランジスタ５０２がノードＮ３へ供給する出力電流Ｉｏｕｔが、トランジスタスイッチ２０８ａに入力される制御信号Ｓｃｈｇに応じて切替えられることになる。即ち、トランジスタスイッチ２０８ａによって「ゲイン切替機構」の一実施例を構成することができる。 As a result, in the voltage-to-current conversion circuit 22a, the conversion gain of the output current Iout with respect to the measured voltage Vout can be set in two stages, like the voltage-to-current conversion circuit 21a of the second embodiment (FIG. 7). The respective conversion gains correspond to 1/RO1 and 1/(RO1+RO2). In the current comparator 50, the output current Iout supplied to the node N3 by the PMOS transistor 502 is switched according to the control signal Schg input to the transistor switch 208a. That is, an embodiment of a "gain switching mechanism" can be configured by the transistor switch 208a.
　実施の形態２と同様の判定電圧Ｖｔｌ（下限値側）について、Ｖｏｕｔ＝Ｖｔｌのときに、Ｉｏｕｔ＝Ｉｒｅｆとするための電気抵抗値ＲＯ１は、式（４）を変形した下記の式（１１）によって示される。 Regarding the determination voltage Vtl (lower limit side) similar to that of the second embodiment, when Vout=Vtl, the electrical resistance value RO1 for setting Iout=Iref is given by the following formula (11), which is a modified formula (4). indicated by
　ＲＯ１＝（Ｖｔｌ－Ｖｇｓ２）／（Ｖｒｅｆ－Ｖｇｓ４）・ＲＰ　　…（１１）
　同様に、判定電圧Ｖｔｕ（上限値側）について、Ｖｏｕｔ＝Ｖｔｕのときに、Ｉｏｕｔ＝Ｉｒｅｆとするための電気抵抗値ＲＯ１＋ＲＯ２は、式（４）を変形した下記の式（１２）によって示される。 RO1=(Vtl−Vgs2)/(Vref−Vgs4)·RP (11)
Similarly, regarding the determination voltage Vtu (on the upper limit side), when Vout=Vtu, the electric resistance value RO1+RO2 for setting Iout=Iref is given by the following equation (12), which is a modified equation (4).
　ＲＯ１＋ＲＯ２＝（Ｖｔｕ－Ｖｇｓ２）／（Ｖｒｅｆ－Ｖｇｓ４）・ＲＰ　…（１２）
　電流比較器５０では、図２と同様に、基準電流Ｉｒｅｆと同等の電流が、ＮＭＯＳトランジスタ５０３によって、ノードＮ３から引き抜かれる。従って、ノードＮ３では、制御信号Ｓｃｈｇに応じて変換ゲインが切り替えられる出力電流Ｉｏｕｔと、基準電流Ｉｒｅｆの電流差を増幅した電圧Ｖ３が生じる。 RO1+RO2=(Vtu−Vgs2)/(Vref−Vgs4)·RP (12)
In current comparator 50, a current equivalent to reference current Iref is drawn from node N3 by NMOS transistor 503, as in FIG. Therefore, at the node N3, a voltage V3 is generated by amplifying the current difference between the output current Iout whose conversion gain is switched according to the control signal Schg and the reference current Iref.
　従って、制御信号ＳｃｈｇのＨレベル時（トランジスタスイッチ２０８ａのオン時）には、Ｖｏｕｔ＜Ｖｔｌのときには、Ｉｏｕｔ＞Ｉｒｅｆとなって、判定信号ＳｊｄはＨレベルに設定される。一方で、制御信号ＳｃｈｇのＬレベル時（トランジスタスイッチ２０８ａのオフ時）には、Ｖｏｕｔ＜Ｖｔｕのときには、Ｉｏｕｔ＜Ｉｒｅｆとなって、判定信号ＳｊｄはＬレベルに設定される。この様にして、測定電圧Ｖｏｕｔが、予め定められた電圧範囲（正常範囲）Ｖｔｕ＜Ｖｏｕｔ＜Ｖｔｌに含まれるか否かを判定することができる。 Therefore, when the control signal Schg is at H level (when the transistor switch 208a is on), when Vout<Vtl, Iout>Iref, and the determination signal Sjd is set at H level. On the other hand, when the control signal Schg is at L level (when the transistor switch 208a is off), when Vout<Vtu, Iout<Iref, and the determination signal Sjd is set at L level. In this manner, it is possible to determine whether or not the measured voltage Vout is included in a predetermined voltage range (normal range) Vtu<Vout<Vtl.
　以上説明した様に、実施の形態３に係る半導体集積回路装置によれば、実施の形態２と同様に、１組の基準電流源４０及び電流比較器５０を用いて、回路規模の増大を抑制して、測定電圧Ｖｏｕｔを複数の判定電圧と比較することができる。これにより、正常範囲の下限値及び上限値との比較により、測定電圧Ｖｏｕｔが正常範囲内であるか否かの判定を効率的に実行することができる。 As described above, according to the semiconductor integrated circuit device according to the third embodiment, similar to the second embodiment, one set of the reference current source 40 and the current comparator 50 is used to suppress an increase in circuit size. Thus, the measured voltage Vout can be compared with a plurality of decision voltages. Thus, it is possible to efficiently determine whether or not the measured voltage Vout is within the normal range by comparison with the lower limit value and the upper limit value of the normal range.
　更に、実施の形態３の構成によれば、スイッチ数が２倍となる選択回路３１を用いることなく、実施の形態２と同様の測定電圧Ｖｏｕｔの判定を実行することができる。即ち、実施の形態２と同様の効果が得られるとともに、実施の形態２と比較して、回路規模を抑制することが可能となる。 Furthermore, according to the configuration of the third embodiment, it is possible to determine the measured voltage Vout in the same manner as in the second embodiment without using the selection circuit 31 that doubles the number of switches. That is, the same effect as in the second embodiment can be obtained, and the circuit scale can be suppressed as compared with the second embodiment.
　尚、実施の形態３においても、実施の形態１で説明した変形例１及び変形例２を適用することが可能である。即ち、電圧電流変換回路２２、電流比較器５０，及び、基準電流源４０において、電源ラインＮＰ及び接地ラインＮＬの位置の入れ替え、並びに、ＮＭＯＳトランジスタ及びＰＭＯＳトランジスタの入れ替えを行うことにより、ＰＭＯＳトランジスタを用いて電圧電流変換を行うことが可能である。或いは、電圧電流変換回路２２及び基準電流源４０にオペアンプバッファ（図４、図５）を追加することで、ＭＯＳトランジスタのばらつき及び温度変動の影響を抑制して、判定の高精度化を図ることができる。 Also in Embodiment 3, Modification 1 and Modification 2 described in Embodiment 1 can be applied. That is, in the voltage-current conversion circuit 22, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged to replace the PMOS transistor. It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 22 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
　実施の形態４．
　実施の形態４では、実施の形態２及び３で説明した、測定電圧Ｖｏｕｔと、複数の判定電圧（例えば、Ｖｔｕ，Ｖｔｌ）との比較を同時刻に実行可能な構成を説明する。 Embodiment 4.
In a fourth embodiment, a configuration capable of simultaneously comparing the measurement voltage Vout and a plurality of determination voltages (for example, Vtu and Vtl) described in the second and third embodiments will be described.
　図１０は、実施の形態４に係る半導体集積回路装置５ｄの構成を示すブロック図である。 FIG. 10 is a block diagram showing the configuration of a semiconductor integrated circuit device 5d according to the fourth embodiment.
　図１０に示される様に、半導体集積回路装置５ｄは、実施の形態２に係る半導体集積回路装置５ｂ（図６）と比較して、選択回路３１に代えて選択回路３２が配置される点、電流比較器５０に代えて電流比較器５１が配置される点、及び、判定論理回路６０が更に配置される点で異なる。一方で、電圧電流変換回路２１及び基準電流源４０は、実施の形態２（図６）と同様である。 As shown in FIG. 10, a semiconductor integrated circuit device 5d differs from the semiconductor integrated circuit device 5b (FIG. 6) according to the second embodiment in that a selection circuit 32 is arranged instead of the selection circuit 31. It differs in that a current comparator 51 is arranged instead of the current comparator 50 and that a decision logic circuit 60 is further arranged. On the other hand, the voltage-current conversion circuit 21 and the reference current source 40 are the same as those in the second embodiment (FIG. 6).
　図１１には、図１０に示された各ブロックの内部構成を説明するための回路図が示される。図１１においても、内部回路１０ａに対応する構成が添字ａを付して代表的に示されるが、同様の構成が、各内部回路１０に対応して配置されている。 FIG. 11 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. In FIG. 11 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10. In FIG.
　図１１に示される様に、選択回路３２は、スイッチ３０４ａ～３０４ｄ，３０５ａ～３０５ｄを有する。又、電流比較器５１は、ノードＮ２ｘ及びＮ２ｘに出力電流Ｉｏｕｔｘ及びＩｏｕｔｙを同時に生成できる様に構成される。 As shown in FIG. 11, the selection circuit 32 has switches 304a-304d and 305a-305d. Also, the current comparator 51 is configured to simultaneously generate output currents Ioutx and Iouty at nodes N2x and N2x.
　従って、電圧電流変換回路２１ａのノードＮ１ａｘは、選択回路３２のスイッチ３０５ａを介して、電流比較器５１のノードＮ２ｘと接続され、電圧電流変換回路２１ａのノードＮ１ａｙは、選択回路３２のスイッチ３０４ａを介して、電流比較器５１のノードＮ２ｙと接続される。この様に、選択回路３２は、電圧電流変換回路２１ａ～２１ｄのうちの１つの電圧電流変換回路２１の２個のノード（Ｎｉａｘ，Ｎ１ａｙ相当）を、電流比較器５１のノードＮ２ｘ及びＮ２ｙとそれぞれ接続する様に制御される。 Therefore, the node N1ax of the voltage-current conversion circuit 21a is connected to the node N2x of the current comparator 51 via the switch 305a of the selection circuit 32, and the node N1ay of the voltage-current conversion circuit 21a connects the switch 304a of the selection circuit 32. It is connected to the node N2y of the current comparator 51 via. In this way, the selection circuit 32 connects the two nodes (corresponding to Niax and N1ay) of one of the voltage-to-current conversion circuits 21a to 21d to the nodes N2x and N2y of the current comparator 51, respectively. Controlled to connect.
　電流比較器５１は、４組のカレントミラーを構成する、ＰＭＯＳトランジスタ５０５～５０８と、ＮＭＯＳトランジスタ５０９～５１１とを有する。 The current comparator 51 has PMOS transistors 505 to 508 and NMOS transistors 509 to 511 that form four sets of current mirrors.
　ＰＭＯＳトランジスタ５０５及び５０６は、電源ラインＮＰと、ノードＮ２ｘ及びＮ３ｘとの間にそれぞれ接続される。ＰＭＯＳトランジスタ５０５及び５０６は、ゲートがノードＮ２ｘ（即ち、ＰＭＯＳトランジスタ５０５のドレイン）と共通接続されることでカレントミラー（電流比は１：１）を構成する。 The PMOS transistors 505 and 506 are connected between the power supply line NP and the nodes N2x and N3x, respectively. The PMOS transistors 505 and 506 form a current mirror (current ratio is 1:1) by commonly connecting the gates to the node N2x (that is, the drain of the PMOS transistor 505).
　ＰＭＯＳトランジスタ５０７及び５０８は、電源ラインＮＰと、ノードＮ２ｙ及びＮ３ｙとの間にそれぞれ接続される。ＰＭＯＳトランジスタ５０７及び５０８は、ゲートがノードＮ２ｙ（即ち、ＰＭＯＳトランジスタ５０７のドレイン）と共通接続されることでカレントミラー（電流比は１：１）を構成する。 The PMOS transistors 507 and 508 are connected between the power line NP and the nodes N2y and N3y, respectively. The PMOS transistors 507 and 508 form a current mirror (current ratio is 1:1) by commonly connecting the gates to the node N2y (that is, the drain of the PMOS transistor 507).
　ＮＭＯＳトランジスタ５０９は、ノードＮ３ｘ及び接地ラインＮＬの間に接続され、ＮＭＯＳトランジスタ５１０は、ノードＮ３ｙ及び接地ラインＮＬの間に接続される。ＮＭＯＳトランジスタ５１１は、図７のＮＭＯＳトランジスタ５０４と同様に、ノードＮ４と接地ラインＮＬとの間に接続される。ノードＮ４に対しては、図２と同様の基準電流源４０から基準電流Ｉｒｅｆが供給される。 The NMOS transistor 509 is connected between the node N3x and the ground line NL, and the NMOS transistor 510 is connected between the node N3y and the ground line NL. NMOS transistor 511 is connected between node N4 and ground line NL, similar to NMOS transistor 504 in FIG. Reference current Iref is supplied to node N4 from reference current source 40 similar to that in FIG.
　ＮＭＯＳトランジスタ５０９～５１１のゲートは、ノードＮ４（ＮＭＯＳトランジスタ５１１のドレイン）と共通接続される。これにより、ＮＭＯＳトランジスタ５１１及び５０９によるカレントミラー（電流比は１：１）、並びに、ＮＭＯＳトランジスタ５１１及び５１０によるカレントミラー（電流比は１：１）が構成される。 The gates of NMOS transistors 509 to 511 are commonly connected to node N4 (the drain of NMOS transistor 511). As a result, a current mirror (with a current ratio of 1:1) is formed by the NMOS transistors 511 and 509 and a current mirror (with a current ratio of 1:1) is formed by the NMOS transistors 511 and 510 .
　次に、図１１に示された回路の動作を説明する。図１１の例では、内部回路１０ａの内部ノードＮＴａが選択されて、選択回路３２において、スイッチ３０４ａ及び３０５ａがオンされたときの動作を説明する。 Next, the operation of the circuit shown in FIG. 11 will be described. In the example of FIG. 11, the operation when the internal node NTa of the internal circuit 10a is selected and the switches 304a and 305a in the selection circuit 32 are turned on will be described.
　スイッチ３０５ａのオンにより、電源ラインＮＰから接地ラインＮＬへ、ＰＭＯＳトランジスタ５０５、スイッチ３０５ａ（ノードＮ１ａｘ）、ＮＭＯＳトランジスタ２０３ａ、及び、抵抗素子２０４ａを含む、出力電流Ｉｏｕｔｘの経路が生じる。出力電流Ｉｏｕｔｘは、図７における出力電流Ｉｏｕと同等である。 Turning on the switch 305a creates a path for the output current Ioutx from the power supply line NP to the ground line NL, including the PMOS transistor 505, the switch 305a (node N1ax), the NMOS transistor 203a, and the resistance element 204a. The output current Ioutx is equivalent to the output current Iou in FIG.
　同様に、スイッチ３０４ａのオンにより、電源ラインＮＰから接地ラインＮＬへ、ＰＭＯＳトランジスタ５０７、スイッチ３０４ａ（ノードＮ１ａｙ）、ＮＭＯＳトランジスタ２０５ａ、及び、抵抗素子２０６ａを含む、出力電流Ｉｏｕｔｙの経路が生じる。出力電流Ｉｏｕｔｙは、図７における出力電流Ｉｏｌと同等である。この様に、実施の形態４の電流比較器５２では、図７での出力電流Ｉｏｕ及びＩｏｌにそれぞれ相当する出力電流Ｉｏｕｔｘ及びＩｏｕｔｙが同時に発生する。即ち、電流比較器５０には、電圧電流変換回路２２によって生成された、変換比が異なる複数の出力電流Ｉｏｕｔｘ，Ｉｏｕｔｙが並列に入力される。 Similarly, turning on the switch 304a creates a path for the output current Iouty from the power supply line NP to the ground line NL, including the PMOS transistor 507, the switch 304a (node N1ay), the NMOS transistor 205a, and the resistance element 206a. The output current Iouty is equivalent to the output current Iol in FIG. Thus, in the current comparator 52 of the fourth embodiment, the output currents Ioutx and Iouty respectively corresponding to the output currents Iou and Iol in FIG. 7 are generated at the same time. That is, a plurality of output currents Ioutx and Iouty with different conversion ratios generated by the voltage-current conversion circuit 22 are input in parallel to the current comparator 50 .
　出力電流Ｉｏｕｔｘは、ＰＭＯＳトランジスタ５０５及び５０６によるカレントミラー（電流比１：１）によってコピーされる。同様に、出力電流Ｉｏｕｔｙは、ＰＭＯＳトランジスタ５０７及び５０８によるカレントミラー（電流比１：１）によってコピーされる。この結果、電流比較器５２では、ＰＭＯＳトランジスタ５０６によって、出力電流Ｉｏｕｔｘ相当の電流が、ノードＮ３ｘに供給されるとともに、ＰＭＯＳトランジスタ５０８によって、出力電流Ｉｏｕｔｙ相当の電流が、ノードＮ３ｙに供給される。 The output current Ioutx is copied by a current mirror (current ratio 1:1) by PMOS transistors 505 and 506. Similarly, the output current Iouty is copied by a current mirror (1:1 current ratio) by PMOS transistors 507 and 508 . As a result, in current comparator 52, PMOS transistor 506 supplies a current equivalent to output current Ioutx to node N3x, and PMOS transistor 508 supplies a current equivalent to output current Iouty to node N3y.
　一方で、基準電流源４０からノードＮ４に供給される基準電流Ｉｒｅｆが、ＮＭＯＳトランジスタ５１１及び５０９によるカレントミラー（電流比１：１）、及び、ＮＭＯＳトランジスタ５１１及び５１０によるカレントミラー（電流比１：１）によってコピーされる。これにより、ノードＮ３ｘから、ＰＭＯＳトランジスタ５０９によって、基準電流Ｉｒｅｆと同等の電流が引き抜かれる。同様に、ノードＮ３ｙから、ＰＭＯＳトランジスタ５１０によって、基準電流Ｉｒｅｆと同等の電流が引き抜かれる。 On the other hand, the reference current Iref supplied from the reference current source 40 to the node N4 is a current mirror by the NMOS transistors 511 and 509 (current ratio 1:1) and a current mirror by the NMOS transistors 511 and 510 (current ratio 1:1). 1). As a result, the PMOS transistor 509 extracts a current equivalent to the reference current Iref from the node N3x. Similarly, a current equivalent to reference current Iref is drawn from node N3y by PMOS transistor 510 .
　この結果、ノードＮ３ｘには、出力電流Ｉｏｕｔｘ（Ｉｏｕｔｘ＝Ｉｏｕ）と基準電流Ｉｒｅｆとの電流差を増幅した電圧Ｖ３ｘが生じる。これは、図７において、スイッチ３０３ａのオン時にノードＮ３に生じる電圧Ｖ３と同等である。従って、電圧Ｖ３ｘは、測定電圧Ｖｏｕｔと、判定電圧Ｖｔｕ（上限値側）との比較結果を示す電圧レベルに設定される。図７と同様に、Ｖｏｕｔ＜Ｖｔｕのときには、Ｉｏｕｔ＜Ｉｒｅｆとなるので、電圧Ｖ３ｘに相当する判定信号ＳｉｄｘはＬレベルに設定される。 As a result, a voltage V3x, which is obtained by amplifying the current difference between the output current Ioutx (Ioutx=Iou) and the reference current Iref, is generated at the node N3x. This is equivalent to the voltage V3 generated at the node N3 when the switch 303a is turned on in FIG. Therefore, the voltage V3x is set to a voltage level indicating the comparison result between the measured voltage Vout and the determination voltage Vtu (on the upper limit side). As in FIG. 7, when Vout<Vtu, Iout<Iref, so the determination signal Sidx corresponding to the voltage V3x is set to L level.
　一方で、ノードＮ３ｙには、出力電流Ｉｏｕｔｙ（Ｉｏｕｔｙ＝Ｉｏｕ）と基準電流Ｉｒｅｆとの電流差を増幅した電圧Ｖ３ｙが生じる。これは、図７において、スイッチ３０２ａのオン時にノードＮ３に生じる電圧Ｖ３と同等である。従って、電圧Ｖ３ｙは、測定電圧Ｖｏｕｔと、判定電圧Ｖｔｌ（下限値側）との比較結果を示す電圧レベルに設定される。図７と同様に、Ｖｏｕｔ＞Ｖｔｌのときには、Ｉｏｕｔ＝Ｉｏｌ＞Ｉｒｅｆとなるので、電圧Ｖ３ｙに相当する判定信号ＳｉｄｙはＨレベルに設定される。 On the other hand, a voltage V3y generated by amplifying the current difference between the output current Iouty (Iouty=Iou) and the reference current Iref is generated at the node N3y. This is equivalent to the voltage V3 generated at the node N3 when the switch 302a is turned on in FIG. Therefore, the voltage V3y is set to a voltage level indicating the comparison result between the measured voltage Vout and the determination voltage Vtl (lower limit side). As in FIG. 7, when Vout>Vtl, Iout=Iol>Iref, so the determination signal Sidy corresponding to the voltage V3y is set to H level.
　判定論理回路６０は、インバータ６０１及びＮＡＮＤ（否定論理積）ゲート６０２を有する。インバータ６０１は、判定信号Ｓｉｄｘを反転して出力する。ＮＡＮＤゲート６０２には、インバータ６１０の出力電圧と、判定信号Ｓｉｄｙとが入力されて、判定信号Ｓｊｄを出力する。図１１の構成では、判定論理回路６０からの判定信号Ｓｊｄを、半導体集積回路装置５ｆの外部からコンタクト可能な端子６に出力することができる。 The decision logic circuit 60 has an inverter 601 and a NAND (negative logical product) gate 602 . Inverter 601 inverts and outputs determination signal Sidx. The output voltage of the inverter 610 and the determination signal Sidy are input to the NAND gate 602 to output the determination signal Sjd. In the configuration of FIG. 11, the determination signal Sjd from the determination logic circuit 60 can be output to the terminal 6 that can be contacted from the outside of the semiconductor integrated circuit device 5f.
　従って、上述した、Ｖｏｕｔ＜Ｖｔｕ（Ｖ３ｘ＝Ｌレベル）、及び、Ｖｏｕｔ＞Ｖｔｌ（Ｖ３ｙ＝Ｈレベル）の両方が成立して、測定電圧Ｖｏｕｔが、Ｖｔｌ＜Ｖｏｕｔ＜Ｖｔｕの電圧範囲（正常範囲）に含まれる場合には、判定信号Ｓｊｄ＝Ｌレベルに設定される。これに対して、測定電圧Ｖｏｕｔが、Ｖｔｌ＜Ｖｏｕｔ＜Ｖｔｕの電圧範囲（正常範囲）に含まれない場合には、Ｖｏｕｔ＜Ｖｔｕ、及び、Ｖｏｕｔ＞Ｖｔｌのいずれが不成立になるので、判定信号Ｓｊｄ＝Ｈレベルに設定される。 Therefore, both Vout<Vtu (V3x=L level) and Vout>Vtl (V3y=H level) are established, and the measured voltage Vout is in the voltage range (normal range) of Vtl<Vout<Vtu. , the determination signal Sjd is set to L level. On the other hand, when the measured voltage Vout is not included in the voltage range (normal range) of Vtl<Vout<Vtu, either Vout<Vtu or Vout>Vtl is not established, so the determination signal Sjd =H level.
　以上説明した様に、実施の形態４に係る半導体集積回路装置において、電流比較器５２では、測定電圧Ｖｏｕｔ及び判定電圧Ｖｔｌ（下限値側）の比較と、測定電圧Ｖｏｕｔ及び判定電圧Ｖｔｕ（上限値側）との比較とを同時刻に行うことができる。 As described above, in the semiconductor integrated circuit device according to the fourth embodiment, the current comparator 52 compares the measured voltage Vout and the determination voltage Vtl (lower limit side), and compares the measured voltage Vout and the determination voltage Vtu (upper limit side). side) can be performed at the same time.
　これに対して、実施の形態２及び３の構成では、測定電圧Ｖｏｕｔは、１個の判定電圧としか比較できないので、測定電圧Ｖｏｕｔが、上限値及び下限値によって規定される正常範囲内に含まれるか否かの判定は、異なるタイミングでの判定信号Ｓｊｄを用いて実行することが必要になる。 On the other hand, in the configurations of Embodiments 2 and 3, the measured voltage Vout can be compared with only one judgment voltage, so that the measured voltage Vout falls within the normal range defined by the upper and lower limits. It is necessary to use the determination signal Sjd at different timings to determine whether or not it will be possible.
　この結果、実施の形態４の構成によれば、実施の形態２と同様の測定電圧Ｖｏｕｔと複数の判定電圧との比較、例えば、正常範囲の下限値及び上限値との比較による測定電圧Ｖｏｕｔが正常範囲内であるか否かの判定を、実施の形態２よりも高速に行うことができる。即ち、実施の形態４に係る半導体集積回路装置では、実施の形態２で説明した効果に加えて、更なるテスト時間の短縮が可能となる。 As a result, according to the configuration of the fourth embodiment, the measured voltage Vout obtained by comparing the same measured voltage Vout as in the second embodiment with a plurality of judgment voltages, for example, the lower limit value and the upper limit value of the normal range is It is possible to determine whether or not it is within the normal range at a higher speed than in the second embodiment. That is, in the semiconductor integrated circuit device according to the fourth embodiment, in addition to the effect described in the second embodiment, it is possible to further shorten the test time.
　尚、実施の形態４においても、実施の形態１で説明した変形例１及び変形例２を適用することが可能である。即ち、電圧電流変換回路２１、電流比較器５１，及び、基準電流源４０において、電源ラインＮＰ及び接地ラインＮＬの位置の入れ替え、並びに、ＮＭＯＳトランジスタ及びＰＭＯＳトランジスタの入れ替えを行うことにより、ＰＭＯＳトランジスタを用いて電圧電流変換を行うことが可能である。或いは、電圧電流変換回路２１及び基準電流源４０にオペアンプバッファ（図４、図５）を追加することで、ＭＯＳトランジスタのばらつき及び温度変動の影響を抑制して、判定の高精度化を図ることができる。 It should be noted that Modification 1 and Modification 2 described in Embodiment 1 can also be applied to Embodiment 4. That is, in the voltage-current conversion circuit 21, the current comparator 51, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged, so that the PMOS transistor is It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 21 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
　実施の形態５．
　実施の形態５では、実施の形態４での選択回路３２の配置を省略するための回路構成を説明する。 Embodiment 5.
In the fifth embodiment, a circuit configuration for omitting the placement of the selection circuit 32 in the fourth embodiment will be described.
　図１２は、実施の形態５に係る半導体集積回路装置５ｅの構成を示すブロック図である。 FIG. 12 is a block diagram showing the configuration of a semiconductor integrated circuit device 5e according to the fifth embodiment.
　図１２に示される様に、半導体集積回路装置５ｅは、実施の形態４に係る半導体集積回路装置５ｄ（図１０）と比較して、選択回路３２の配置が省略される点と、電圧電流変換回路２１に代えて電圧電流変換回路２３が配置される点が異なる。各電圧電流変換回路２１には、イネーブル信号ＥＮが入力される。図１２においても、Ｎ＝４の構成が示されており、内部回路１０ａ～１０ｄにそれぞれ対応して配置される電圧電流変換回路２３ａ～２３ｄに対して、個別のイネーブル信号ＥＮａ～ＥＮｄがそれぞれ入力される。イネーブル信号ＥＮａ～ＥＮｄのうちの１個は、内部回路１０ａ～１０ｄの内部ノードＮＴａ～ＮＴｄを測定対象に選択するためにＨレベルに設定される。一方で、イネーブル信号ＥＮａ～ＥＮｄの残りの３個はＬレベルに設定される。 As shown in FIG. 12, a semiconductor integrated circuit device 5e is different from the semiconductor integrated circuit device 5d (FIG. 10) according to the fourth embodiment in that the arrangement of the selection circuit 32 is omitted, and voltage-current conversion is performed. The difference is that a voltage-current conversion circuit 23 is arranged instead of the circuit 21 . An enable signal EN is input to each voltage-current conversion circuit 21 . FIG. 12 also shows a configuration where N=4, and individual enable signals ENa-ENd are input to voltage-current conversion circuits 23a-23d arranged corresponding to internal circuits 10a-10d, respectively. be done. One of enable signals ENa-ENd is set to H level to select internal nodes NTa-NTd of internal circuits 10a-10d to be measured. On the other hand, the remaining three enable signals ENa-ENd are set to L level.
　図１３には、図１２に示された各ブロックの内部構成を説明するための回路図が示される。図１３においても、内部回路１０ａに対応する構成が添字ａを付して代表的に示されるが、同様の構成が、各内部回路１０に対応して配置されている。 FIG. 13 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. In FIG. 13 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10. In FIG.
　図１３に示される様に、電圧電流変換回路２３ａは、図１１の電圧電流変換回路２１ａと比較して、抵抗素子２０４ａ及び２０６ａと接地ラインＮＬとの間に、抵抗素子２０４ａ及び２０６ａの各々に対して直列接続されたイネーブルスイッチ２０７ａを更に含む。イネーブルスイッチ２０７ａは、イネーブル信号ＥＮａに応じてオンオフする。 As shown in FIG. 13, the voltage-to-current conversion circuit 23a is different from the voltage-to-current conversion circuit 21a of FIG. It further includes an enable switch 207a connected in series therewith. The enable switch 207a is turned on and off according to the enable signal ENa.
　更に、実施の形態５では、図１１での選択回路３２が配置されないため、各電圧電流変換回路２３の２個のノードは、電流比較器５１のノードＮ２ｘ及びＮ２ｙのそれぞれと、スイッチを介することなく接続される。例えば、電圧電流変換回路２３ａのノードＮ１ａｘ及びＮ１ａｙは、スイッチを介することなく、電流比較器５１のノードＮ２ｘ及びＮ２ｙとそれぞれ接続される。 Furthermore, in the fifth embodiment, since the selection circuit 32 in FIG. 11 is not arranged, the two nodes of each voltage-to-current conversion circuit 23 are connected to the nodes N2x and N2y of the current comparator 51 and through switches. connected without For example, nodes N1ax and N1ay of the voltage-current conversion circuit 23a are connected to nodes N2x and N2y of the current comparator 51, respectively, without switches.
　イネーブル信号ＥＮａがＨレベルに設定されて、イネーブルスイッチ２０７ａがオンすると、電圧電流変換回路２３ａは、電流比較器５１のノードＮ２ｘ及びＮ２ｙに対して、電圧電流変換回路２１ａと同様の回路状態で接続される。従って、電圧電流変換回路２３ａによって、図１１と同様の出力電流Ｉｏｕｔｘ及びＩｏｕｔｙを、電流比較器５１に入力することができる。これにより、実施の形態４と同様の、測定電圧Ｖｏｕｔと、判定電圧Ｖｌｕ及びＶｔｌとの比較に基づく、判定信号Ｓｊｄを生成することができる。 When the enable signal ENa is set to H level and the enable switch 207a is turned on, the voltage-current conversion circuit 23a is connected to the nodes N2x and N2y of the current comparator 51 in the same circuit state as the voltage-current conversion circuit 21a. be done. Therefore, output currents Ioutx and Iouty similar to those in FIG. This makes it possible to generate the determination signal Sjd based on the comparison between the measured voltage Vout and the determination voltages Vlu and Vtl, as in the fourth embodiment.
　これに対して、イネーブル信号ＥＮａがＬレベルに設定されて、イネーブルスイッチ２０７ａがオフすると、電圧電流変換回路２３ａにおいて、出力電流Ｉｏｕｔｘ及びＩｏｕｔｙの経路が遮断される。これにより、図１１において、選択回路３２のスイッチ３０４ａ及び３０５ａがオフされた場合と同様に、電流比較器５１において、内部ノードＮＴａの測定電圧Ｖｏｕｔに従う出力電流Ｉｏｕｔｘ及びＩｏｕｔｙは生成されない。この場合は、他の電圧電流変換回路２３（図１２での電圧電流変換回路２３ｂ～２３ｄのうちの１個が選択されて、対応するイネーブル信号ＥＮがＨレベルに設定される。そして、電流比較器５１では、選択された電圧電流変換回路２３に入力される測定電圧Ｖｏｕｔに従った出力電流Ｉｏｕｔｘ及びＩｏｕｔｙが生成されて、基準電流Ｉｒｅｆと比較されることになる。 On the other hand, when the enable signal ENa is set to L level and the enable switch 207a is turned off, the paths of the output currents Ioutx and Iouty are cut off in the voltage-current conversion circuit 23a. As a result, current comparator 51 does not generate output currents Ioutx and Iouty according to measured voltage Vout of internal node NTa, similarly to the case where switches 304a and 305a of selection circuit 32 are turned off in FIG. In this case, another voltage-to-current conversion circuit 23 (one of the voltage-to-current conversion circuits 23b to 23d in FIG. 12) is selected, and the corresponding enable signal EN is set to H level. The unit 51 generates output currents Ioutx and Iouty according to the measured voltage Vout input to the selected voltage-current conversion circuit 23 and compares them with the reference current Iref.
　この様に、実施の形態５に係る半導体集積回路装置では、選択回路３２の配置を省略して、実施の形態４に係る半導体装置と同様の測定電圧Ｖｏｕｔと、複数の判定電圧Ｖｔｕ，Ｖｙｌとの比較による判定を実行することができる。従って、実施の形態４の半導体集積回路装置による効果に加えて、回路の小型化の効果を更に享受することができる。 As described above, in the semiconductor integrated circuit device according to the fifth embodiment, the arrangement of the selection circuit 32 is omitted, and the same measurement voltage Vout and the plurality of determination voltages Vtu and Vyl as in the semiconductor device according to the fourth embodiment are used. A determination can be made by comparing the Therefore, in addition to the effect of the semiconductor integrated circuit device of the fourth embodiment, the effect of miniaturization of the circuit can be further enjoyed.
　尚、実施の形態５においても、実施の形態１で説明した変形例１及び変形例２を適用することが可能である。即ち、電圧電流変換回路２２、電流比較器５０，及び、基準電流源４０において、電源ラインＮＰ及び接地ラインＮＬの位置の入れ替え、並びに、ＮＭＯＳトランジスタ及びＰＭＯＳトランジスタの入れ替えを行うことにより、ＰＭＯＳトランジスタを用いて電圧電流変換を行うことが可能である。或いは、電圧電流変換回路２２及び基準電流源４０にオペアンプバッファ（図４、図５）を追加することで、ＭＯＳトランジスタのばらつき及び温度変動の影響を抑制して、判定の高精度化を図ることができる。 Also in Embodiment 5, Modification 1 and Modification 2 described in Embodiment 1 can be applied. That is, in the voltage-current conversion circuit 22, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged to replace the PMOS transistor. It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 22 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
　更に、実施の形態５は、実施の形態１～３、並びに、実施の形態１～３に変形例１及び／又は変形例２を適用した構成と組み合わせることも可能である。具体的には、電圧電流変換回路２０ａ（図２）及び電圧電流変換回路２０ａ♯（図４）において抵抗素子２０２ａと直列にイネーブルスイッチ２０７ａを接続することで、実施の形態１又は変形例１が適用された実施の形態１と、実施の形態５とを組み合わせることができる。同様に、電圧電流変換回路２０ｐａ（図３）において抵抗素子２０２ｐａと直列にイネーブルスイッチ２０７ａを接続することで、変形例２が適用された実施の形態１と、実施の形態５とを組み合わせることができる。 Furthermore, Embodiment 5 can be combined with Embodiments 1 to 3 and configurations obtained by applying Modification 1 and/or Modification 2 to Embodiments 1 to 3. Specifically, by connecting the enable switch 207a in series with the resistance element 202a in the voltage-current conversion circuit 20a (FIG. 2) and the voltage-current conversion circuit 20a# (FIG. 4), the first embodiment or the modified example 1 Applied Embodiment 1 and Embodiment 5 can be combined. Similarly, by connecting the enable switch 207a in series with the resistance element 202pa in the voltage-current conversion circuit 20pa (FIG. 3), it is possible to combine the first embodiment to which the modification 2 is applied and the fifth embodiment. can.
　又、電圧電流変換回路２１ａ（図７）において抵抗素子２０４ａ及び２０６ａと接地ラインＮＬとの間に、図１３と同じ態様でイネーブルスイッチ２０７ａを接続することで、実施の形態２と、実施の形態５とを組み合わせることができる。又、電圧電流変換回路２２ａ（図９）において、抵抗素子２０９ａ及び２１０ａと直列に、かつ、トランジスタスイッチ２０８ａによる短絡経路からは外れる様に、イネーブルスイッチ２０７ａを接続することで、実施の形態３と、実施の形態５とを組み合わせることも可能である。 Further, by connecting an enable switch 207a between the resistor elements 204a and 206a and the ground line NL in the voltage-current conversion circuit 21a (FIG. 7) in the same manner as in FIG. 5 can be combined. In addition, in the voltage-current conversion circuit 22a (FIG. 9), by connecting the enable switch 207a in series with the resistance elements 209a and 210a and out of the short-circuit path by the transistor switch 208a, , and Embodiment 5 can be combined.
　実施の形態６．
　実施の形態６では、実施の形態４，５での判定結果を用いた異常対応構成について説明する。 Embodiment 6.
In a sixth embodiment, an abnormality handling configuration using the determination results in the fourth and fifth embodiments will be described.
　図１４は、実施の形態６に係る半導体集積回路装置５ｆの構成を示すブロック図である。 FIG. 14 is a block diagram showing the configuration of a semiconductor integrated circuit device 5f according to the sixth embodiment.
　図１４に示される様に、半導体集積回路装置５ｆは、Ｎ個の内部回路１０の各々を、同一機能の内部回路（以下、「第１内部回路」とも称する）１１及び内部回路（以下、「第２内部回路」とも称する）１２によって構成するとともに、各内部回路１０において、第１内部回路１１に故障が検出されたときに第２内部回路１２に切り替える異常対応構成を具備している。 As shown in FIG. 14, a semiconductor integrated circuit device 5f includes N internal circuits 10 each composed of an internal circuit (hereinafter also referred to as "first internal circuit") 11 having the same function and an internal circuit (hereinafter also referred to as " 12, and each internal circuit 10 has an abnormality response configuration that switches to the second internal circuit 12 when a failure is detected in the first internal circuit 11.
　図１４においても、Ｎ＝４の例が示される。即ち、内部回路１０ａは、第１内部回路１１ａ及び第２内部回路１２ａを有し、内部回路１０ｂは、第１内部回路１１ｂ及び第２内部回路１２ｂを有し、内部回路１０ｃは、第１内部回路１１ｃ及び第２内部回路１２ｃを有し、内部回路１０ｄは、第１内部回路１１ｄ及び第２内部回路１２ｄを有する。 FIG. 14 also shows an example of N=4. That is, the internal circuit 10a has a first internal circuit 11a and a second internal circuit 12a, the internal circuit 10b has a first internal circuit 11b and a second internal circuit 12b, and the internal circuit 10c has a first internal circuit. It has a circuit 11c and a second internal circuit 12c, and the internal circuit 10d has a first internal circuit 11d and a second internal circuit 12d.
　半導体集積回路装置５ｆは、半導体集積回路装置５ｄ（図１０）と同様の、電圧電流変換回路２１ａ～２１ｄ、選択回路３２，基準電流源４０，電流比較器５１，及び、判定論理回路６０に加えて、上記異常対応構成のための、選択回路１５ａ～１５ｄ、判定結果選択回路７０、記録装置８０ａ～８０ｄ、及び、制御論理回路９ａ～９ｄを更に備える。 The semiconductor integrated circuit device 5f includes voltage-to-current conversion circuits 21a to 21d, a selection circuit 32, a reference current source 40, a current comparator 51, and a decision logic circuit 60 similar to the semiconductor integrated circuit device 5d (FIG. 10). Further, selection circuits 15a to 15d, a judgment result selection circuit 70, recording devices 80a to 80d, and control logic circuits 9a to 9d are further provided for the above-described abnormality handling configuration.
　図１５には、図１４に記載された各ブロックの内部構成を説明するための回路図が示される。図１５においても、内部回路１０ａに対応する構成が添字ａを付して示されるが、同様の構成が、各内部回路１０に対応して配置されている。 FIG. 15 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. In FIG. 15 as well, the structure corresponding to internal circuit 10a is indicated with a suffix a, and the same structure is arranged corresponding to each internal circuit 10. As shown in FIG.
　選択回路１５は、スイッチ１００１ａ～１００４ａを有する。スイッチ１００１ａ及び１００２ａは、第１内部回路１１ａ及び第２内部回路１２ａと、内部回路１０ａの出力電圧を入力とする、半導体集積回路装置５ｆに搭載される他の実回路（図示せず）との間に接続される。スイッチ１００１ａは、制御信号Ａａに応じてオンオフされる一方で、スイッチ１００１ａは、制御信号／Ａａ（Ａａの反転信号）に応じてオンオフされる。これにより、第１内部回路１１ａ及び第２内部回路１２ａの一方の出力電圧が、実回路へ入力される。 The selection circuit 15 has switches 1001a to 1004a. The switches 1001a and 1002a connect the first internal circuit 11a, the second internal circuit 12a, and another actual circuit (not shown) mounted on the semiconductor integrated circuit device 5f to which the output voltage of the internal circuit 10a is input. connected between Switch 1001a is turned on and off according to control signal Aa, while switch 1001a is turned on and off according to control signal /Aa (inverted signal of Aa). As a result, the output voltage of one of the first internal circuit 11a and the second internal circuit 12a is input to the actual circuit.
　スイッチ１００３ａは、第１内部回路１１ａの出力ノードに相当する内部ノードＮＴ１ａと、電圧電流変換回路２１ａとの間に接続される。スイッチ１００４ａは、第２内部回路１２ａの出力ノードに相当する内部ノードＮＴ２ａと、電圧電流変換回路２１ａとの間に接続される。 The switch 1003a is connected between the internal node NT1a corresponding to the output node of the first internal circuit 11a and the voltage-current conversion circuit 21a. Switch 1004a is connected between internal node NT2a corresponding to the output node of second internal circuit 12a and voltage-current conversion circuit 21a.
　スイッチ１００３ａのオン時には、内部ノードＮＴ１ａの電圧、即ち、第１内部回路１１ａの出力電圧が、測定電圧Ｖｏｕｔとして、電圧電流変換回路２１ａに入力される。これに対して、スイッチ１００４ａのオン時には、内部ノードＮＴ２ａの電圧、即ち、第２内部回路１２ａの出力電圧が、測定電圧Ｖｏｕｔとして、電圧電流変換回路２１ａに入力される。 When the switch 1003a is turned on, the voltage of the internal node NT1a, that is, the output voltage of the first internal circuit 11a is input to the voltage-current conversion circuit 21a as the measurement voltage Vout. On the other hand, when the switch 1004a is turned on, the voltage of the internal node NT2a, that is, the output voltage of the second internal circuit 12a is input to the voltage-current conversion circuit 21a as the measurement voltage Vout.
　スイッチ１００３ａ，１００４ａの制御により、第１内部回路１１ａの出力電圧、及び、第２内部回路１２ａの出力電圧の各々について、実施の形態５で説明したのと同様に、第１内部回路１１ａの出力電圧（Ｖｏｕｔ）が、Ｖｔｌ＜Ｖｏｕｔ＜Ｖｔｕの範囲（正常範囲）に含まれているかを示す判定信号ＳｊｄをノードＮ２０に得ることができる。 By controlling the switches 1003a and 1004a, the output voltage of the first internal circuit 11a and the output voltage of the second internal circuit 12a are changed in the same manner as described in the fifth embodiment. A determination signal Sjd indicating whether the voltage (Vout) is within the range of Vtl<Vout<Vtu (normal range) can be obtained at the node N20.
　判定結果選択回路７０は、スイッチ７０１ａ～７０１ｄ，７０２ａ～７０２ｄを有する。内部回路１０ａに対応する記録装置８０ａは、第１ラッチ回路８０１ａと、第２ラッチ回路８０２ａと、ＮＡＮＤゲート８０３ａとを有する。 The determination result selection circuit 70 has switches 701a to 701d and 702a to 702d. A recording device 80a corresponding to the internal circuit 10a has a first latch circuit 801a, a second latch circuit 802a, and a NAND gate 803a.
　スイッチ７０１ａは、ノードＮ２０と、第１ラッチ回路８０１ａとの間に接続される。第１ラッチ回路８０１ａは、内部回路１０ａに含まれる第１内部回路１１ａに対する判定信号Ｓｊｄを記憶するために配置される。従って、スイッチ７０１ａは、スイッチ１００３ａと連動してオン期間が設けられる。 The switch 701a is connected between the node N20 and the first latch circuit 801a. The first latch circuit 801a is arranged to store the determination signal Sjd for the first internal circuit 11a included in the internal circuit 10a. Therefore, the switch 701a is provided with an ON period in conjunction with the switch 1003a.
　同様に、スイッチ７０２ａは、ノードＮ２０と、第２ラッチ回路８０２ａとの間に接続される。第２ラッチ回路８０２ａは、内部回路１０ａに含まれる第２内部回路１２ａに対する判定信号Ｓｊｄを記憶するために配置される。従って、スイッチ７０２ａは、スイッチ１００４ａと連動してオン期間が設けられる。 Similarly, the switch 702a is connected between the node N20 and the second latch circuit 802a. Second latch circuit 802a is arranged to store determination signal Sjd for second internal circuit 12a included in internal circuit 10a. Therefore, the switch 702a is provided with an ON period in conjunction with the switch 1004a.
　図示は省略しているが、内部回路１０ｂ～１０ｄのそれぞれに対応して配置される記録装置８０ｂ～８０ｄの各々にも、第１内部回路１１の判定結果を記憶する第１ラッチ回路８０１、及び、第２内部回路１２の判定結果を記憶する第２ラッチ回路８０２が含まれる。更に、判定結果選択回路７０では、記録装置８０ｂ～８０ｄと、判定論理回路６０から判定信号Ｓｊｄが出力されるノードＮ２０との間に、第１ラッチ回路に至るスイッチ７０１及び第２ラッチ回路に至るスイッチ７０２が配置される。 Although not shown, each of the recording devices 80b to 80d arranged corresponding to each of the internal circuits 10b to 10d also has a first latch circuit 801 for storing the judgment result of the first internal circuit 11, and , and a second latch circuit 802 for storing the determination result of the second internal circuit 12 . Further, in the determination result selection circuit 70, between the recording devices 80b to 80d and the node N20 to which the determination signal Sjd is output from the determination logic circuit 60, a switch 701 leading to the first latch circuit and a second latch circuit are provided. A switch 702 is provided.
　ＮＡＮＤゲート８０３ａは、第１ラッチ回路８０１ａのラッチデータＳ１１ａ及び第２ラッチ回路８０２ａのラッチデータＳ１２ａを入力として、内部回路正常信号／Ｅａを出力する。 The NAND gate 803a receives the latch data S11a of the first latch circuit 801a and the latch data S12a of the second latch circuit 802a, and outputs the internal circuit normal signal /Ea.
　制御論理回路９ａは、ＮＡＮＤゲート９０１ａと、インバータ９０２ａとを有する。ＮＡＮＤゲート９０１ａは、ラッチデータＳ１１ａと、ラッチデータＳ１２ａの反転データとを入力として、スイッチ１００１ａの制御信号Ａａを出力する。インバータ９０２ａは、ＮＡＮＤゲート９０１ａの出力信号を反転して、スイッチ１００２ａの制御信号／Ａａを出力する。 The control logic circuit 9a has a NAND gate 901a and an inverter 902a. The NAND gate 901a receives the latch data S11a and the inverted data of the latch data S12a as inputs, and outputs a control signal Aa for the switch 1001a. Inverter 902a inverts the output signal of NAND gate 901a to output control signal /Aa for switch 1002a.
　図１６には、半導体集積回路装置５ｆの動作を説明するための信号波形図が示される。
　図１６を参照して、第１内部回路１１ａ及び第２内部回路１２ａの出力電圧を判定するための内部回路１０ａのテストタイミングにおいて、選択回路３２のスイッチ３０４ａ，３０５ａがオンされて、内部回路１０ａに対応する電圧電流変換回路２１ａが電流比較器５１と接続される。 FIG. 16 shows a signal waveform diagram for describing the operation of semiconductor integrated circuit device 5f.
Referring to FIG. 16, at the test timing of internal circuit 10a for determining the output voltages of first internal circuit 11a and second internal circuit 12a, switches 304a and 305a of selection circuit 32 are turned on, and internal circuit 10a is connected to the current comparator 51 .
　内部回路１０ａのテストタイミングでは、第１内部回路１１ａの出力電圧と、第２内部回路１２ａの出力電圧とが順に判定される。まず、スイッチ１００３ａ及び７０１ａをオンすることで、第１内部回路１１ａの出力電圧（Ｖｏｕｔ）が、Ｖｔｌ＜Ｖｏｕｔ＜Ｖｔｕの範囲（正常範囲）に含まれているかを示す判定信号Ｓｊｄが、第１ラッチ回路８０１ａに入力される。第１内部回路１１ａの判定結果が正常であれば、第１ラッチ回路８０１ａのラッチデータＳ１１ａはＬレベルとなる。 At the test timing of the internal circuit 10a, the output voltage of the first internal circuit 11a and the output voltage of the second internal circuit 12a are determined in order. First, by turning on the switches 1003a and 701a, the determination signal Sjd indicating whether the output voltage (Vout) of the first internal circuit 11a is within the range of Vtl<Vout<Vtu (normal range) is output to the first It is input to the latch circuit 801a. If the determination result of the first internal circuit 11a is normal, the latch data S11a of the first latch circuit 801a becomes L level.
　次に、スイッチ１００４ａ及び７０２ａをオンすることで、第２内部回路１２ａの出力電圧（Ｖｏｕｔ）が、Ｖｔｌ＜Ｖｏｕｔ＜Ｖｔｕの範囲（正常範囲）に含まれているかを示す判定信号Ｓｊｄが、第２ラッチ回路８０２ａに入力される。第１内部回路１１ａの判定結果が正常であれば、第２ラッチ回路８０２ａのラッチデータＳ１２ａはＬレベルとなる。 Next, by turning on the switches 1004a and 702a, the determination signal Sjd indicating whether the output voltage (Vout) of the second internal circuit 12a is within the range of Vtl<Vout<Vtu (normal range) is generated. 2 is input to the latch circuit 802a. If the determination result of the first internal circuit 11a is normal, the latch data S12a of the second latch circuit 802a becomes L level.
　第１ラッチ回路８０１ａは「第１記憶回路」の一実施例に対応し、ラッチデータＳ１１ａは「第１情報」の一実施例に対応する。第２ラッチ回路８０２ａは「第２記憶回路」の一実施例に対応し、ラッチデータＳ１２ａは「第２情報」の一実施例に対応する。又、選択回路１５ａのうちの、スイッチ１００３ａ，１００４ａによって、「測定選択回路」の一実施例を構成することができる。 The first latch circuit 801a corresponds to an example of "first storage circuit", and the latch data S11a corresponds to an example of "first information". The second latch circuit 802a corresponds to an example of the "second storage circuit", and the latch data S12a corresponds to an example of the "second information". Also, the switches 1003a and 1004a in the selection circuit 15a can constitute an embodiment of the "measurement selection circuit".
　第１内部回路１１ａ及び第２内部回路１２ａの出力電圧の判定が終了すると、内部回路１０ａのテストタイミングが終了されて、内部回路１０ｂのテストタイミングが設けられる。内部回路１０ｂのテストタイミングでは、第１内部回路１１ｂの出力電圧と、第２内部回路１２ｂの出力電圧とを順に判定する様に、内部回路１０ｂに対応するスイッチ１００３ｂ，１００４ｂ，３０４ｂ，３０５ｂ，７０１ｂ，７０２ｂが、内部回路１０ａのテストタイミングでのスイッチ１００３ａ，１００４ａ，３０４ａ，３０５ａ，７０１ａ，７０２ａと同じ態様でオンオフされる。 When the determination of the output voltages of the first internal circuit 11a and the second internal circuit 12a is finished, the test timing of the internal circuit 10a is finished, and the test timing of the internal circuit 10b is provided. At the test timing of the internal circuit 10b, switches 1003b, 1004b, 304b, 305b, and 701b corresponding to the internal circuit 10b are selected so that the output voltage of the first internal circuit 11b and the output voltage of the second internal circuit 12b are sequentially determined. , 702b are turned on and off in the same manner as switches 1003a, 1004a, 304a, 305a, 701a and 702a at the test timing of internal circuit 10a.
　図１７には、第１及び第２内部回路の判定結果に対する異常検出構成の動作を説明する図表が示される。図１７に示される様に、第１及び第２内部回路の判定結果の組み合わせにはケース１～ケース４が存在する。 FIG. 17 shows a chart for explaining the operation of the abnormality detection configuration with respect to the judgment results of the first and second internal circuits. As shown in FIG. 17, there are cases 1 to 4 in combination of determination results of the first and second internal circuits.
　ケース１では、第１内部回路１１ａ及び第２内部回路１２ａとも出力電圧（Ｖｏｕｔ）が正常である（Ｓ１１ａ＝Ｓ１２ａ＝Ｌ）。このとき、制御信号ＡａがＨレベルに設定される一方で、制御信号／ＡａはＬレベルに設定される。即ち、第１内部回路１１ａの出力が、スイッチ１００１ａによって実回路へ伝達される。又、内部回路異常信号／Ｅａは、Ｈレベルに設定される。 In case 1, the output voltages (Vout) of both the first internal circuit 11a and the second internal circuit 12a are normal (S11a=S12a=L). At this time, control signal Aa is set to H level, while control signal /Aa is set to L level. That is, the output of the first internal circuit 11a is transmitted to the actual circuit by the switch 1001a. Also, the internal circuit abnormality signal /Ea is set to H level.
　ケース２では、第１内部回路１１ａの出力電圧が正常（Ｓ１１ａ＝Ｌ）である一方で、第２内部回路１２ａの出力電圧が異常（Ｓ１２ａ＝Ｈ）であり、第２内部回路１２ａが故障している。この場合にも、ケース１と同様に、制御信号ＡａがＨレベルに設定される一方で、制御信号／ＡａはＬレベルに設定される。即ち、第１内部回路１１ａの出力が、スイッチ１００１ａによって実回路へ伝達される。又、内部回路異常信号／Ｅａは、Ｈレベルに設定される。 In case 2, the output voltage of the first internal circuit 11a is normal (S11a=L), while the output voltage of the second internal circuit 12a is abnormal (S12a=H), and the second internal circuit 12a fails. ing. Also in this case, similarly to case 1, control signal Aa is set to H level, while control signal /Aa is set to L level. That is, the output of the first internal circuit 11a is transmitted to the actual circuit by the switch 1001a. Also, the internal circuit abnormality signal /Ea is set to H level.
　ケース３では、ケース２と反対に、第２内部回路１２ａの出力電圧が正常（Ｓ１２ａ＝Ｌ）である一方で、第１内部回路１１ａの出力が異常（Ｓ１１ａ＝Ｈ）であり、第１内部回路１１ａが故障している。この場合には、制御信号ＡａがＬレベルに設定される一方で、制御信号／ＡａはＨレベルに設定される。即ち、第２内部回路１２ａの出力が、スイッチ１００２ａによって実回路へ伝達される。又、内部回路異常信号／Ｅａは、Ｈレベルに設定される。この様に、選択回路１５ａのうちの、スイッチ１００１ａ，１００２ａによって、「出力択回路」の一実施例を構成することができる。 In case 3, contrary to case 2, the output voltage of the second internal circuit 12a is normal (S12a=L), while the output of the first internal circuit 11a is abnormal (S11a=H). Circuit 11a is faulty. In this case, control signal Aa is set to L level, while control signal /Aa is set to H level. That is, the output of the second internal circuit 12a is transmitted to the actual circuit by the switch 1002a. Also, the internal circuit abnormality signal /Ea is set to H level. In this manner, the switches 1001a and 1002a in the selection circuit 15a can constitute an embodiment of the "output selection circuit".
　ケース４では、第１内部回路１１ａ及び第２内部回路１２ａともに出力電圧が異常であり（Ｓ１１ａ＝Ｓ１２ａ＝Ｌ）、第１内部回路１１ａ及び第２内部回路１２ａの両方が故障している。この場合には、内部回路異常信号／Ｅａが、ケース１～ケース３とは異なり、Ｌレベルに設定される。制御信号Ａａ，／Ａａについては、ケース１及びケース２と同様に設定される。 In case 4, the output voltages of both the first internal circuit 11a and the second internal circuit 12a are abnormal (S11a=S12a=L), and both the first internal circuit 11a and the second internal circuit 12a are out of order. In this case, unlike cases 1 to 3, internal circuit abnormality signal /Ea is set to the L level. The control signals Aa and /Aa are set in the same manner as in cases 1 and 2. FIG.
　この様に、第１内部回路１１ａを実使用のデフォルト回路とし、第１内部回路１１ａの故障時には、判定結果が正常であることを条件に予備用の第２内部回路１２ａを、実使用の回路に自動的に切替える異常対応構成が実現される。これにより、内部回路の故障発生時にも、半導体集積回路装置５ｅの動作を継続することが可能となる。 In this manner, the first internal circuit 11a is used as the default circuit for actual use, and when the first internal circuit 11a fails, the second internal circuit 12a for backup is used as the circuit for actual use on condition that the determination result is normal. An abnormality handling configuration that automatically switches to . As a result, the operation of semiconductor integrated circuit device 5e can be continued even when a failure occurs in the internal circuit.
　又、第１内部回路１１ａ及び第２内部回路１２ａの両方が故障した場合には、内部回路異常信号／ＥａがＬレベルに設定されることで、内部回路１０ａが使用不可であることを報知できる。 Further, when both the first internal circuit 11a and the second internal circuit 12a fail, the internal circuit abnormality signal /Ea is set to L level, thereby notifying that the internal circuit 10a cannot be used. .
　図１６に示された内部回路１０のテストタイミングは、半導体集積回路装置５ｆの電源立ち上げ時、及び、回路動作に影響のない時刻に定期的に設けることができる。 The test timing of the internal circuit 10 shown in FIG. 16 can be set periodically at the time of power-up of the semiconductor integrated circuit device 5f and at a time that does not affect the circuit operation.
　以上説明した様に、実施の形態６に係る半導体集積回路装置によれば、内部回路１０の故障の検知、及び、故障発生時の予備回路への切替を自動的に行うことができるので、実施の形態４で説明した効果に加えて、回路動作継続の信頼性を高めることができる。又、制御信号Ａａ，／Ａａ及び内部回路異常信号／Ｅａを、半導体集積回路装置５ｆの外部からモニタすることで、各内部回路１０の故障状態についても把握することができる。即ち、制御信号Ａａ，／Ａａ及び内部回路異常信号／Ｅａについては、端子６と同様に、半導体集積回路装置５ｆの外部からコンタクト可能な端子（図示せず）に出力することができる。 As described above, according to the semiconductor integrated circuit device according to the sixth embodiment, it is possible to automatically detect a failure in the internal circuit 10 and switch over to the backup circuit when a failure occurs. In addition to the effect described in Embodiment 4, it is possible to improve the reliability of circuit operation continuation. Further, by monitoring the control signals Aa, /Aa and the internal circuit abnormality signal /Ea from the outside of the semiconductor integrated circuit device 5f, the failure state of each internal circuit 10 can also be grasped. That is, the control signals Aa, /Aa and the internal circuit error signal /Ea can be output to terminals (not shown) that can be contacted from the outside of the semiconductor integrated circuit device 5f, similarly to the terminal 6. FIG.
　尚、図１５では、実施の形態４に係る半導体集積回路装置に対して、実施の形態６での異常対応構成を適用する例を説明したが、他の実施の形態１～３，５に対しても同様に、変形例１，２の適用に加えて、実施の形態６を更に組み合わせることが可能である。この際に、必要に応じて、記録装置８０のラッチ回路数、及び、制御論理回路９での論理演算内容を適宜変更することができる。 Note that FIG. 15 illustrates an example in which the abnormality handling configuration of the sixth embodiment is applied to the semiconductor integrated circuit device of the fourth embodiment. Similarly, in addition to the application of modifications 1 and 2, it is possible to further combine the sixth embodiment. At this time, the number of latch circuits of the recording device 80 and the content of the logic operation in the control logic circuit 9 can be changed as needed.
　一例として、実施の形態１～３において、実施の形態４と同様の電圧範囲（Ｖｔｌ＜Ｖｏｕｔ＜Ｖｔｕ）に係る判定結果を用いて正常及び≧を判断するためには、判定電圧Ｖｔｌ及びＶｔｕのそれぞれとの比較における判定信号Ｓｊｄを保持するために、各記録装置８０に４個のラッチ回路が必要となり、当該４個のラッチ回路のラッチデータを用いて、第１内部回路１１ａ及び第２内部回路１２ａの正常及び異常の組み合わせ（ケース１～ケース４）に対して、図１７と同様の制御信号Ａａ，／Ａａ及び内部回路異常信号／Ｅａが得られる様に、制御論理回路９での論理演算を変更することが必要である。 As an example, in Embodiments 1 to 3, in order to determine normality and ≧ using the same determination result related to the voltage range (Vtl<Vout<Vtu) as in Embodiment 4, the determination voltages Vtl and Vtu Four latch circuits are required in each recording device 80 in order to hold the determination signal Sjd for comparison with each other. The logic in the control logic circuit 9 is adjusted so that the control signals Aa and /Aa and the internal circuit abnormality signal /Ea similar to those in FIG. It is necessary to change the operation.
　実施の形態７．
　実施の形態７では、内部回路の測定ノードに係る２個の電圧差（電圧差）を測定電圧、即ち、判定の対象とする構成について説明する。 Embodiment 7.
In the seventh embodiment, a configuration will be described in which two voltage differences (voltage differences) relating to measurement nodes of an internal circuit are used as measurement voltages, ie, determination targets.
　図１８は、実施の形態７に係る半導体集積回路装置５ｇの構成を示すブロック図である。 FIG. 18 is a block diagram showing the configuration of a semiconductor integrated circuit device 5g according to the seventh embodiment.
　図１８に示される様に、半導体集積回路装置５ｇは、実施の形態４に係る半導体集積回路装置５ｂ（図１０）と比較して、内部回路１０ａから２個の第１電圧Ｖｏｕｔ１及び第２電圧Ｖｏｕｔ２が出力される点と、電圧電流変換回路２１ａに代えて、電圧電流変換回路２４ａが配置される点とで異なる。更に、「測定ノード」に相当する、内部回路１０ａの内部ノードＮＴａ（出力電圧Ｖｏｕｔ）に対して、上側ピーク検波器１３ａ及び下側ピーク検波器１４ａが設けられる。 As shown in FIG. 18, a semiconductor integrated circuit device 5g differs from the semiconductor integrated circuit device 5b according to the fourth embodiment (FIG. 10) in that two voltages Vout1 and Vout2 are applied from the internal circuit 10a. It differs in that Vout2 is output and in that a voltage-current conversion circuit 24a is arranged instead of the voltage-current conversion circuit 21a. Further, an upper peak detector 13a and a lower peak detector 14a are provided for the internal node NTa (output voltage Vout) of the internal circuit 10a, which corresponds to the "measurement node".
　上側ピーク検波器１３ａは、出力電圧Ｖｏｕｔの最大値（上側ピーク値）を抽出して、第１電圧Ｖｏｕｔ１として出力する。下側ピーク検波器１４ａは、出力電圧Ｖｏｕｔの最小値（下側ピーク値）を抽出して、第２電圧Ｖｏｕｔ２として出力する。例えば、内部ノードＮＴａに交流電圧が出力される場合には、Ｖｏｕｔ１－Ｖｏｕｔ２は、当該交流電圧のピーク・トゥ・ピーク値を示す。 The upper peak detector 13a extracts the maximum value (upper peak value) of the output voltage Vout and outputs it as the first voltage Vout1. The lower peak detector 14a extracts the minimum value (lower peak value) of the output voltage Vout and outputs it as the second voltage Vout2. For example, when an AC voltage is output to internal node NTa, Vout1-Vout2 represents the peak-to-peak value of the AC voltage.
　電圧電流変換回路２４ａには、第１電圧Ｖｏｕｔ１及び第２電圧Ｖｏｕｔ２が入力される。電圧電流変換回路２４ａは、第１電圧Ｖｏｕｔ１及び第２電圧Ｖｏｕｔ２の電圧差（Ｖｏｕｔ１－Ｖｏｕｔ２）を、異なる変換ゲインで、図１１での出力電流Ｉｏｕｔｘ，Ｉｏｕｔｙに変換する。 A first voltage Vout1 and a second voltage Vout2 are input to the voltage-current conversion circuit 24a. The voltage-current conversion circuit 24a converts the voltage difference (Vout1-Vout2) between the first voltage Vout1 and the second voltage Vout2 into output currents Ioutx and Iouty in FIG. 11 with different conversion gains.
　一方で、Ｎ個の内部回路１０で共有される、選択回路３２、電流比較器５０、基準電流源４０、及び、判定論理回路６０は、実施の形態４（図１０）と同様である。図１８及び図１９においても、内部回路１０ａに対応する構成が添字ａを付して代表的に示されるが、同様の構成が、各内部回路１０に対応して配置されている。 On the other hand, the selection circuit 32, the current comparator 50, the reference current source 40, and the decision logic circuit 60, which are shared by the N internal circuits 10, are the same as in the fourth embodiment (FIG. 10). In FIGS. 18 and 19 as well, the structure corresponding to internal circuit 10a is representatively shown with the suffix a.
　図１９には、実施の形態７に係る電圧電流変換回路、即ち、図１８の電圧電流変換回路２４ａの構成を説明する回路図が示される。 FIG. 19 shows a circuit diagram for explaining the configuration of the voltage-current conversion circuit according to Embodiment 7, that is, the voltage-current conversion circuit 24a of FIG.
　図１９を参照して、電圧電流変換回路２４ａは、ノードＮ１ａｘ及びＮ１ａｙを介して、選択回路３２（図１１）と接続される。電圧電流変換回路２４ａは、ＮＭＯＳトランジスタ２０３１ａ，２０３５ａ，２３０８ａと、ＰＭＯＳトランジスタ２３０４ａ，２３０７ａ，２３１０ａと、抵抗素子２３０６ａ，２３０９ａと、電流源２３０２ａ，２３０３ａとを有する。 Referring to FIG. 19, voltage-current conversion circuit 24a is connected to selection circuit 32 (FIG. 11) via nodes N1ax and N1ay. The voltage-current conversion circuit 24a has NMOS transistors 2031a, 2035a, 2308a, PMOS transistors 2304a, 2307a, 2310a, resistance elements 2306a, 2309a, and current sources 2302a, 2303a.
　ＮＭＯＳトランジスタ２３０１ａは、電源ラインＮＰ及びノードＮ３１の間に接続され、電流源２３０２ａは、ノードＮ３１及び接地ラインＮＬの間に接続される。ＮＭＯＳトランジスタ２３０１ａのゲートには、第２電圧Ｖｏｕｔ２が入力される。 The NMOS transistor 2301a is connected between the power supply line NP and the node N31, and the current source 2302a is connected between the node N31 and the ground line NL. A second voltage Vout2 is input to the gate of the NMOS transistor 2301a.
　電流源２３０３ａは、電源ラインＮＰ及びノードＮ３２の間に接続され、ＰＭＯＳトランジスタ２３０４ａは、ノードＮ３２及び接地ラインＮＬの間に接続される。ＰＭＯＳトランジスタ２３０４ａのゲートには、第１電圧Ｖｏｕｔ１が入力される。 A current source 2303a is connected between the power supply line NP and the node N32, and a PMOS transistor 2304a is connected between the node N32 and the ground line NL. A first voltage Vout1 is input to the gate of the PMOS transistor 2304a.
　ＮＭＯＳトランジスタ２３０５ａは、ノードＮ１ａｘ及びノードＮ３３の間に接続される。抵抗素子２３０６ａは、ノードＮ３３及びＰＭＯＳトランジスタ２３０７ａの間に接続され、ＰＭＯＳトランジスタ２３０７ａは、抵抗素子２３０６ａ及び接地ラインＮＬの間に接続される。抵抗素子２３０６ａは、電気抵抗値ＲＤＵを有する。 The NMOS transistor 2305a is connected between the node N1ax and the node N33. Resistive element 2306a is connected between node N33 and PMOS transistor 2307a, and PMOS transistor 2307a is connected between resistive element 2306a and ground line NL. Resistive element 2306a has an electrical resistance value RDU.
　ＮＭＯＳトランジスタ２３０８ａは、ノードＮ１ａｙ及びノードＮ３４の間に接続される。抵抗素子２３０９ａは、ノードＮ３４及びＰＭＯＳトランジスタ２３１０ａの間に接続され、ＰＭＯＳトランジスタ２３１０ａは、抵抗素子２３０９ａ及び接地ラインＮＬの間に接続される。抵抗素子２３０９ａは、電気抵抗値ＲＤＬを有する。 The NMOS transistor 2308a is connected between the node N1ay and the node N34. Resistive element 2309a is connected between node N34 and PMOS transistor 2310a, and PMOS transistor 2310a is connected between resistive element 2309a and ground line NL. Resistance element 2309a has an electrical resistance value RDL.
　ＮＭＯＳトランジスタ２３０５ａ及び２０３８ａのゲートは、ノードＮ３２と共通に接続される。ＰＭＯＳトランジスタ２３０７ａ及び２３１０ａのゲートは、ノードＮ３１と共通に接続される。 The gates of NMOS transistors 2305a and 2038a are commonly connected to node N32. The gates of PMOS transistors 2307a and 2310a are commonly connected to node N31.
　ノードＮ３２の電圧Ｖ３２は、ＰＭＯＳトランジスタ２３０４ａのゲートソース間電圧Ｖｇｓ１４を用いて、Ｖ３２＝Ｖｏｕｔ１＋Ｖｇｓ１４と示される。同様に、ノードＮ３１の電圧Ｖ３１は、ＮＭＯＳトランジスタ２３０１ａのゲートソース間電圧Ｖｇｓ１１を用いて、Ｖ３１＝Ｖｏｕｔ２－Ｖｇｓ１１と示される。 The voltage V32 at the node N32 is expressed as V32=Vout1+Vgs14 using the gate-to-source voltage Vgs14 of the PMOS transistor 2304a. Similarly, the voltage V31 at node N31 is expressed as V31=Vout2−Vgs11 using the gate-to-source voltage Vgs11 of NMOS transistor 2301a.
　従って、抵抗素子２３０６ａの両端に印加される電圧差は、ＮＭＯＳトランジスタ２３０５ａのゲートソース間電圧Ｖｇｓ１５と、ＮＭＯＳトランジスタ２３０７ａのゲートソース間電圧Ｖｇｓ１７とを更に用いると、（Ｖ３２－Ｖｇｓ１５）－（Ｖ３１＋Ｖｇｓ１７）で示される。この結果、出力電流Ｉｏｕｔｘは、下記の式（１３）で示される。 Therefore, using the gate-source voltage Vgs15 of the NMOS transistor 2305a and the gate-source voltage Vgs17 of the NMOS transistor 2307a, the voltage difference applied across the resistance element 2306a is (V32-Vgs15)-(V31+Vgs17). is indicated by As a result, the output current Ioutx is given by the following equation (13).
　Ｉｏｕｔｘ＝（（Ｖｏｕｔ１＋Ｖｇｓ１４－Ｖｇｓ１５）－（Ｖｏｕｔ２－Ｖｇｓ１１＋Ｖｇｓ１７））／ＲＤＵ
　＝（Ｖｏｕｔ１－Ｖｏｕｔ２＋Ｖｇｓ１４－Ｖｇｓ１５＋Ｖｇｓ１１－Ｖｇｓ１７）／ＲＤＵ　　…（１３）
　同様に、抵抗素子２３０９ａの両端に印加される電圧差は、ＮＭＯＳトランジスタ２３０８ａのゲートソース間電圧Ｖｇｓ１８と、ＮＭＯＳトランジスタ２３１０ａのゲートソース間電圧Ｖｇｓ２０とを更に用いると、（Ｖ３２－Ｖｇｓ１８）－（Ｖ３１＋Ｖｇｓ２０）で示される。この結果、出力電流Ｉｏｕｔｙは、下記の式（１４）で示される。 Ioutx=((Vout1+Vgs14-Vgs15)-(Vout2-Vgs11+Vgs17))/RDU
= (Vout1-Vout2+Vgs14-Vgs15+Vgs11-Vgs17)/RDU (13)
Similarly, the voltage difference applied across the resistance element 2309a is (V32-Vgs18)-(V31+Vgs20) using the gate-source voltage Vgs18 of the NMOS transistor 2308a and the gate-source voltage Vgs20 of the NMOS transistor 2310a. ). As a result, the output current Iouty is given by the following equation (14).
　Ｉｏｕｔｙ＝（（Ｖｏｕｔ１＋Ｖｇｓ１４－Ｖｇｓ１８）－（Ｖｏｕｔ２－Ｖｇｓ１１＋Ｖｇｓ２０））／ＲＤＬ
　＝（Ｖｏｕｔ１－Ｖｏｕｔ２＋Ｖｇｓ１４－Ｖｇｓ１８＋Ｖｇｓ１１－Ｖｇｓ２０）／ＲＤＬ　　…（１４）
　この様に、出力電流Ｉｏｕｔｘ及びＩｏｕｔｙは、測定電圧（Ｖｏｕｔ１－Ｖｏｕｔ２）を異なる変換ゲインによって電圧電流変換して得られる。 Iouty=((Vout1+Vgs14-Vgs18)-(Vout2-Vgs11+Vgs20))/RDL
= (Vout1-Vout2+Vgs14-Vgs18+Vgs11-Vgs20)/RDL (14)
Thus, the output currents Ioutx and Iouty are obtained by voltage-to-current conversion of the measured voltage (Vout1-Vout2) with different conversion gains.
　測定電圧Ｖｏｕｔ＝Ｖｏｕｔ１－Ｖｏｕｔ２の正常範囲の下限値及び上限値に相当する判定電圧Ｖｄｕ及びＶｄｌを設定すると、当該判定電圧Ｖｄｕ及びｈＶｄｌの各々と、電圧差（Ｖｏｕｔ１－Ｖｏｕｔ２）との比較により、電圧差（Ｖｏｕｔ１－Ｖｏｕｔ２）が正常範囲に含まれているか否かを判定することができる。 When the determination voltages Vdu and Vdl corresponding to the lower and upper limits of the normal range of the measured voltage Vout=Vout1-Vout2 are set, by comparing each of the determination voltages Vdu and hVdl with the voltage difference (Vout1-Vout2), It can be determined whether the voltage difference (Vout1-Vout2) is within the normal range.
　実施の形態１と同様に、Ｖｏｕｔ＝Ｖｏｕｔ１－Ｖｏｕｔ２＝Ｖｄｕのときに、Ｉｏｕｔｘ＝Ｉｒｅｆとするための、電気抵抗値ＲＤＵは、基準電流Ｉｒｅｆを決める電気抵抗値ＲＳ（基準電流源４０）を用いて、下記の式（１５）によって示される。 As in the first embodiment, the electrical resistance value RS (reference current source 40) that determines the reference current Iref is used as the electrical resistance value RDU for setting Ioutx=Iref when Vout=Vout1−Vout2=Vdu. is represented by the following equation (15).
　ＲＤＵ＝（Ｖｄｕ＋Ｖｇｓ１４－Ｖｇｓ１５＋Ｖｇｓ１１－Ｖｇｓ１７）／（Ｖｒｅｆ－Ｖｇｓ４）・ＲＰ　　…（１５）
　同様に、Ｖｏｕｔ＝Ｖｏｕｔ１－Ｖｏｕｔ２＝Ｖｄｌのときに、Ｉｏｕｔｙ＝Ｉｒｅｆとするための、電気抵抗値ＲＤＬは、電気抵抗値ＲＳ（基準電流源４０）を用いて、下記の式（１６）によって示される。 RDU=(Vdu+Vgs14−Vgs15+Vgs11−Vgs17)/(Vref−Vgs4)·RP (15)
Similarly, when Vout=Vout1−Vout2=Vdl, the electrical resistance value RDL for Iouty=Iref is expressed by the following equation (16) using the electrical resistance value RS (reference current source 40). be
　ＲＤＬ＝（Ｖｄｌ＋Ｖｇｓ１４－Ｖｇｓ１８＋Ｖｇｓ１１－Ｖｇｓ２０）／（Ｖｒｅｆ－Ｖｇｓ４）・ＲＰ　　…（１６）
　式（１５），（１６）に従って、抵抗素子２３０６ａの電気抵抗値ＲＤＵ、及び、抵抗素子２３０９ａの電気抵抗値ＲＤＬを定めることにより、固定された基準電流Ｉｒｅｆを用いて、電圧差（Ｖｏｕｔ１－Ｖｏｕｔ２）を測定電圧Ｖｏｕｔとして、判定電圧Ｖｄｕ及びＶｄｌの各々と比較することができる。この結果、内部回路の測定ノードに係る２つ電圧の電圧差が、判定電圧Ｖｄｕ，Ｖｄｌによって定められる正常範囲に含まれるか否かを判定することができる。 RDL=(Vdl+Vgs14−Vgs18+Vgs11−Vgs20)/(Vref−Vgs4)·RP (16)
By determining the electrical resistance value RDU of the resistor element 2306a and the electrical resistance value RDL of the resistor element 2309a according to equations (15) and (16), the voltage difference (Vout1-Vout2 ) can be compared with each of the determination voltages Vdu and Vdl as the measurement voltage Vout. As a result, it can be determined whether or not the voltage difference between the two voltages associated with the measurement nodes of the internal circuit is within the normal range determined by the determination voltages Vdu and Vdl.
　尚、実施の形態１及び３と同様に、単一のノードＮ１ａが、選択回路３０（図２又は図９）を介して、電流比較器５０と接続される構成においても、第１電圧Ｖｏｕｔ１及び第２電圧Ｖｏｕｔ２の電圧差を測定電圧Ｖｏｕｔとして、単一の判定電圧Ｖｄｔとを比較することが可能である。この場合には、図１９の電圧電流変換回路２４ａにおいて、ＮＭＯＳトランジスタ２３０８ａ、抵抗素子２３０９ａ、及び、ＰＭＯＳトランジスタ２３１０ａの配置を省略して、ＮＭＯＳトランジスタ２３０５ａを、ノードＮ１ａ及びノードＮ３３の間に接続することで、上記の電圧比較が実行できる。その際の抵抗素子２３０６ａの電気抵抗値は、式（１５）において、判定電圧Ｖｔｕを判定電圧Ｖｄｔに置換することで求めることができる。 As in the first and third embodiments, even in the configuration in which the single node N1a is connected to the current comparator 50 via the selection circuit 30 (FIG. 2 or FIG. 9), the first voltage Vout1 and It is possible to compare the voltage difference of the second voltage Vout2 as the measurement voltage Vout with the single determination voltage Vdt. In this case, the NMOS transistor 2308a, the resistance element 2309a, and the PMOS transistor 2310a are omitted from the voltage-current conversion circuit 24a of FIG. 19, and the NMOS transistor 2305a is connected between the node N1a and the node N33. Thus, the above voltage comparison can be performed. The electrical resistance value of the resistive element 2306a at that time can be obtained by replacing the determination voltage Vtu with the determination voltage Vdt in the equation (15).
　又、内部回路１０の測定ノードに係る第１電圧Ｖｏｕｔ１及び第２電圧Ｖｏｕｔ２について、図１８の例では、同一ノードの異なるタイミングでの２つの電圧としたが、内部回路１０の異なる２つのノードの電圧を第１電圧Ｖｏｕｔ１及び第２電圧Ｖｏｕｔ２として、２つの内部ノード間の電圧差を測定電圧Ｖｏｕｔとすることも可能である。 In the example of FIG. 18, the first voltage Vout1 and the second voltage Vout2 related to the measurement node of the internal circuit 10 are two voltages at different timings of the same node. It is also possible to take the voltages as the first voltage Vout1 and the second voltage Vout2 and the voltage difference between the two internal nodes as the measured voltage Vout.
　実施の形態７の半導体集積回路装置では、ノードＮ１ａｘ及びＮ１ａｙ（又は、ノードＮ１ａ）の後段の回路は、実施の形態１～６のいずれかと同様とすることが可能である。これにより、内部回路１０に係る２つの電圧の差（電圧差）について、実施の形態１～６と同様の判定、或いは、当該判定結果に基づく異常対応構成を行うことができる。 In the semiconductor integrated circuit device of the seventh embodiment, the circuits subsequent to the nodes N1ax and N1ay (or the node N1a) can be the same as those of any one of the first to sixth embodiments. As a result, the difference between the two voltages (voltage difference) associated with the internal circuit 10 can be determined in the same manner as in the first to sixth embodiments, or an abnormality handling configuration based on the determination result can be performed.
　（変形例）
　図１８及び図１９では、第１電圧Ｖｏｕｔ１及び第２電圧Ｖｏｕｔ２が、同一ノードの上限ピーク電圧及び下限ピーク電圧である例を説明したので、判定電圧Ｖｔｕ（上限値側）及び判定電圧（下限値側）の両方が正電圧であることを想定した電圧電流変換回路２４ａの構成例を説明した。図２０では、変形例として、判定電圧Ｖｔｕ（上限値側）が正電圧である一方で、判定電圧（下限値側）が負電圧である場合に対応するための電圧電流変換回路２５ａの構成例を、図２０を用いて説明する。 (Modification)
18 and 19, the first voltage Vout1 and the second voltage Vout2 are the upper limit peak voltage and the lower limit peak voltage of the same node. A configuration example of the voltage-to-current conversion circuit 24a has been described on the assumption that both of the voltages on both sides are positive voltages. In FIG. 20, as a modified example, the configuration example of the voltage-current conversion circuit 25a for coping with the case where the determination voltage Vtu (on the upper limit side) is a positive voltage and the determination voltage (on the lower limit side) is a negative voltage. will be described with reference to FIG.
　図２０に示される様に、電圧電流変換回路２５ａは、図１９に示された、電圧電流変換回路２４ａと比較して、ＰＭＯＳトランジスタ２３１２ａ、ＮＭＯＳトランジスタ２３１３ａ、及び、電流源２３１１ａ，２３１４ａを更に有する点と、ＮＭＯＳトランジスタ２３０８ａ及びＰＭＯＳトランジスタ２３１０ａのゲートの接続先が変更される点とで異なる。 As shown in FIG. 20, the voltage-to-current conversion circuit 25a further includes a PMOS transistor 2312a, an NMOS transistor 2313a, and current sources 2311a and 2314a compared to the voltage-to-current conversion circuit 24a shown in FIG. and that the connection destinations of the gates of the NMOS transistor 2308a and the PMOS transistor 2310a are changed.
　電流源２３１１ａは、電源ラインＮＰ及びノードＮ３５の間に接続され、ＰＭＯＳトランジスタ２３１２ａは、ノードＮ３５及び接地ラインＮＬの間に接続される。ＰＭＯＳトランジスタ２３１２ａのゲートには、ＮＭＯＳトランジスタ２３０１ａのゲートと共通に、第２電圧Ｖｏｕｔ２が入力される。 The current source 2311a is connected between the power supply line NP and the node N35, and the PMOS transistor 2312a is connected between the node N35 and the ground line NL. A second voltage Vout2 is input to the gate of the PMOS transistor 2312a in common with the gate of the NMOS transistor 2301a.
　ＮＭＯＳ２３１３ａは、電源ラインＮＰ及びノードＮ３６の間に接続され、電流源２３１４ａは、ノードＮ３６及び接地ラインＮＬの間に接続される。ＮＭＯＳトランジスタ２３１３ａのゲートには、ＰＭＯＳトランジスタ２３０４ａのゲートと共通に、第１電圧Ｖｏｕｔ１が入力される。 The NMOS 2313a is connected between the power supply line NP and the node N36, and the current source 2314a is connected between the node N36 and the ground line NL. A first voltage Vout1 is input to the gate of the NMOS transistor 2313a in common with the gate of the PMOS transistor 2304a.
　ＮＭＯＳトランジスタ２３０８のゲートは、第２電圧Ｖｏｕｔ２に従う電圧が発生するノードＮ３５と接続され、ＰＭＯＳトランジスタ２３１０ａのゲートは、第１電圧Ｖｏｕｔ１に従う電圧が発生するノードＮ３６と接続される。従って、抵抗素子２３０９ａの両端には、電圧差（Ｖｏｕｔ２－Ｖｏｕｔ１）に従う電圧が印加される。この結果、出力電流Ｉｏｕｔｙは、電圧差（Ｖｏｕｔ２－Ｖｏｕｔ１）を電気抵抗値ＲＤＬに従う変換ゲインによって変換した電流となる。 The gate of the NMOS transistor 2308 is connected to the node N35 generating a voltage according to the second voltage Vout2, and the gate of the PMOS transistor 2310a is connected to the node N36 generating a voltage according to the first voltage Vout1. Therefore, a voltage according to the voltage difference (Vout2-Vout1) is applied across the resistance element 2309a. As a result, the output current Iouty becomes a current obtained by converting the voltage difference (Vout2-Vout1) by the conversion gain according to the electrical resistance value RDL.
　即ち、図２０の電圧電流変換回路２５ａでは、電圧電流変換回路２４ａに対して、出力電流Ｉｏｕｔｙの変換ゲインの極性（正／負）が反転される。従って、全体としては、電圧電流変換回路２４ａを用いる場合に対して、判定電圧Ｖｄｌの極性（正／負）を反転して、電圧差（Ｖｏｕｔ１－Ｖｏｕｔ２）と比較できることが理解される。 That is, in the voltage-current conversion circuit 25a of FIG. 20, the polarity (positive/negative) of the conversion gain of the output current Iouty is inverted with respect to the voltage-current conversion circuit 24a. Therefore, as a whole, it can be understood that the polarity (positive/negative) of the determination voltage Vdl can be reversed and compared with the voltage difference (Vout1-Vout2) as compared with the case of using the voltage-current conversion circuit 24a.
　この様に、図２０に示された電圧電流変換回路２５ａを用いることで、電圧差（Ｖｏｕｔ１－Ｖｏｕｔ２）の正常範囲の下限値が負電圧であっても、実施の形態１～６と同様に、第１電圧Ｖｏｕｔ１及び第２電圧Ｖｏｕｔ２の電圧差を測定電圧Ｖｏｕｔとして、判定電圧と比較することができる。 In this way, by using the voltage-current conversion circuit 25a shown in FIG. 20, even if the lower limit of the normal range of the voltage difference (Vout1-Vout2) is a negative voltage, the same as in the first to sixth embodiments , the voltage difference between the first voltage Vout1 and the second voltage Vout2 can be compared with the determination voltage as the measurement voltage Vout.
　本開示には、様々な例示的な実施の形態及び実施例が記載されているが、１つ、または複数の実施の形態に記載された様々な特徴、態様、及び機能は特定の実施の形態の適用に限られるのではなく、単独で、または様々な組合せで実施の形態に適用可能である。 While this disclosure describes various exemplary embodiments and examples, various features, aspects, and functions described in one or more embodiments may not be found in particular embodiments. can be applied to the embodiments singly or in various combinations.
　従って、例示されていない無数の変形例が、本開示での技術の範囲内において想定される。例えば、少なくとも１つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも１つの構成要素を抽出し、他の実施の形態の構成要素と組合せる場合が含まれるものとする。 Therefore, countless modifications not illustrated are envisioned within the technical scope of the present disclosure. For example, when at least one component is modified, added or omitted, and at least one component is extracted and combined with the components of other embodiments. .
　又、実施の形態２以降では、測定電圧Ｖｏｕｔを変換ゲインが異なる２個の出力電流に変換することで２個の判定電圧と比較する構成例を説明したが、変換ゲインが異なる３以上の出力電流を基準電流と比較することで、測定電圧Ｖｏｕｔを３個以上の判定電圧と比較する構成とすることも、原理上は可能である。例えば、各電圧電流変換回路２１，２２において、図７等での並列配置される電圧電流変換ユニットの個数、又は、図９での抵抗素子及びスイッチ（ゲイン切替機構）の個数を増加することで、この様な構成を実現することができる。 In the second and subsequent embodiments, a configuration example in which the measured voltage Vout is converted into two output currents with different conversion gains and compared with two determination voltages has been described. In principle, it is also possible to compare the measured voltage Vout with three or more determination voltages by comparing the current with the reference current. For example, in each of the voltage-current conversion circuits 21 and 22, by increasing the number of voltage-current conversion units arranged in parallel in FIG. , such a configuration can be realized.
　又、上記実施の形態では、各カレントミラーの電流比を１：１としたが、それ以外の電流比とすることも可能である。この場合には、電圧電流変換回路２０等の出力電流Ｉｏｕｔ，Ｉｏｕｔｘ，Ｉｏｕｔｙに対する、電流比較器５０トランジスタ，５１内（ノードＮ３，Ｎ３ｘ，Ｎ３ｙ）に生じる出力電流Ｉｏｕｔの電流比Ａ、及び、基準電流源４０での基準電流Ｉｒｅｆに対する、電流比較器５０～５２，５１内（ノードＮ４）に生じる基準電流Ｉｒｅｆの電流比Ｂを用いて、式（４）等の電気抵抗値ＲＯについて、（Ａ／Ｂ）倍することが必要である。 Also, in the above embodiment, the current ratio of each current mirror is 1:1, but other current ratios are also possible. In this case, the current ratio A of the output current Iout generated in the current comparator 50 transistors, 51 (nodes N3, N3x, N3y) to the output currents Iout, Ioutx, Iouty of the voltage-current conversion circuit 20, etc., and the reference (A /B) Multiplication is required.
　この場合には、更に、式（４）等中のＶｇｓ２及びＶｇｓ４を均衡させるために、例えば、トランジスタサイズの調整によって、図２中のＮＭＯＳトランジスタ２０１ａ及びＮＭＯＳトランジスタ４０３の間で、電流及びトランジスタサイズの比を揃えることが好ましい。一例として（Ａ／Ｂ）＝０．５である場合には、電気抵抗値ＲＯが１／２倍とされて、ＮＭＯＳトランジスタ２０１ａを流れる電流が２倍になるので、ＮＭＯＳトランジスタ２０１ａのトランジスタサイズは、ＮＭＯＳトランジスタ４０３の２倍とすることが好ましい。例えば、ＮＭＯＳトランジスタ４０３と同等のトランジスタサイズを有するＮＭＯＳトランジスタを２個並列接続してＮＭＯＳトランジスタ２０１ａを構成することで、ＮＭＯＳトランジスタ２０１ａ及びＮＭＯＳトランジスタ４０３の間で、電流及びトランジスタサイズの比を揃えることができる。 In this case, furthermore, to balance Vgs2 and Vgs4 in equation (4) etc., the current and transistor size between NMOS transistor 201a and NMOS transistor 403 in FIG. It is preferable to align the ratio of As an example, when (A/B)=0.5, the electric resistance value RO is halved and the current flowing through the NMOS transistor 201a is doubled, so the transistor size of the NMOS transistor 201a is , is preferably twice that of the NMOS transistor 403 . For example, two NMOS transistors having a transistor size equivalent to that of the NMOS transistor 403 are connected in parallel to configure the NMOS transistor 201a, so that the ratio of current and transistor size can be made uniform between the NMOS transistor 201a and the NMOS transistor 403. can be done.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本開示の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。 The embodiments disclosed this time should be considered illustrative in all respects and not restrictive. The scope of the present disclosure is indicated by the scope of the claims rather than the above description, and is intended to include all changes within the meaning and scope of equivalents of the scope of the claims.
　５ａ～５ｇ　半導体集積回路装置、９ａ～９ｄ　制御論理回路、１０ａ～１０ｄ　内部回路、１１ａ～１１ｄ　第１内部回路、１２ａ～１２ｄ　第２内部回路、１３ａ　上側ピーク検波器、１４ａ　下側ピーク検波器、１５ａ～１５ｄ，２１，３０，３１，３２　選択回路、２０ａ～２０ｄ，２０ｐａ，２１ａ～２１ｄ，２２ａ～２２ｄ，２３ａ～２３ｄ，２４ａ，２５ａ　電圧電流変換回路、４０，４０ｐ　基準電流源、５０，５０ｐ，５１，５２　電流比較器、６０　判定論理回路、７０　判定結果選択回路、８０ａ，８０ｂ，８０ｄ　記録装置、２０７ａ　イネーブルスイッチ、２０８ａ　トランジスタスイッチ、２３０ａ，４０７　オペアンプバッファ、８０１ａ　第１ラッチ回路、８０２ａ　第２ラッチ回路、Ａａ，／Ａａ，Ｓｃｈｇ　制御信号、ＥＮａ～ＥＮｄ　イネーブル信号、ＧＮＤ　接地電圧、Ｉｏｌ，Ｉｏｕ，Ｉｏｕｔ，Ｉｏｕｔｘ，Ｉｏｕｔｙ　出力電流、Ｉｒｅｆ　基準電流、ＮＬ　接地ライン、ＮＰ　電源ライン、Ｓ１１ａ，Ｓ１２ａ　ラッチデータ、Ｓｊｄ　判定信号、ＶＤＤ　電源電圧、Ｖｏｕｔ　測定電圧、Ｖｏｕｔ１　第１電圧、Ｖｏｕｔ２　第２電圧、Ｖｒｅｆ　基準電圧。 5a to 5g semiconductor integrated circuit device, 9a to 9d control logic circuit, 10a to 10d internal circuit, 11a to 11d first internal circuit, 12a to 12d second internal circuit, 13a upper peak detector, 14a lower peak detector, 15a to 15d, 21, 30, 31, 32 selection circuits, 20a to 20d, 20pa, 21a to 21d, 22a to 22d, 23a to 23d, 24a, 25a voltage-current conversion circuits, 40, 40p reference current sources, 50, 50p , 51, 52 current comparator, 60 decision logic circuit, 70 decision result selection circuit, 80a, 80b, 80d recording device, 207a enable switch, 208a transistor switch, 230a, 407 operational amplifier buffer, 801a first latch circuit, 802a second Latch circuit, Aa, /Aa, Schg control signal, ENa to ENd enable signal, GND ground voltage, Iol, Iou, Iout, Ioutx, Iouty output current, Iref reference current, NL ground line, NP power supply line, S11a, S12a latch Data, Sjd decision signal, VDD power supply voltage, Vout measurement voltage, Vout1 first voltage, Vout2 second voltage, Vref reference voltage.

Claims (14)

  1. 　複数の電圧電流変換回路を備え、
    　前記複数の電圧電流変換回路の各々は、半導体集積回路装置の内部の少なくとも１つの測定ノードの電圧に従う測定電圧を、前記測定電圧と比較されるべき判定電圧が反映された第１変換ゲインに従って電圧電流変換して少なくとも１つの出力電流を生成する様に構成され、
    　予め定められた基準電流を出力する基準電流源と、
    　前記複数の電圧電流変換回路のうちの選択された電圧電流変換回路から入力された前記少なくとも１つの出力電流のそれぞれと前記基準電流との比較結果に従う少なくとも１つの判定信号を出力する電流比較器とを更に備える、半導体集積回路装置。     Equipped with multiple voltage-current conversion circuits,
    Each of the plurality of voltage-current conversion circuits converts a measured voltage according to the voltage of at least one measurement node inside the semiconductor integrated circuit device to a voltage according to a first conversion gain reflecting a determination voltage to be compared with the measured voltage. configured to current convert to produce at least one output current;
    a reference current source that outputs a predetermined reference current;
    a current comparator for outputting at least one determination signal according to a comparison result between each of the at least one output current input from a voltage-current conversion circuit selected from the plurality of voltage-current conversion circuits and the reference current; A semiconductor integrated circuit device further comprising:
  2. 　各前記電圧電流変換回路は、前記第１変換ゲインが異なる複数の電圧電流変換ユニットを有し、
    　前記複数の電圧電流変換ユニットは、前記測定電圧をそれぞれの前記第１変換ゲインに従って変換して複数の前記出力電流を生成し、
    　前記選択された電圧電流変換回路の前記複数の電圧電流変換ユニットによって生成された前記複数の出力電流は、１つずつ順に前記電流比較器に入力され、
    　前記電流比較器は、前記選択された電圧電流変換回路から入力された前記複数の出力電流のうちの１つと、前記基準電流との比較結果に従う前記判定信号を出力するように構成される、請求項１記載の半導体集積回路装置。     each of the voltage-to-current conversion circuits has a plurality of voltage-to-current conversion units with different first conversion gains;
    the plurality of voltage-to-current conversion units convert the measured voltages according to respective first conversion gains to generate a plurality of the output currents;
    the plurality of output currents generated by the plurality of voltage-to-current conversion units of the selected voltage-to-current conversion circuit are sequentially input to the current comparator one by one;
    wherein the current comparator is configured to output the determination signal according to a comparison result between one of the plurality of output currents input from the selected voltage-current conversion circuit and the reference current; 2. A semiconductor integrated circuit device according to item 1.
  3. 　各前記電圧電流変換回路は、
    　前記第１変換ゲインを複数に切替えるためのゲイン切替機構を有し、
    　前記選択された電圧電流変換回路は、前記ゲイン切替機構によって切替えられた前記複数の第１変換ゲインにそれぞれ従う複数の前記出力電流を、１つずつ順に出力し、
    　前記電流比較器は、前記選択された電圧電流変換回路から入力された前記複数の出力電流のうちの１つと、前記基準電流との比較結果に従う前記判定信号を出力するように構成される、請求項１記載の半導体集積回路装置。     Each voltage-to-current conversion circuit includes:
    Having a gain switching mechanism for switching the first conversion gain to a plurality,
    The selected voltage-current conversion circuit sequentially outputs the plurality of output currents respectively according to the plurality of first conversion gains switched by the gain switching mechanism,
    wherein the current comparator is configured to output the determination signal according to a comparison result between one of the plurality of output currents input from the selected voltage-current conversion circuit and the reference current; 2. A semiconductor integrated circuit device according to item 1.
  4. 　各前記電圧電流変換回路は、前記第１変換ゲインがそれぞれ異なる複数の電圧電流変換ユニットを有し、
    　前記複数の電圧電流変換ユニットは、前記測定電圧をそれぞれの前記第１変換ゲインに従って変換して複数の前記出力電流を生成し、
    　前記複数の電圧電流変換ユニットによって生成された前記複数の出力電流は、並列に前記電流比較器に入力され、
    　前記電流比較器は、前記複数の電圧電流変換ユニットから入力された前記複数の出力電流のそれぞれと前記基準電流との比較結果に従う複数の前記判定信号を出力するように構成される、請求項１記載の半導体集積回路装置。     each of the voltage-to-current conversion circuits has a plurality of voltage-to-current conversion units with different first conversion gains;
    the plurality of voltage-to-current conversion units convert the measured voltages according to respective first conversion gains to generate a plurality of the output currents;
    the plurality of output currents generated by the plurality of voltage-to-current conversion units are input in parallel to the current comparator;
    2. The current comparator is configured to output a plurality of the determination signals according to comparison results between each of the plurality of output currents input from the plurality of voltage-to-current conversion units and the reference current. A semiconductor integrated circuit device as described.
  5. 　前記複数の判定信号の論理演算結果を示す信号を生成する判定論理回路を更に備える、請求項４記載の半導体集積回路装置。 5. The semiconductor integrated circuit device according to claim 4, further comprising a decision logic circuit for generating a signal indicating a logical operation result of said plurality of decision signals.
  6. 　前記電圧電流変換回路は、１つの前記測定ノードの電圧を前記測定電圧として、前記少なくとも１つの出力電流を生成する、請求項１～５のいずれか１項に記載の半導体集積回路装置。 6. The semiconductor integrated circuit device according to claim 1, wherein said voltage-to-current conversion circuit generates said at least one output current using the voltage of one said measurement node as said measurement voltage.
  7. 　前記電圧電流変換回路は、１つの前記測定ノードの異なるタイミングでの第１電圧及び第２電圧の電圧差を前記測定電圧として、前記少なくとも１つの出力電流を生成する、請求項１～５のいずれか１項に記載の半導体集積回路装置。 6. The voltage-current conversion circuit according to any one of claims 1 to 5, wherein the voltage difference between the first voltage and the second voltage at different timings of one of the measurement nodes is used as the measurement voltage to generate the at least one output current. 1. A semiconductor integrated circuit device according to claim 1.
  8. 　前記第１電圧及び前記第２電圧は、前記１つの測定ノードの電圧の最大ピーク値及び最小ピーク値である、請求項７記載の半導体集積回路装置。 8. The semiconductor integrated circuit device according to claim 7, wherein said first voltage and said second voltage are the maximum peak value and minimum peak value of the voltage of said one measurement node.
  9. 　前記電圧電流変換回路は、２つの前記測定ノードの電圧差を前記測定電圧として、前記少なくとも１つの出力電流を生成する、請求項１～５のいずれか１項に記載の半導体集積回路装置。 6. The semiconductor integrated circuit device according to any one of claims 1 to 5, wherein said voltage-to-current conversion circuit generates said at least one output current using a voltage difference between said two measurement nodes as said measurement voltage.
  10. 　前記基準電流源は、予め定められた基準電圧を予め定められた第２変換ゲインに従って電圧電流変換することで前記基準電流を生成する様に構成され、
    　各前記電圧電流変換回路における前記第１変換ゲインは、前記判定電圧及び前記基準電圧の比、並びに、前記第２変換ゲインを用いて定められる、請求項１～９のいずれか１項に記載の半導体集積回路装置。     The reference current source is configured to generate the reference current by converting a predetermined reference voltage into voltage-to-current in accordance with a predetermined second conversion gain,
    10. The first conversion gain in each voltage-current conversion circuit according to claim 1, wherein the first conversion gain is determined using the ratio of the judgment voltage and the reference voltage, and the second conversion gain. Semiconductor integrated circuit device.
  11. 　前記第１変換ゲインは、前記測定電圧が前記判定電圧と同等であるときに、前記出力電流と前記基準電流とが同等となるように設定される、請求項１～９のいずれか１項に記載の半導体集積回路装置。 The first conversion gain according to any one of claims 1 to 9, wherein the output current is equal to the reference current when the measured voltage is equal to the judgment voltage. A semiconductor integrated circuit device as described.
  12. 　前記半導体集積回路装置は、
    　前記複数の電圧電流変換回路と前記電流比較器の間に接続された複数のスイッチを有する選択回路を更に備え、
    　前記選択回路において、前記複数のスイッチのうちの、前記選択された電圧電流変換回路と前記電流比較器の間に接続された一部のスイッチは選択的にオンされる、請求項１～１１のいずれか１項に記載の半導体集積回路装置。     The semiconductor integrated circuit device is
    further comprising a selection circuit having a plurality of switches connected between the plurality of voltage-to-current conversion circuits and the current comparator;
    12. The method of claim 1, wherein in said selection circuit, some of said plurality of switches connected between said selected voltage-to-current conversion circuit and said current comparator are selectively turned on. The semiconductor integrated circuit device according to any one of items 1 to 3.
  13. 　前記複数の電圧電流変換回路の各々は、前記少なくとも１つの出力電流の経路に介挿接続されたイネーブルスイッチを有し、
    　前記イネーブルスイッチは、前記選択された電圧電流変換回路においてオンされる、請求項１～１１のいずれか１項に記載の半導体集積回路装置。     each of the plurality of voltage-to-current conversion circuits has an enable switch interposed and connected to the path of the at least one output current;
    12. The semiconductor integrated circuit device according to claim 1, wherein said enable switch is turned on in said selected voltage-current conversion circuit.
  14. 　前記半導体集積回路装置は、
    　予め定められた機能を有する第１内部回路と、
    　前記第１内部回路と同一機能を有する第２内部回路と、
    　前記第１内部回路に係る前記測定電圧及び前記第２内部回路に係る前記測定電圧の一方を選択的に前記電圧電流変換回路に入力するための測定選択回路と、
    　前記測定選択回路によって前記第１内部回路に係る前記測定電圧が前記電圧電流変換回路に入力されているときに前記電流比較器から出力された前記判定信号に係る第１情報を記憶するための第１記憶回路と、
    　前記測定選択回路によって前記第２内部回路に係る前記測定電圧が前記電圧電流変換回路に入力されているときに前記電流比較器から出力された前記判定信号に係る第２情報を記憶するための第２記憶回路と、
    　前記第１記憶回路及び前記第２記憶回路に記憶された前記第１情報及び前記第２情報に基づき、前記第１内部回路に故障が生じているときは前記第２内部回路の出力を用いて前記半導体集積回路装置を動作させる一方で、前記第２内部回路に故障が生じているときは前記第１内部回路の出力を用いて前記半導体集積回路装置を動作させるための出力選択回路とを更に備える、請求項１～１３のいずれか１項に記載の半導体集積回路装置。     The semiconductor integrated circuit device is
    a first internal circuit having a predetermined function;
    a second internal circuit having the same function as the first internal circuit;
    a measurement selection circuit for selectively inputting one of the measured voltage related to the first internal circuit and the measured voltage related to the second internal circuit to the voltage-current conversion circuit;
    a first information for storing first information related to the determination signal output from the current comparator when the measured voltage related to the first internal circuit is input to the voltage-current conversion circuit by the measurement selection circuit; 1 memory circuit;
    a second information for storing second information related to the determination signal output from the current comparator when the measured voltage related to the second internal circuit is input to the voltage-current conversion circuit by the measurement selection circuit; 2 a memory circuit;
    Based on the first information and the second information stored in the first memory circuit and the second memory circuit, using the output of the second internal circuit when a failure occurs in the first internal circuit an output selection circuit for operating the semiconductor integrated circuit device while operating the semiconductor integrated circuit device using the output of the first internal circuit when a failure occurs in the second internal circuit; 14. The semiconductor integrated circuit device according to claim 1, comprising:
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