WO2022252986A1

WO2022252986A1 - Interrupt scheduling method, electronic device, and storage medium

Info

Publication number: WO2022252986A1
Application number: PCT/CN2022/093584
Authority: WO
Inventors: 王辉; 成坚
Original assignee: 华为技术有限公司
Priority date: 2021-06-02
Filing date: 2022-05-18
Publication date: 2022-12-08
Also published as: CN115437755A

Abstract

The present application relates to the field of operation systems, and in particular to an interrupt scheduling method, an electronic device, and a storage medium. The method comprises: obtaining a pre-configured first delay threshold, the first delay threshold being a maximum value of a scheduling delay caused by interrupt handling configured for a first processor core; obtaining a scheduling delay value of the first processor core, the scheduling delay value being used for indicating a current interrupt load of the first processor core; and when the scheduling delay value is greater than the first delay threshold, migrating and binding some of current interrupt requests of the first processor core to a second processor core. In embodiments of the present application, the first delay threshold is configured for the first processor core, such that when the scheduling delay value of the first processor core is greater than the first delay threshold, some of the current interrupt requests of the first processor core are migrated and bound to the second processor core. Therefore, a reasonable interrupt handling throughput can be simultaneously guaranteed on the basis of ensuring the scheduling delay.

Description

Interrupt scheduling method, electronic device and storage medium

This application claims the priority of the Chinese patent application with the application number 202110613606.2 and the application name "interrupt scheduling method, electronic equipment and storage medium" submitted to the China Patent Office on June 2, 2021, the entire contents of which are incorporated herein by reference Applying.

technical field

The present application relates to the field of operating systems, and in particular to an interrupt scheduling method, electronic equipment and storage media.

Background technique

In the field of telecommunications, more and more Linux operating systems are used to process high real-time services.

Please refer to FIG. 1 , which shows a schematic diagram of an architecture in the related art that uses a Linux operating system to process high real-time services. The architecture includes a hardware layer 120 , a kernel layer 140 and a user layer 160 . The user layer 160 can run at least one thread, and each thread is used for processing tasks. The task scheduling process and interrupt handling process of each thread are mainly implemented by the kernel layer 140 .

The current interrupt processing strategy mainly includes the following two possible implementation methods. One possible implementation method is interrupt balance processing, that is, sending interrupt requests (Interrupt Request, IRQ) to each processor (Central Processing Unit, CPU) relatively evenly. core, this method can guarantee the throughput of interrupt processing, but it cannot solve the problem of uncontrollable scheduling delay caused by interrupt processing; another possible implementation method is interrupt binding core processing, such as pre-binding the network card interrupt request to a certain On one processor core, the scheduling delay on other processor cores other than the bound processor core can be controlled, but in this way, the interrupt load on the bound processor core may be too large, and the The frequency of the entire cluster causes waste of power consumption. At present, a reasonable and effective interrupt scheduling method has not been provided, which can ensure a reasonable interrupt processing throughput on the basis of ensuring the scheduling delay.

Contents of the invention

In view of this, an embodiment of the present application proposes an interrupt scheduling method, electronic equipment, and a storage medium. In the embodiment of the present application, the maximum value of the scheduling delay caused by the interrupt processing configured for the first processor core is the first delay threshold, so that when the scheduling delay value of the first processor core is greater than the first delay threshold In this case, migrating and binding part of the current interrupt requests of the first processor core to the second processor core can ensure reasonable interrupt processing throughput while ensuring scheduling delay.

In a first aspect, an embodiment of the present application provides an interrupt scheduling method, the method comprising:

Acquiring a preconfigured first delay threshold, where the first delay threshold is the maximum value of scheduling delay caused by interrupt processing configured for the first processor core;

Acquire a scheduling delay value of the first processor core, where the scheduling delay value is used to indicate a current interrupt load of the first processor core;

When the scheduling delay value is greater than the first delay threshold, migrate and bind the current part of the interrupt request of the first processor core to the second processor core, and the second processor core is different from the on the first processor core.

In this implementation, in this embodiment of the present application, the maximum value of the scheduling delay caused by the interrupt processing configured for the first processor core is the first delay threshold, so that the scheduling delay value of the first processor core is greater than the first delay threshold. In the case of a delay threshold, some of the current interrupt requests of the first processor core are migrated and bound to the second processor core, which ensures that the scheduling delay caused by interrupt processing on the first processor core is controllable, avoiding The problem of excessive scheduling delay caused by interrupt processing in the related art ensures the real-time performance of the business processing process and improves the overall performance of the electronic equipment.

In a possible implementation manner, the scheduling delay value of the first processor core after the migration binding is less than or equal to the first delay threshold.

In this implementation, if the current scheduling delay value of the first processor core is greater than the first delay threshold, some current interrupt requests of the first processor core are migrated and bound to the second processor core, so that the migration bound After setting, the scheduling delay value of the first processor core is less than or equal to the first delay threshold, which reduces the scheduling delay on the first processor core and further ensures the real-time performance of the service processing process.

In another possible implementation manner, after the migration and binding, the absolute values of the differences between the scheduling delay values of other processor cores are all smaller than a preset first difference threshold, and the other processor cores are All processor cores except the first processor core.

In this implementation, the part of the interrupt requests moved out is reasonably evenly distributed on other processor core clusters, so that the absolute value of the difference between the scheduling delay values of other processor cores after migration and binding is less than the preset The first difference threshold, to ensure the concurrency of interrupt processing, and to avoid the excessive load of a single processor core to increase the frequency of the entire cluster, resulting in waste of power consumption.

In another possible implementation manner, the method is used in an electronic device including a user layer, a kernel layer, and a hardware layer, and the acquiring the preconfigured first delay threshold includes:

The user layer sends first configuration information to the kernel layer, where the first configuration information includes a processor core identifier of the first processor core and the first delay threshold;

The kernel layer receives the first configuration information sent by the user layer;

When the scheduling delay value is greater than the first delay threshold, migrating and binding the current part of the interrupt request of the first processor core to the second processor core includes:

When the scheduling delay value is greater than the first delay threshold, the kernel layer sends second configuration information to the interrupt controller of the hardware layer, and the second configuration information includes the first processing The interrupt number to be transferred out of the processor core and the processor core identification of the second processor core;

The interrupt controller migrates and binds at least one interrupt request corresponding to the interrupt number to the second processor core according to the second configuration information.

In this implementation, the kernel layer dynamically adjusts the interrupt binding according to the current scheduling delay value of the first processor core and the first delay threshold configured by the user layer. If the current scheduling delay value of the first processor core is greater than the first Once the delay threshold is reached, the second configuration information is sent to the interrupt controller at the hardware layer, so that the interrupt controller migrates and binds at least one interrupt request corresponding to the interrupt number to the second processor core according to the second configuration information, further ensuring The scheduling delay caused by interrupt processing on the first processor core is controllable, and the overall performance of the electronic device is improved.

In another possible implementation, the method further includes:

After receiving the interrupt request, the interrupt processing duration corresponding to the interrupt request is obtained, and the interrupt processing duration includes the total duration of hard interrupt processing and soft interrupt processing;

According to the interrupt processing duration of the interrupt request, a preset algorithm is used to determine the scheduling delay value corresponding to the interrupt request;

The scheduling delay value corresponding to the interrupt request is summed with the current scheduling delay value of the first processor core to obtain the updated scheduling delay value.

In this implementation, compared with the scheme in the related art that calculates the scheduling delay value overhead according to the processor core dimension, the embodiment of the present application tracks and calculates the load overhead of each interrupt request, so as to avoid the traditional calculation based on the number of interrupts The extensive algorithm of the load supports more accurate interrupt balancing processing, and the time overhead of soft interrupt processing triggered by hard interrupt processing is included in the corresponding interrupt processing time, making the scheduling delay value determined based on the interrupt processing time more accurate, so that In the follow-up, interrupt equalization processing can be performed more accurately.

In another possible implementation, the method further includes:

Obtaining a preconfigured second latency threshold, where the second latency threshold is the maximum value of scheduling latency caused by interrupt processing configured for a specified thread;

After the specified thread is woken up, the processor core that meets the preset core selection condition is determined as the target processor core, and the preset core selection condition includes that the current scheduling delay value of the processor core is less than or equal to the specified The second delay threshold;

Add the specified thread to the scheduling queue of the target processor core.

In this implementation, the task scheduling delay requirement and the scheduling delay value of the processor core are considered when selecting a task core, and only the current scheduling delay value of the processor core is less than or equal to the second delay threshold of the task scheduling delay requirement , it is possible to use the processor core as the target processor core to ensure that the key designated thread can be selected to the processor core with a low scheduling delay value and be scheduled in time.

In another possible implementation manner, the specified thread includes a frame drawing process and/or a process of an inter-process communication mechanism of the foreground application.

In this implementation mode, it supports the configuration of scheduling delay requirements for task granularity, separates foreground/background threads, and reduces the impact of background threads on foreground specified threads.

In a second aspect, an embodiment of the present application provides an electronic device, and the electronic device includes:

processor;

memory for storing processor-executable instructions;

Wherein, the processor is configured to implement the first aspect or the method provided in any possible implementation manner of the first aspect when executing the instruction.

In the third aspect, the embodiments of the present application provide a non-volatile computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above-mentioned first aspect or the first aspect can be realized A method provided by any of the possible implementations in .

In a fourth aspect, an interrupt scheduling device is provided, and the device includes at least one unit, and the at least one unit is configured to implement the method provided in the first aspect or any possible implementation manner of the first aspect.

In the fifth aspect, the embodiments of the present application provide a computer program product, including computer readable code, or a non-volatile computer readable storage medium bearing computer readable code, when the computer readable code is stored in an electronic When running in the device, the processor in the electronic device executes the method provided in the first aspect or any one possible implementation manner of the first aspect.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the application and, together with the specification, serve to explain the principles of the application.

FIG. 1 shows a schematic diagram of an architecture in the related art that uses a Linux operating system to process high real-time services.

Fig. 2 shows a schematic diagram of five scheduling classes in the Linux kernel in the related art.

FIG. 3 shows a schematic diagram of a scheduling queue of a processor core in the related art.

FIG. 4 shows a schematic diagram of an interrupt processing architecture of a Linux operating system in the related art.

Fig. 5a shows a schematic diagram of time-consuming interrupt processing of multiple processor cores in the case of adopting interrupt balancing processing.

Fig. 5b shows a schematic diagram of time-consuming interrupt processing of multiple processor cores in the case of using interrupt bundled core processing.

FIG. 6 shows a schematic diagram of an electronic device involved in an embodiment of the present application.

Fig. 7 shows a flowchart of an interrupt scheduling method provided by an exemplary embodiment of the present application.

Fig. 8 shows a flowchart of a process of counting scheduling delay values provided by an exemplary embodiment of the present application.

Fig. 9 shows a flowchart of a task selection process provided by an exemplary embodiment of the present application.

Fig. 10 shows a schematic diagram of an interface involved in an interrupt scheduling method provided by another exemplary embodiment of the present application.

Fig. 11 shows a flowchart of an interrupt scheduling method provided by another exemplary embodiment of the present application.

Fig. 12 shows a schematic diagram of a scheduling delay of a specified thread provided by an exemplary embodiment of the present application.

Fig. 13 shows a flowchart of an interrupt scheduling method provided by another exemplary embodiment of the present application.

Fig. 14 shows a block diagram of an interrupt scheduling device provided by an exemplary embodiment of the present application.

Detailed ways

Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures indicate functionally identical or similar elements. While various aspects of the embodiments are shown in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

In addition, in order to better illustrate the present application, numerous specific details are given in the following specific implementation manners. It will be understood by those skilled in the art that the present application may be practiced without certain of the specific details. In some instances, methods, means, components and circuits well known to those skilled in the art have not been described in detail in order to highlight the gist of the present application.

First, some nouns involved in the embodiments of this application are introduced.

1. Process: A process is an entity in the execution period of a program. In addition to executing code, it also includes information such as open files and pending signals.

2. Thread: A process can include multiple threads, and the address space is shared between threads

3. Task: The kernel (the core of the operating system) schedules the object, which can be a process or a thread. For example, the task_struct structure is used uniformly in the Linux kernel to describe processes and threads.

4. Scheduling queue: A processor core includes at least one scheduling queue. After a task wakes up, it will join the scheduling queue of a certain processor core and wait for scheduling. Optionally, the task will join the scheduling queue (Deadline Runqueue, dl_rq) of the deadline-oriented scheduler in the processor core, the scheduling queue of the real-time scheduler (Real Time Runqueue, rt_rq) and the scheduling queue of the completely fair scheduler in the processor core according to the scheduling policy. In a dispatch queue in the dispatch queue (Completely Fair Runqueue, cfs_rq).

Optionally, each processor core includes a process queue (Runqueue, rq) for managing dl_rq, rt_rq and cfs_rq in the processor core. Among them, all DL tasks need to add dl_rq to wait for scheduling before running, all RT tasks need to add rt_rq to wait for scheduling before running, and all CFS tasks need to add cfs_rq to wait for scheduling before running.

5. Scheduling delay: the time it takes for a task to wake up and join the scheduling queue until it actually starts executing. The scheduling delay in the real-time system can reach the lowest us level.

6. Context switching: switching between operating states of the kernel, and/or, the kernel switches tasks on the processor core. For example, the Linux kernel includes the following running states: user state, kernel state (running in process context), kernel state (running in interrupt context), switching between these running states, and switching between tasks, all It's called a context switch. Context switching has certain overhead due to the need to save and restore state information such as registers and page tables.

7. Preemption: After a high-priority task wakes up, if the currently executing task has a lower priority, immediately switch the currently executing task to a high-priority task. In this way, high-priority tasks can be executed as soon as possible with low scheduling delay.

8. Off Preemption: Turn off the above preemption ability. This is because the kernel needs to avoid concurrency competition introduced by preemption when processing some key resources.

9. Throughput: the amount of data processed by the system per unit time. It reflects the data processing capability of the system. It is usually negatively correlated with the number of context switches, that is, the more the number of context switches, the lower the throughput; on the contrary, the smaller the number of context switches, the higher the throughput.

10. Interruption: During the execution of the electronic device, any unusual or unexpected emergency processing event occurs in the system, causing the processor to temporarily interrupt the currently executing program and turn to execute the corresponding event processing program. Return to the original interrupted process to continue execution or schedule a new process to execute. Events that cause an interrupt to occur are called interrupt sources. The request interrupt processing signal sent by the interrupt source to the processor is called an interrupt request. The process by which the processor processes an interrupt request is called interrupt handling.

The scheduling subsystem is one of the core modules in the Linux kernel. The scheduling subsystem is used for task scheduling, such as determining the task to be executed, the execution start time and execution duration of the task, and so on. In the current Linux kernel, five scheduling classes are defined, as shown in FIG. 2 . The five scheduling classes are STOP scheduling class, Deadline (DL) scheduling class, Real Time (RT) scheduling class, Completely Fair Scheduler (CFS) scheduling class and idle ( IDLE) scheduling class, where STOP and IDLE are two special scheduling classes, not used for scheduling common tasks.

Among them, there is a priority order among scheduling classes. For example, if there are tasks waiting to be scheduled in both the RT scheduling class and the CFS scheduling class, the kernel will preferentially select a task to execute from the scheduling queue of the RT scheduling class. The tasks in the CFS scheduling class can only be scheduled for execution when all the tasks in the RT scheduling class are executed, or the processor core is voluntarily given up (such as sleep), or the running time of the RT task exceeds the pre-configured threshold. . In some systems (such as Android), the RT scheduling class and the CFS scheduling class take over most of the tasks in the operating system.

The CFS scheduling class is the default scheduling algorithm of the Linux kernel. This algorithm focuses on ensuring the fairness of scheduling, and can guarantee that all processes will be scheduled within a certain period of time. But precisely because of its fairness, even if the task has the highest priority, it cannot be guaranteed that the task will always be scheduled and executed first (even if the nice value is adjusted to -20), that is to say, the scheduling delay is uncontrollable.

The RT scheduling class is an algorithm that schedules strictly according to the priority. After a task wakes up, if it has a higher priority than the currently running task, it will trigger the preemption of the current running task, so that the processor core will immediately switch to execute the scheduled task. The wake-up high-priority task ensures the scheduling delay of the high-priority task. In order to ensure timely drawing (for example, a mobile phone with a refresh rate of 60 frames needs to complete one frame of drawing in 16.7ms), it is necessary to strictly ensure the scheduling delay of designated threads such as UI/Render thread and Surfaceflinger thread. If the scheduling delay is too large, the It will cause a freeze because it is too late to draw the frame. Therefore, the system recognizes these designated threads and configures them as RT tasks.

In an illustrative example, the scheduling queue of a processor core is shown in FIG. 3 . Wherein, the parameter prio of the task indicates the normalized priority of the task, and the value range is [0, 139]. When the value of the parameter prio is in [100, 139], it indicates that the task is a task managed by the CFS scheduling class; when the value of the parameter prio is in [0, 99], it indicates that the task is a task managed by the RT scheduling class. The value of the parameter prio is negatively correlated with the priority of the task, that is, the lower the value of the parameter prio, the higher the priority of the task. For example, the parameter prio of task 1 is 97, and the parameter prio of task 2 is 98. Then task 1 has a higher priority than task 2. In Fig. 3, the current scheduling queue of processor core 0 (abbreviated as core 0) includes task A (prio=98) managed by RT scheduling class, task X (prio=120) managed by CFS scheduling class and Task Y (prio=120) managed by the CFS scheduling class. After the task B (prio=97) managed by the RT scheduling class wakes up, in a possible implementation, if it supports high-priority tasks to preempt low-priority tasks, then core 0 immediately switches the currently executing task A to a high-priority task. For task B with priority, after switching, the scheduling queue of core 0 includes task B, task A, task X, and task Y in order of execution. In another possible implementation, if preemption is not supported (that is, preemption is turned off), high-priority task B cannot be scheduled immediately, and task B only joins the scheduling queue after waking up, and the currently executing task is still task A , at this time, the scheduling queue of core 0 includes task A, task B, task X, and task Y in order of execution.

In related technologies, in order to prevent concurrency during interrupt processing, a preemption operation is performed. During this period, if the Surfaceflinger thread joins the scheduling queue, it cannot be scheduled immediately due to preemption. It usually waits for a period of time (such as 4ms) before being scheduled for execution, which eventually leads to too late to draw, resulting in frame loss. In the case of large network traffic (such as updating applications in batches, downloading videos, etc.), the scheduling delay of soft interrupt processing can even reach 10ms, which is very prone to similar frame loss and freeze problems.

In a schematic example, a schematic diagram of an architecture of a Linux operating system for interrupt processing is shown in FIG. 4 . Interrupt is an asynchronous event processing mechanism, which is used to improve the concurrent processing capability of the system. When an interrupt request occurs, it will trigger the execution of the interrupt handler, and the interrupt handler is divided into two parts: the upper part of the interrupt and the lower part of the interrupt. The upper part of the interrupt corresponds to the hard interrupt, which is used to quickly process the interrupt. For example, the processor core calls the registered interrupt function according to the interrupt table. This interrupt function will call the corresponding function in the driver (Driver); the lower part of the interrupt corresponds to the soft interrupt. Interrupt, used to asynchronously handle the unfinished work in the upper half of the interrupt. The ksoftirqd process in the Linux kernel is specially responsible for the processing of soft interrupts. When it receives a soft interrupt, it will call the processing function corresponding to the corresponding soft interrupt, such as the net_rx_action function. At present, the main reason why the Surfaceflinger thread cannot be scheduled in time is that preemption is disabled for both the upper half of the interrupt and the lower half of the interrupt, and the processing of the lower half of the interrupt takes a long time. After the processing of the lower half of the interrupt is completed and the preemption is enabled, The Surfaceflinger thread will be scheduled for execution, but it is too late to complete the drawing frame. In order to solve the above problems, a processing method in the related art is to thread the interrupt processing, so that the interrupt processing can be preempted, so that high-priority tasks can be scheduled in time, effectively reducing the scheduling delay. In one possible implementation, a real-time set of patches (such as PREEMPT_RT patches) maintained outside the Linux mainline, this set of patches threads the kernel's interrupt handling and allows interrupt handling threads to be preempted by high-priority tasks. In this way, high-priority tasks will not be unscheduled due to interrupt processing, thereby reducing the scheduling delay caused by interrupt processing.

However, in the above method, there are the following problems: on the one hand, the original interrupt processing will be delayed due to the preemption of high-priority tasks. The deviation of 5ms will lead to the impact on other business processes/threads; on the other hand, the preemption of interrupt threads will introduce task context switching, which has performance overhead, and frequent switching will lead to a decrease in system throughput.

In order to solve the above problems, another processing method in the related art is the interrupt binding method, which is to bind the interrupt processing to the target processor core, and the target processor core is at least one pre-set processor core; according to the processor core load, the specified Threads are scheduled to other processor cores except the target processor core, so that the number of interrupts on other processor cores is controllable except for the target processor core, and the scheduling delay is also controllable without causing excessive scheduling delay.

In a schematic example, the electronic device includes 8 processors (core 0 to core 7), as shown in Figure 5a, the interrupt processing strategy adopted is interrupt balanced processing, and the interrupt processing is basically amortized on each processor core , that is, the interrupt processing time (in us) corresponding to each processor core is similar. Under this strategy, interrupt processing may migrate back and forth, resulting in uncontrollable scheduling delay. In Figure 5b, the interrupt processing strategy adopted is interrupt binding core processing, such as binding interrupt processing to core 0 and core 4 (other processor cores still have interrupt loads because some interrupt requests cannot be bound to cores , such as a clock interrupt). According to the processor core load, the specified thread is scheduled to other processor cores except core 0 and core 4 to control its scheduling delay.

But in above-mentioned method, there are following several problems: 1, can cause interrupt processing to be concentrated on the core of target processor (as shown in Fig. 5b core 0 and core 4), pull up the frequency of whole cluster, cause the waste of power consumption (same cluster The load of other processor cores is low, but the frequency is high); 2. Also because the interrupt processing is concentrated on the target processor core, other processor cores will not process even if they are idle, and the system throughput is low; 3. Interrupt binding Previously, it was often necessary to evaluate the interrupt load of each peripheral, and reasonably bind interrupts according to the load. This method lacks flexibility. If a new peripheral is added, the allocation of interrupts needs to be re-evaluated, and sometimes the original interrupt needs to be reassessed. Redesign bindings.

To this end, embodiments of the present application provide an interrupt scheduling method, electronic equipment, and a storage medium, so as to solve the problems existing in the above-mentioned related technologies. In the technical solution provided by the embodiment of the present application, the maximum value of the scheduling delay caused by the interrupt processing configured for the first processor core is the first delay threshold, so that the scheduling delay value of the first processor core is greater than the first In the case of the delay threshold, the current part of the interrupt request of the first processor core is migrated and bound to the second processor core, which ensures that the scheduling delay caused by interrupt processing on the first processor core is controllable, and avoids related problems. The problem of excessive scheduling delay caused by interrupt processing in the technology ensures the real-time nature of business processing and improves the overall performance of electronic equipment.

Before explaining the embodiment of the present application, the application scenario of the embodiment of the present application will be described first. Please refer to FIG. 6 , which shows a schematic diagram of an electronic device involved in an embodiment of the present application. The electronic device includes a hardware layer 610 , a kernel layer 620 and a user layer 630 . User layer 630 may run with at least one thread, each thread for processing tasks. The task scheduling process and interrupt response process of each thread are mainly implemented by the kernel layer 620 .

Wherein, the hardware layer 610 is the hardware basis in the electronic device. The electronic equipment may be base station equipment, transmission equipment, industrial robots and other electronic equipment that have certain requirements for real-time task processing. For example, if the electronic device is a mobile phone, the interrupt scheduling method provided by the embodiment of the present application can be applied to application scenarios that require fast response, such as autopilot, industrial control, virtual reality technology (Virtual Reality, VR) and other scenarios. Configuration can reduce task scheduling delay and ensure that key tasks can be scheduled in time.

Hardware layer 610 includes peripherals 612 , interrupt controller 614 and at least one processor 616 . The peripheral device 612 includes a wireless network card, a Bluetooth device, and the like. The processor 616 may be a single-core processor or a multi-core processor.

The peripheral device 612 generates an interrupt request when processing data (for example, a wireless network card sends and receives packets), and routes the interrupt request to one of the multiple processor cores through the interrupt controller 614 .

The kernel layer 620 is the layer where the operating system kernel, virtual storage space, and driver applications run. For example, the operating system kernel is the Linux kernel.

The kernel layer 620 includes an interrupt subsystem 622 and a scheduling subsystem 624 . The interrupt subsystem 622 includes an interrupt processing module 640 , an interrupt load collection module 641 , an interrupt load calculation module 642 , an interrupt load information statistics module 643 , an interrupt load policy module 644 , and an interrupt load balancing execution module 645 . The scheduling subsystem 624 includes a specified thread configuration module 651 , a task core selection policy module 652 and a task scheduling execution module 653 .

The interrupt processing module 640 obtains the interrupt request of the processor core, and starts interrupt processing in the interrupt subsystem 622, and the interrupt processing includes hard interrupt processing and soft interrupt processing.

The interrupt load collection module 641 records the interrupt processing duration, and sends the interrupt processing duration to the interrupt load calculation module 642 . Wherein, the interrupt processing duration includes the total duration of hard interrupt processing and soft interrupt processing.

The interrupt load calculation module 642 uses a preset algorithm to determine the scheduling delay value of the current processor core according to the interrupt processing duration provided by the interrupt load collection module 641, and the unit of the calculation result is us or ns.

The interrupt load information statistics module 643 saves and summarizes the scheduling delay information on the processor core, and the scheduling delay information includes the summary information of the scheduling delay value of each interrupt request on the processor core.

The interrupt load policy module 644 obtains the first delay threshold configured for the first processor core by the user layer 630, and makes a decision according to the scheduling delay information and the first delay threshold stored in the interrupt load information statistics module 643. When the scheduling delay value of the first processor core is greater than the preconfigured first delay threshold, the core binding policy is determined, and the core binding policy is sent to the interrupt load balancing execution module 645. out, bound to other second processor cores, so as to ensure that the scheduling delay value of the first processor core is less than the first delay threshold.

The interrupt load balancing execution module 645 receives the core binding policy from the interrupt load policy module 644, operates the interrupt controller 614 according to the core binding policy, and binds the corresponding interrupt request to the second processor core.

The scheduling subsystem 624 is responsible for scheduling and executing all processes/threads in the system.

The specified thread configuration module 651 supports configuring the second delay threshold for the specified thread.

The task core selection policy module 652 is used to check the interrupt load of the first processor core in the task core selection process, and when the scheduling delay value is less than or equal to the second delay threshold, it is considered that the corresponding processor core meets the condition , as a second processor core for further screening.

The task scheduling execution module 653 is used to add the process/thread to the scheduling queue of the corresponding processor core. Since the interrupt load of the processor core has been checked in the previous step, it can be considered that the corresponding process/thread can be obtained within a certain period of time. Schedule execution.

The user layer 630 is the layer where normal applications run. For example, the user layer includes an application framework layer (such as a Framework layer). The user layer 630 includes an interrupt load management module 632 and a specified thread identification/control module 634 .

The user layer 630 is responsible for configuring the first latency threshold of the first processor core, and identifying and configuring specified threads.

The interrupt load control module 632 is responsible for monitoring the overall interrupt load of the system, and when the interrupt load of a certain processor core is too large, selects a suitable second processor core (such as selecting a processor core with a lighter interrupt load at present, which can reduce the interrupt load). Migration), and configure the first latency threshold for the processor core to ensure that there is at least one processor core with a controllable interrupt load in each cluster.

The specified thread identification/control module 634 is responsible for identifying the thread responsible for drawing frames (such as UI/Render) in the user layer 630, and configuring the second delay threshold for it.

It should be noted that, for the functions implemented by the above functional modules, reference may be made to the relevant descriptions in the following method embodiments, which will not be introduced here. Moreover, the electronic device provided by the above-mentioned embodiments only uses the division of the above-mentioned functional modules as an example to illustrate when realizing its functions. The internal structure of the system is divided into different functional modules to complete all or part of the functions described above.

In the following, several exemplary embodiments are used to introduce the interrupt scheduling method provided by this application.

Please refer to FIG. 7 , which shows a flowchart of an interrupt scheduling method provided by an exemplary embodiment of the present application. The embodiment of the present application is illustrated by taking the interrupt scheduling method applied to the electronic device shown in FIG. 6 as an example. The interrupt scheduling method includes:

In step 701, the user layer configures a first delay threshold of the first processor core, and sends first configuration information to the kernel layer.

Optionally, the user layer determines that at least one processor core in the electronic device is the first processor core, and the maximum value of the scheduling delay caused by interrupt processing configured for the first processor core is the first delay threshold. The user layer sends the first configuration information to the kernel layer.

Schematically, the first processor core is a processor core, and the first configuration information includes a processor core identifier of the first processor core and a first latency threshold. Alternatively, the first processor core is at least two processor cores, the first configuration information includes at least two processor core identifiers and their corresponding first delay thresholds, and the at least two processor core identifiers respectively correspond to first time delay thresholds. The delay thresholds can be the same or different. This embodiment of the present application does not limit this, and for the convenience of introduction, only the first processor core is taken as an example for description.

Wherein, the processor core identification is used to uniquely identify the first processor core among the multiple processor cores of the electronic device, and the first delay threshold is the scheduling delay caused by the interrupt processing configured for the first processor core. maximum value. The first delay threshold may be dynamically adjusted subsequently according to the scheduling delay value in each processor core and/or the completion of drawing frames.

Step 702, the kernel layer judges whether the scheduling delay value of the first processor core is greater than the first delay threshold according to the first configuration information.

Correspondingly, the kernel layer receives the first configuration information sent by the user layer, where the first configuration information includes the processor core identifier of the first processor core and the first delay threshold.

Optionally, when the kernel layer receives the first configuration information sent by the user layer or updates information on the scheduling delay values of each processor core, it determines whether the scheduling delay value of the first processor core is greater than the first Delay threshold, if the current scheduling delay value of the first processor core is less than or equal to the first delay threshold, the process of this embodiment ends, and if the scheduling delay value of the first processor core is greater than the first delay threshold, execute Step 703.

Wherein, the scheduling latency value of the first processor core is used to indicate the current interrupt load of the first processor core. Optionally, the scheduling delay value is positively correlated with the interrupt load, that is, the greater the interrupt load, the greater the scheduling delay value.

Optionally, the scheduling latency value of the first processor core is an actual value or an estimated value of the current scheduling latency of the first processor core. Schematically, the scheduling delay value of the first processor core is an estimated value of the scheduling delay determined based on the current interrupt processing duration of the first processor core.

It should be noted that, for the process of determining the scheduling delay value of the first processor core at the kernel layer, reference may be made to relevant descriptions in the following embodiments, which will not be introduced here.

Step 703: If the scheduling latency value of the first processor core is greater than the first latency threshold, the kernel layer performs interrupt equalization processing and sends second configuration information to the interrupt controller.

If the current scheduling delay value of the first processor core is greater than the first delay threshold, the kernel layer determines an interrupt balancing strategy, and sends second configuration information indicating the interrupt balancing strategy to the interrupt controller. Optionally, the kernel layer sends the second configuration information to the interrupt controller by scheduling the latency balance execution module.

Wherein, the interrupt balancing strategy indicated by the second configuration information is to migrate and bind part of the current interrupt requests of the first processor core to the second processor core. The second processor core is different from the first processor core. After the migration and binding The scheduling delay value of the first processor core is less than or equal to the first delay threshold.

Optionally, the second configuration information includes an interrupt number to be migrated out of the first processor core and a processor core identifier of the second processor core. Schematically, the interrupt numbers to be moved out are m interrupt numbers to be moved out, and m is a positive integer. One of the interrupt numbers corresponds to at least one interrupt request.

Schematically, the second configuration information includes the interrupt number to be migrated out and the binding relationship information corresponding to the interrupt number to be migrated out, wherein the binding relationship information corresponding to one interrupt number is used to indicate at least one interrupt number corresponding to the interrupt number The binding relationship between requests and processor cores. For example, the electronic device includes 8 processor cores, the interrupt number to be migrated is interrupt number 10, and the interrupt number 10 corresponds to multiple interrupt requests, and the second configuration information includes the interrupt number 10 and the 8-bit information corresponding to the interrupt number 10. Information, there is a one-to-one correspondence between 8 bits and 8 processor cores, and when the bit is the first value, it is used to indicate that multiple interrupt requests corresponding to the interrupt number are bound to the processor corresponding to the bit The core, when the bit is the second value, is used to indicate that the multiple interrupt requests corresponding to the interrupt number have no binding relationship with the processor core corresponding to the bit. For example, the first value is 1, and the second value is 0. This embodiment of the present application does not limit it.

Optionally, the first processor currently includes multiple interrupt loads, and there is a one-to-one correspondence between the multiple interrupt loads and the multiple interrupt numbers. If the current scheduling delay value of the first processor core is greater than the first delay threshold, the kernel layer determines the absolute value of the difference between the current scheduling delay value of the first processor core and the first delay threshold as the first difference value. The first processor selects at least one interrupt load from a plurality of interrupt loads according to a preset algorithm, and determines the interrupt number corresponding to the selected at least one interrupt load as the interrupt number to be moved out, so that the scheduling time corresponding to the interrupt number to be moved out If the total number of delays is greater than the first difference, it is determined that the interrupt balancing strategy is to migrate and bind the interrupt request corresponding to the interrupt number to be migrated out to the second processor core. For example, the default algorithm is to select the interrupt numbers sequentially according to the sequence of interrupt loads corresponding to the interrupt numbers from high to low. It should be noted that the preset algorithm may also adopt other possible implementation manners, which are not limited in this embodiment of the present application. Wherein, the second processor core is other processor cores in the electronic device except the first processor core. Optionally, the second processor core is any processor core except the first processor core. Alternatively, the second processor core is any at least two processor cores other than the first processor core.

Optionally, the second processor core is at least one processor core other than the first processor core whose scheduling delay value is less than the third delay threshold. Schematically, the kernel layer traverses to query the scheduling delay values of other processor cores, and determines the processor core whose scheduling delay value is less than the third delay threshold as the second processor core. Wherein, the third delay threshold is a user-defined setting or a default setting. This embodiment of the present application does not limit it.

Optionally, the second processor core is at least one processor core other than the first processor core with the smallest scheduling delay value. Schematically, the kernel layer traverses to query the scheduling delay values of other processor cores, sorts the second processor cores in ascending order of scheduling delay values, and determines the first n processor cores after sorting as The second processor core, n is a positive integer.

In step 704, the interrupt controller migrates and binds some current interrupt requests of the first processor core to the second processor core according to the second configuration information.

The interrupt controller receives the second configuration information sent by the kernel layer, executes the interrupt balancing strategy indicated by the second configuration information, that is, migrates and binds part of the current interrupt requests of the first processor core to the second processor core, and the second processing The processor core is different from the first processor core, and the scheduling delay value of the first processor core after migration and binding is less than or equal to the first delay threshold. Wherein, the second processor core is at least one processor core other than the first processor core.

Optionally, the second configuration information includes an interrupt number to be migrated out of the first processor core and a processor core identifier of the second processor core. The interrupt controller migrates and binds at least one interrupt request corresponding to the interrupt number to the second processor core according to the second configuration information. Schematically, the interrupt numbers to be moved out are m interrupt numbers to be moved out, and m is a positive integer.

Optionally, the interrupt controller migrates and binds part of the current interrupt requests of the first processor core to the second processor core in a preset amortization mode, and the preset amortization mode is used to indicate the number of other processor cores after migration and binding. The absolute value of the difference between the scheduling delay values is smaller than the first difference threshold. Wherein, the other processor cores are all processor cores in the electronic device except the first processor core, and the first difference threshold is a custom setting or a default setting. This embodiment of the present application does not limit it.

To sum up, in the embodiment of the present application, the kernel layer dynamically adjusts the interrupt binding according to the current scheduling delay value of the first processor core and the first delay threshold configured by the user layer. If the current scheduling time of the first processor core is If the delay value is greater than the first delay threshold, the interrupt controller will migrate and bind some of the current interrupt requests of the first processor core to the second processor core, so that the scheduling delay value of the first processor core after migration and binding Less than or equal to the first delay threshold, the scheduling delay on the first processor core is reduced. Part of the interrupt requests moved out can be reasonably shared on other processor core clusters to ensure the concurrency of interrupt processing and avoid the problem of excessive load on a single processor core that increases the frequency of the entire cluster, resulting in waste of power consumption.

Regarding the scheduling delay value statistics, there are still the following problems in related technologies: hard interrupt processing and soft interrupt processing are processed separately, soft interrupt processing does not know which hard interrupt processing triggers its own execution, and the corresponding The scheduling delay value is also counted separately.

In fact, the two are related. For example, in the process of receiving packets from the network, the kernel enters the hard interrupt processing for simple hardware configuration (the execution time is relatively short), and then triggers the soft interrupt processing through the raise_softirq_irqoff interface. The data packet is actually processed in the handler function (the execution takes a long time). It can be said that in this scenario, soft interrupt processing will not be triggered without hard interrupt processing, and both should be included in the overhead statistics of the same interrupt number.

In related technologies, the statistics of scheduling delay values are based on the granularity of processor cores, and do not support load statistics based on the granularity of interrupts. Therefore, some current software that implements the interrupt balance function can only evaluate the scheduling delay value of a certain interrupt number based on the number of interrupts, and the processing time of different interrupts is inconsistent. Such statistical results are not accurate and cannot be well supported. The interrupt balance processing in the embodiment of the present application. For example, the hard interrupt processing of the network card itself does not take much time, but its soft interrupt processing is time-consuming. If the calculation method of the scheduling delay value in the related technology does not link the two, it may cause the interruption of the network card. The illusion of less overhead.

In view of the above problems, the embodiment of this application proposes a Per-Interrupt Load Tracking (PILT) method of interrupt granularity, that is, the scheduling delay value statistics are performed according to the interrupt request, and the corresponding soft interrupt processing overhead is included in the In the scheduling delay value corresponding to the interrupt request. Based on the embodiment shown in Figure 7, before the kernel layer judges whether the scheduling delay value of the first processor core is greater than the first delay threshold in step 702, the kernel layer needs to count the scheduling delay value of the first processor core . In a possible implementation, the kernel layer performs real-time statistics on the scheduling delay value according to the received interrupt request, and the process of scheduling delay value statistics includes the following steps, as shown in Figure 8:

In step 801, the interrupt processing duration corresponding to the interrupt request is acquired, and the interrupt processing duration includes the total duration of hard interrupt processing and soft interrupt processing.

Optionally, after receiving an interrupt request, determine the start time and end time of the hard interrupt processing corresponding to the interrupt request, and determine the absolute value of the difference between the start time and end time of the hard interrupt processing as the first processing duration ; Determine the start time and end time of the soft interrupt processing corresponding to the interrupt request, and determine the absolute value of the difference between the start time and the end time of the soft interrupt processing as the second processing duration; the first processing duration and the second processing duration of the interrupt request The sum of the two processing durations is determined as the interrupt processing duration of the interrupt request.

Optionally, in order to establish the association between hard interrupt processing and soft interrupt processing, before the hard interrupt processing of an interrupt request ends and the soft interrupt processing is triggered, the interrupt number of the interrupt request and the soft interrupt processing soft interrupt value triggered by it are saved. interrupt type. Wherein, the interrupt number of an interrupt request is used to uniquely identify the interrupt request among multiple interrupt requests. Soft interrupt types include network receive interrupt, network send interrupt, timing interrupt, scheduling interrupt, read-copy update (Read-Copy Update, RCU) lock and other types.

Optionally, since there may be many hard interrupts processed at the time of statistics, and the soft interrupts may not be processed in time, it is necessary to save the array, that is, the interrupt number of the interrupt request and the soft interrupt type of the soft interrupt triggered by it are stored in an array. . For example, if the interrupt number of an interrupt request is "200" and the softirq type is network receive interrupt "NET_RX", then "softirq_type: NET_RX; hw_irq: 200" is stored in an array. Soft interrupt processing obtains the first array member that matches the soft interrupt type from the array saved in the previous step, for example, the soft interrupt for network packet receiving processing corresponds to the soft interrupt type "NET_RX", and obtains the matching with the soft interrupt type "NET_RX" The interrupt number in the first array member of , the second processing duration of the soft interrupt processing is included in the interrupt processing duration of the interrupt number.

For example, the first processing time of interrupt number 200 is delta_hardirq200, and the second processing time of interrupt number 200 is delta_softirq200, then the interrupt processing time of interrupt number 200 is delta_irq200=delta_hardirq200+delta_softirq200.

Step 802, according to the interrupt processing duration of the interrupt request, a preset algorithm is used to determine the scheduling delay value corresponding to the interrupt request.

Optionally, the preset algorithm includes an entity load tracking algorithm (Per-entity load tracking, PELT) or a window assisted load tracking (Window Assisted Load Tracking, WALT).

In a possible implementation, the WALT algorithm is used to preset the length of the window (for example, 10ms), and the average value or the current maximum interrupt processing duration in the window of the latest preset number (for example, the preset number is 5) is counted. value, and determine the average value or maximum value obtained from the statistics as the scheduling delay value corresponding to the interrupt request.

For another example, the PELT algorithm is used, the value of the attenuation factor is preset, and the attenuation factor is used to perform weighted summation of the interrupt processing duration in a preset number of windows, and the attenuation factor is a positive number less than 1. For example, if the attenuation factor is y, and the interrupt processing durations in the three windows are 10, 9, and 8 respectively, then the scheduling delay value corresponding to the interrupt request is 10×y+9×y ² +8×y ³ .

Optionally, information about the interrupt number and the scheduling delay value corresponding to the interrupt request is saved. Schematically, the information of the interrupt number and the scheduling delay value corresponding to the interrupt request is kept in a designated variable of the first processor core, for example, the designated variable is a per processor core variable.

Step 803: Summing the scheduling delay value corresponding to the interrupt request and the current scheduling delay value of the first processor core to obtain an updated scheduling delay value.

Optionally, a weighted sum is performed on the scheduling delay value corresponding to the interrupt request and the current scheduling delay value of the first processor core to obtain an updated scheduling delay value.

To sum up, compared with the scheme in the related art that calculates the scheduling delay value overhead according to the processor core dimension, the embodiment of the present application tracks and calculates the load overhead of each interrupt request, so as to avoid the load that can only be calculated based on the number of interrupts in the past. The extensive algorithm supports more accurate interrupt balance processing, and includes the time overhead of soft interrupt processing triggered by hard interrupt processing into the corresponding interrupt processing time, making the scheduling delay value determined based on interrupt processing time more accurate, so that subsequent It can perform interrupt equalization processing more accurately.

In addition, in related technologies, the scheduling delay caused by interrupt processing is not considered when selecting task cores, resulting in excessive scheduling delay; or a unified interrupt load judgment standard is adopted for all threads, resulting in the background thread and the specified thread being selected for the same processing core, resulting in unpredictable impacts (such as locks leading to unschedulable). However, the embodiment of the present application supports configuring the scheduling delay requirement for the specified thread, and judges whether the scheduling delay requirement is greater than or equal to the scheduling delay value of the processor core when selecting a core, and only selects the corresponding processor core when the requirement is met, ensuring that the specified Threads can be scheduled in time, reducing the probability of frame loss. Instead of critical threads (such as background threads), since there is no delay requirement, you can choose to schedule processor cores with high delay values to reduce interference with the operation of critical threads. Based on the electronic equipment shown in Figure 6, the task selection process includes the following steps, as shown in Figure 9:

In step 901, the user layer configures a second delay threshold for a specified thread of the foreground application, and sends third configuration information to the kernel layer.

Optionally, the user layer determines the designated thread of the foreground application, and the maximum value of the scheduling delay configured for the designated thread is the second delay threshold. The user layer sends third configuration information to the kernel layer, where the third configuration information includes a thread identifier of a specified thread and a second delay threshold.

Wherein, the thread identifier of the specified thread is used to uniquely identify the specified thread among multiple threads. The designated thread is a thread that requires a scheduling delay. Optionally, the designated thread includes a frame drawing thread and/or a process of an inter-process communication mechanism. For example, the specified thread is UI/Render thread, Surfaceflinger thread, and communication-related binder thread. The embodiment of the present application does not limit the type of the specified thread.

Wherein, the second delay threshold is an upper limit value of a scheduling delay value configured for the specified thread.

The second delay threshold can be dynamically adjusted later according to the completion of frame drawing. For example, if the absolute value of the difference between the actual end time drawn in the previous frame and the specified end time is greater than the second difference threshold, then increase the second delay threshold; if the difference between the actual end time drawn in the previous frame and the specified end time If the absolute value of the value is less than or equal to the second difference threshold, the second delay threshold is reduced to ensure that the thread can be scheduled faster. Wherein, the second difference threshold is a custom setting or a default setting. This embodiment of the present application does not limit it.

Optionally, the user layer identifies the specified thread, obtains the thread identifier of the specified thread, configures the second delay threshold for the specified thread, and sends third configuration information to the kernel layer in a preset manner. Schematically, the default mode is an I/O device control (input/output control, ioctl) mode. For example, the third configuration information includes "tid=1200; lat_req=200000", wherein the thread identifier of the specified thread is 1200, and the scheduling delay requirement is 200000 ns, that is, 200 us.

Step 902: According to the third configuration information, the kernel layer determines the processor core that satisfies the preset core selection condition as the target processor core. The preset core selection condition includes that the current scheduling delay value of the processor core is less than or equal to the second time delay threshold.

After the kernel layer receives the third configuration information sent by the user layer, it checks the current state of the specified thread corresponding to the thread identifier, and if the specified thread is executing, no operation is performed; if the specified thread is not executing, the kernel layer tries to wake up the specified thread. A designated thread, if the designated thread is not allowed to be woken up (for example, waiting for a lock), then modify the second delay threshold required by the scheduling delay (for example, reduce the second delay threshold). If the specified thread is allowed to be awakened, it enters the core selection process.

Optionally, in the core selection process, for a processor core among the plurality of processor cores, the kernel layer judges whether the processor core satisfies a preset core selection condition, and the preset core selection condition includes the current scheduling of the processor core The delay value is less than the second delay threshold. If the processor core meets the preset core selection condition, then determine the processor core as the target processor core, and execute step 903; if the processor core does not meet the preset core selection condition, continue to check the next processor core , performing the step of judging whether the processor core satisfies the preset core selection condition again.

It should be noted that, the current statistical method of scheduling delay value of the processor core can refer to the above-mentioned current statistical method of scheduling delay value of the target processor core by analogy, which will not be repeated here.

Optionally, the preset core selection condition includes that the current scheduling delay value of the processor core is less than the second delay threshold and other core selection conditions. For example, other core selection conditions include that the priority of the processor is greater than the preset priority threshold, and/or the attribute information of the processor matches the specified thread. This embodiment of the present application does not limit it.

Step 903, the kernel layer adds the specified thread to the scheduling queue of the target processor core.

After the kernel layer adds the specified thread to the scheduling queue of the target processor core, it waits for scheduling execution. Since the scheduling delay value of the specified thread is in a controllable range, the specified thread can be scheduled in time within the time that meets the scheduling delay requirement.

To sum up, the embodiment of the present application supports the configuration of scheduling delay requirements for task granularity, distinguishes between foreground and background threads, and reduces the impact of background threads on specified foreground threads. When selecting a task core, consider the task scheduling delay requirement and the scheduling delay value of the processor core. Only when the current scheduling delay value of the processor core is less than or equal to the second delay threshold required by the task scheduling delay, can the The processor core is used as the target processor core to ensure that key threads can be selected to the processor core with a low scheduling delay value and be scheduled in time.

In a schematic application scenario, as shown in FIG. 10 , the “app market” application A is running in the foreground of the mobile phone. When the click operation signal acting on the control 1001 in the application A is received, five recommended application programs are executed. Batch updates. After the mobile phone switches the application A to run in the background, the "Magazine Exchange" application is opened to display multiple magazine covers. Since application A needs to download the upgrade package through the network when performing batch updates, a large amount of network traffic will be received/forwarded through the wireless network card at this time, and the network card notifies the kernel layer to read and write data from the network card memory through an interrupt request. There are a large number of NIC interrupt requests generated. And because it involves data packet processing, the interrupt processing of network sending and receiving packets often takes a long time (up to 10ms), if at this time UI/Render thread, Surfaceflinger thread and other frame drawing threads select the processor that is or will be performing network card interrupt processing core, it is very easy to cause frame loss, causing the user interface to freeze when browsing magazines in application B.

In order to solve the above problems, the task selection method provided by the embodiment of the present application includes the following steps, as shown in Figure 11: Step 1101, the Framework layer identifies the foreground application as "Magazine Collection" application B, and it is the UI/Render of application B The second delay threshold required by the thread configuration key scheduling delay is 500us; step 1102, the Framework layer sets the first delay threshold of processor core 0 and processor core 4 to 500us (4 small core + 4 large core architecture), Ensure that both the small core and the large core have at least one processor core with a controllable task scheduling delay. Step 1103, after the Framework layer delivers the first delay threshold, processor core 0 and processor core 4 respectively decide whether to bind part of the interrupt requests sent to the processor core to other processor cores according to the current scheduling delay value. processor cores, after some interrupt requests exceeding the first delay threshold are moved out, the scheduling delay values of processor core 0 and processor core 4 can be guaranteed to be below 500us. Step 1104, when the mobile phone receives the sliding operation signal in the application B, the frame drawing operation is triggered, and the application B calls the UI/Render thread to draw the frame. Step 1105, after the UI/Render thread is woken up, the core selection process is performed according to the second delay threshold required by the scheduling delay. At this time, since other processor cores are processing network card interrupts and the load is high, there is a high probability that the core will be selected. Processor core 0 and processor core 4, after adding the UI/Render thread to the scheduling queue of these two processor cores, since the scheduling delay value is less than 500us, it can ensure that the UI/Render thread is scheduled within 500us, thereby reducing Probability of dropped frames.

In a schematic example, as shown in Figure 12, in related technologies (assuming that application B takes 16.7ms to draw a frame), due to the lack of control over the scheduling delay value, the specified thread may be interrupted for a long time In the ready (runnable) state, such as 3ms or 8ms. Once the interrupt processing time exceeds 6ms, it is very prone to frame loss. However, through the interrupt scheduling method provided by the embodiment of the present application, the scheduling delay of the specified thread is adjusted to 500us, thereby ensuring that the scheduling delay of the specified thread is within a controllable range, and will not cause frame loss and freeze due to scheduling delay The problem.

Please refer to FIG. 13 , which shows a flowchart of an interrupt scheduling method provided by another exemplary embodiment of the present application. The embodiment of the present application is illustrated by taking the interrupt scheduling method applied to an electronic device as an example. The interrupt scheduling method includes:

Step 1301, acquire a preconfigured first latency threshold, where the first latency threshold is the maximum value of scheduling latency caused by interrupt processing configured for the first processor core.

Step 1302, acquiring a scheduling delay value of the first processor core, where the scheduling delay value is used to indicate the current interrupt load of the first processor core.

Step 1303, when the scheduling delay value is greater than the first delay threshold, migrate and bind some of the current interrupt requests of the first processor core to the second processor core, the second processor core is different from the first processor core nuclear.

It should be noted that, for relevant details of each step in this embodiment, reference may be made to relevant descriptions in the foregoing embodiments, and details are not repeated here.

The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

Please refer to FIG. 14 , which shows a block diagram of an interrupt scheduling device provided by an exemplary embodiment of the present application. The device can be implemented as all or part of the electronic equipment provided above through software, hardware or a combination of the two. The apparatus may include: a first obtaining unit 1410 , a second obtaining unit 1420 and a binding unit 1430 .

The first obtaining unit 1410 is configured to obtain a preconfigured first delay threshold, where the first delay threshold is the maximum value of the scheduling delay caused by the interrupt processing configured for the first processor core;

The second acquiring unit 1420 is configured to acquire a scheduling delay value of the first processor core, where the scheduling delay value is used to indicate the current interrupt load of the first processor core;

The binding unit 1430 is configured to migrate and bind part of the current interrupt requests of the first processor core to the second processor core when the scheduling delay value is greater than the first delay threshold, and the second processor core is different from the first processor core.

In another possible implementation, after migration and binding, the absolute values of the differences between the scheduling delay values of other processor cores are all smaller than the preset first difference threshold, and the other processor cores are Each processor core other than the processor core.

In another possible implementation manner, the apparatus is used in an electronic device including a user layer, a kernel layer, and a hardware layer, and the first obtaining unit 1410 is further configured to send the first configuration information to the kernel layer through the user layer. The configuration information includes the processor core identification of the first processor core and the first delay threshold; the kernel layer receives the first configuration information sent by the user layer;

The binding unit 1430 is further configured to send second configuration information to the interrupt controller at the hardware layer through the kernel layer when the scheduling delay value is greater than the first delay threshold, the second configuration information includes The interrupt number to be migrated out and the processor core identifier of the second processor core; the interrupt controller migrates and binds at least one interrupt request corresponding to the interrupt number to the second processor core according to the second configuration information.

In another possible implementation manner, the device further includes: a statistical unit; the statistical unit is used for:

After receiving the interrupt request, obtain the interrupt processing duration corresponding to the interrupt request, and the interrupt processing duration includes the total duration of hard interrupt processing and soft interrupt processing;

According to the interrupt processing time of the interrupt request, the preset algorithm is used to determine the scheduling delay value corresponding to the interrupt request;

The scheduling delay value corresponding to the interrupt request is summed with the current scheduling delay value of the first processor core to obtain an updated scheduling delay value.

In another possible implementation manner, the device further includes: a nuclear selection unit; the nuclear selection unit is used for:

Obtain a pre-configured second latency threshold, where the second latency threshold is the maximum value of the scheduling latency caused by the interrupt processing configured for the specified thread;

After the specified thread is awakened, the processor core that meets the preset core selection condition is determined as the target processor core, and the preset core selection condition includes that the current scheduling delay value of the processor core is less than or equal to the second delay threshold;

Add the specified thread to the scheduling queue of the target processor core.

In another possible implementation manner, the specified thread includes a frame drawing process of a foreground application and/or a process of an inter-process communication mechanism.

It should be noted that, when realizing the functions of the device provided by the above-mentioned embodiments, the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional modules according to the needs. The internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and the method embodiment provided by the above embodiment belong to the same idea, and the specific implementation process thereof is detailed in the method embodiment, and will not be repeated here.

An embodiment of the present application provides an electronic device, which includes: a processor; a memory for storing processor-executable instructions; wherein, the processor is configured to implement the steps performed by the electronic device in the above-mentioned embodiments when executing the instructions. Interrupt dispatch method.

An embodiment of the present application provides a computer program product, including computer-readable codes, or a non-volatile computer-readable storage medium carrying computer-readable codes, when the computer-readable codes are run in a processor of an electronic device , the processor in the electronic device executes the interrupt scheduling method executed by the electronic device in the foregoing embodiments.

An embodiment of the present application provides a non-volatile computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the interrupt scheduling method performed by the electronic device in the foregoing embodiments is implemented.

A computer readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of computer-readable storage media include: portable computer disk, hard disk, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), erasable Electrically Programmable Read-Only-Memory (EPROM or flash memory), Static Random-Access Memory (Static Random-Access Memory, SRAM), Portable Compression Disk Read-Only Memory (Compact Disc Read-Only Memory, CD -ROM), Digital Video Disc (DVD), memory sticks, floppy disks, mechanically encoded devices such as punched cards or raised structures in grooves with instructions stored thereon, and any suitable combination of the foregoing .

Computer readable program instructions or codes described herein may be downloaded from a computer readable storage medium to a respective computing/processing device, or downloaded to an external computer or external storage device over a network, such as the Internet, local area network, wide area network, and/or wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. A network adapter card or a network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing/processing device .

Computer program instructions for performing the operations of the present application may be assembly instructions, instruction set architecture (Instruction Set Architecture, ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or in one or more source or object code written in any combination of programming languages, including object-oriented programming languages—such as Smalltalk, C++, etc., and conventional procedural programming languages—such as the “C” language or similar programming languages. Computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server implement. In cases involving a remote computer, the remote computer can be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or it can be connected to an external computer such as use an Internet service provider to connect via the Internet). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or programmable logic arrays (Programmable Logic Array, PLA), the electronic circuit can execute computer-readable program instructions, thereby realizing various aspects of the present application.

Aspects of the present application are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It should be understood that each block of the flowcharts and/or block diagrams, and combinations of blocks in the flowcharts and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine such that when executed by the processor of the computer or other programmable data processing apparatus , producing an apparatus for realizing the functions/actions specified in one or more blocks in the flowchart and/or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause computers, programmable data processing devices and/or other devices to work in a specific way, so that the computer-readable medium storing instructions includes An article of manufacture comprising instructions for implementing various aspects of the functions/acts specified in one or more blocks in flowcharts and/or block diagrams.

It is also possible to load computer-readable program instructions into a computer, other programmable data processing device, or other equipment, so that a series of operational steps are performed on the computer, other programmable data processing device, or other equipment to produce a computer-implemented process , so that instructions executed on computers, other programmable data processing devices, or other devices implement the functions/actions specified in one or more blocks in the flowcharts and/or block diagrams.

The flowchart and block diagrams in the figures show the architecture, functions and operations of possible implementations of apparatuses, systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in a flowchart or block diagram may represent a module, a portion of a program segment, or an instruction that includes one or more Executable instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved.

It should also be noted that each block in the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts, can be implemented with hardware (such as circuits or ASIC (Application Specific Integrated Circuit, application-specific integrated circuit)), or can be implemented with a combination of hardware and software, such as firmware.

Although the present application has been described in conjunction with various embodiments here, however, in the process of implementing the claimed application, those skilled in the art can understand and Other variations of the disclosed embodiments are implemented. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

Having described various embodiments of the present application above, the foregoing description is illustrative, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principle of each embodiment, practical application or improvement of technology in the market, or to enable other ordinary skilled in the art to understand each embodiment disclosed herein.

Claims

An interrupt scheduling method, characterized in that the method comprises:

Acquiring a preconfigured first delay threshold, where the first delay threshold is the maximum value of scheduling delay caused by interrupt processing configured for the first processor core;

Acquire a scheduling delay value of the first processor core, where the scheduling delay value is used to indicate a current interrupt load of the first processor core;

When the scheduling delay value is greater than the first delay threshold, migrate and bind part of the current interrupt requests of the first processor core to a second processor core, and the second processor core is different from the The first processor core.
The method according to claim 1, wherein the scheduling delay value of the first processor core after the migration binding is less than or equal to the first delay threshold.
The method according to claim 1 or 2, wherein the absolute values of the differences between the scheduling delay values of other processor cores after the migration and binding are all smaller than a preset first difference threshold, the The other processor cores are all processor cores except the first processor core.
The method according to any one of claims 1 to 3, wherein the method is used in an electronic device including a user layer, a kernel layer, and a hardware layer, and the obtaining a preconfigured first delay threshold includes:

The kernel layer receives first configuration information sent by the user layer, where the first configuration information includes a processor core identifier of the first processor core and the first delay threshold;

When the scheduling delay value is greater than the first delay threshold, migrating and binding the current part of the interrupt request of the first processor core to the second processor core includes:

When the scheduling delay value is greater than the first delay threshold, the kernel layer sends second configuration information to the interrupt controller of the hardware layer, the second configuration information includes the first processor core The interrupt number to be migrated out and the processor core identifier of the second processor core; the second configuration information is used to instruct the interrupt controller to migrate and bind at least one interrupt request corresponding to the interrupt number to The second processor core.
The method according to any one of claims 1 to 4, wherein the method further comprises:

After receiving the interrupt request, the interrupt processing duration corresponding to the interrupt request is obtained, and the interrupt processing duration includes the total duration of hard interrupt processing and soft interrupt processing;

According to the interrupt processing duration of the interrupt request, a preset algorithm is used to determine the scheduling delay value corresponding to the interrupt request;

The scheduling delay value corresponding to the interrupt request is summed with the current scheduling delay value of the first processor core to obtain the updated scheduling delay value.
The method according to any one of claims 1 to 5, wherein the method further comprises:

Obtaining a pre-configured second delay threshold, the second delay threshold is the maximum value of the scheduling delay caused by the interrupt processing configured for the specified thread;

After the specified thread is woken up, the processor core that meets the preset core selection condition is determined as the target processor core, and the preset core selection condition includes that the current scheduling delay value of the processor core is less than or equal to the specified The second delay threshold;

Add the specified thread to the scheduling queue of the target processor core.
The method according to claim 6, wherein the specified thread includes a frame drawing process and/or a process of an inter-process communication mechanism of the foreground application.
An electronic device, characterized in that the electronic device comprises:

processor;

memory for storing processor-executable instructions;

Wherein, the processor is configured to implement the method according to any one of claims 1-8 when executing the instructions.
A non-volatile computer-readable storage medium, on which computer program instructions are stored, wherein, when the computer program instructions are executed by a processor, the method according to any one of claims 1-8 is implemented.
A computer program product, comprising computer-readable codes, or a non-volatile computer-readable storage medium bearing computer-readable codes, characterized in that, when the computer-readable codes are run in an electronic device, the A processor in the electronic device executes the method of any one of claims 1-8.