WO2022227063A1

WO2022227063A1 - Lga pad structure, manufacturing method, chip module, printed circuit board, and device

Info

Publication number: WO2022227063A1
Application number: PCT/CN2021/091674
Authority: WO
Inventors: 李永胜; 史坡; 杨正得; 杨威; 曾川权
Original assignee: 华为技术有限公司
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2022-11-03
Also published as: CN115552596A

Abstract

Embodiments of the present application relates to microelectronic technology. Disclosed are an LGA pad structure, a manufacturing method, a chip module, a printed circuit board, and a device. The LGA pad structure comprises one or more signal portions, a grounding portion, and a solder mask portion; the one or more signal portions are used for transmitting a signal between a chip module and a printed circuit board; the grounding portion is used for coating the one or more signal portions; and the solder mask portion is provided between the grounding portion and the one or more signal portions to isolate the grounding portion from the one or more signal portions. According to the embodiments of the present application, electromagnetic interference radiation of a chip can be effectively shielded, the electromagnetic shielding performance is improved, and the product competitiveness is improved.

Description

LGA pad structure and manufacturing method, chip module, printed circuit board and device

technical field

The present application relates to the technical field of microelectronics, and in particular, to an LGA pad structure and a manufacturing method, a chip module, a printed circuit board and a device.

Background technique

System-in-Package (SIP) can integrate active electronic components with different functions plus passive optical components in a single package. For example, integrating chips and component groups and connecting them to a printed circuit board (PCB) through solder layers can solve the problem of limited circuit board layout and wiring for electronic products.

Chip packaging solutions existing in the prior art are Ball Grid Array (BGA) and Land Grid Array (LGA). The BGA connects the chip pins to the PCB through the solder balls at the bottom of the printed circuit board, and the LGA connects the chip pins to the contacts mounted to the PCB through the pads at the bottom of the printed circuit board. In the above implementation scheme, if the working current of the chip is relatively large, the soldering layer of the chip may cause electromagnetic interference (Electromagnetic Interference, EMI) leakage, and the electromagnetic shielding performance is poor.

SUMMARY OF THE INVENTION

The embodiments of the present application provide an LGA pad structure and a manufacturing method, a chip module, a printed circuit board and a device. The embodiments of the present application can effectively suppress electromagnetic interference in system-level packaging, improve electromagnetic shielding performance, and enhance product competition. force.

In a first aspect, embodiments of the present application provide a grid array package LGA pad structure for electrically connecting a chip module and a printed circuit board, the LGA pad structure comprising: one or more signal parts, a ground part, and a solder resist part; the one or more signal parts are used to transmit signals between the chip module and the printed circuit board; the ground part is used to cover the one or more signal parts; the resistance A soldering portion is disposed between the ground portion and the one or more signal portions to isolate the ground portion from the one or more signal portions.

Based on such a design, through the coaxial structure design of the LGA pad structure, since the ground part can tightly wrap the one or more signal parts, and the solder mask part can isolate the ground part from the one or more signal parts The signal part and the ground part can effectively shield the electromagnetic interference radiation of the first or more signal parts, improve the electromagnetic shielding performance and enhance the competitiveness of products.

In a possible design, the one or more signal parts include one or more first signal parts, and the one or more first signal parts are used to transmit the communication between the chip and the printed circuit board first signal. Based on such a design, the use of the coaxially designed LGA pad structure can perform EMI shielding on the first signals of one or more first signal parts, thereby improving the shielding performance.

In a possible design, the one or more signal parts include one or more second signal parts, and the one or more second signal parts are used to transmit the communication between the chip and the printed circuit board. The second signal, the anti-interference ability of the second signal is weaker than the anti-interference ability of the first signal. Based on such a design, the use of the coaxially designed LGA pad structure can perform EMI shielding on the second signals of one or more second signal parts, thereby improving the shielding performance.

In a possible design, the solder resist portion is further disposed between two signal portions of the one or more signal portions to surround the two signal portions. Based on such a design, since the solder resist portion is provided between two signal portions of the one or more signal portions, interference of one signal portion of the two signal portions by the other signal portion can be avoided.

In a possible design, the two signal portions include a first signal portion and a second signal portion, and the solder resist portion surrounding the first signal portion and the solder mask surrounding the second signal portion The solder resist portion is isolated by the ground portion.

In a possible design, the pad structure is a single pad structure formed by an LGA process. In a second aspect, embodiments of the present application further provide a chip module, the chip module includes one or more chips and one or more LGA pad structures as described above; the one or more chips pass through the The one or more LGA pad structures are electrically connected to the printed circuit board.

Based on such a design, through the coaxial structure design of the LGA pad structure, the grounding portion can effectively shield the electromagnetic interference radiation of the first or more signal portions, thereby improving the electromagnetic shielding performance.

In one possible design, the one or more chips have a one-to-one correspondence with the one or more LGA pad structures.

In a third aspect, embodiments of the present application further provide a printed circuit board, the printed circuit board includes one or more LGA pad structures as described above, and the printed circuit board passes through the one or more LGA pad structures The pad structure is electrically connected to the chip module.

In a fourth aspect, embodiments of the present application further provide a signal device, wherein the signal device includes the above-mentioned chip module and the above-mentioned printed circuit board, and the printed circuit board is electrically connected to the chip module.

In a fifth aspect, embodiments of the present application further provide a method for fabricating an LGA pad structure, including the following steps: providing a substrate; generating a solder resist portion on the substrate; A plurality of signal parts and ground parts; wherein, the one or more signal parts are used to transmit signals between the chip module and the printed circuit board, and the ground parts are used to cover the one or more signal parts , the solder resist portion is located between the ground portion and the one or more signal portions to isolate the ground portion from the one or more signal portions.

The LGA pad structure and the manufacturing method, the chip module, the printed circuit board and the signal device provided by the embodiments of the present application are designed through the coaxial structure of the LGA pad structure, since the ground portion can tightly wrap the one or more signals part, and the solder mask part can isolate the ground part from the one or more signal parts, and the ground part can effectively shield the electromagnetic interference radiation of the first or more signal parts The embodiments of the present application can effectively suppress The electromagnetic interference in the system-in-package improves the electromagnetic shielding performance and enhances the product competitiveness.

Description of drawings

FIG. 1 is a schematic structural diagram of a system-in-package module according to an embodiment of the present application.

FIG. 2 is another schematic structural diagram of a system-in-package module according to an embodiment of the present application.

FIG. 3 is an application environment diagram of a system-in-package module according to an embodiment of the present application.

FIG. 4 is a schematic structural diagram of a signal device according to an embodiment of the present application.

FIG. 5 is a specific application scenario diagram of the system level packaging module according to the embodiment of the present application.

FIG. 6 is a schematic structural diagram of an LGA pad structure according to an embodiment of the present application.

FIG. 7 is a specific application scenario diagram of the LGA pad structure of the embodiment of the present application.

FIG. 8 is another structural schematic diagram of the LGA pad structure according to an embodiment of the present application.

FIG. 9 is another schematic structural diagram of the LGA pad structure according to an embodiment of the present application.

FIG. 10 is a flowchart of a method for fabricating an LGA pad structure according to an embodiment of the present application.

FIG. 11 is another flowchart of a method for fabricating an LGA pad structure according to an embodiment of the present application.

Description of main component symbols

System-in-package module 100

External device 200

Chip module 10

Chip 101, 11

Component group

102, 15

Plastic layer

103, 13

Shield 104

LGA pad structure 105

Regular pad 106

Ground part 107

Solder mask 108

Power Signal Section 109

Sensitive signal part 110

Welding layer 12

Sputter coating 14

Printed

circuit board

16, 20

Signal pad 17

Ground Pad 18

Shield 21

The following specific embodiments will further describe the present application in detail with reference to the above drawings.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments.

In the embodiments of this application, words such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. For example, the first application, the second application, etc. are used to distinguish different applications, rather than to describe the specific order of the applications, and the features defined with "first" and "second" may expressly or implicitly include one or more of this feature.

In the description of the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, illustration or illustration. Any embodiment or design described in the embodiments herein as "exemplary" or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present the related concepts in a specific manner.

With the rapid development of the electronic industry, electronic products are required to be smaller, lighter, and more functionally diverse according to the needs of users. As an assembly technique to meet this demand, homogeneous or heterogeneous integrated circuit (IC) chips are integrated into a single unit module. One such packaging technology that fits this trend is System In Package (SIP). In a system-in-package module, individual devices with different functions are mounted in a single package to utilize a given space, enabling miniaturization. In some possible scenarios, the system-in-package module may generate electromagnetic interference (Electromagnetic Interference, EMI) leakage, and the electromagnetic shielding performance is poor.

In order to deal with the above-mentioned EMI leakage situation, in a possible implementation manner, as shown in FIG. 1 , a system-in-package module 100 may cover the top surface of the chip 11 with a plastic encapsulation layer 13 , and the chip 11 passes the The solder layer 12 is interconnected with the printed circuit board 16, and a shielding cover 21 is provided outside the chip 11 to connect both ends of the shielding cover 21 to the printed circuit board 16, that is, the shielding cover completely covers the chip 11, Therefore, the electromagnetic interference of the system-in-package module 100 can be shielded, and the electromagnetic interference shielding performance of the system-in-package module 100 can be improved. In this implementation manner, the soldering layer 12 may be a Grid Array (Land Grid Array, LGA) layer.

In the above implementation manner, based on the reliability requirements of the system-in-package module 100, a certain gap needs to exist between the shield 21 and the chip 11 in both the vertical direction and the horizontal direction. In addition, the shielding cover 21 needs to have pads on the surface of the printed circuit board 16, and the shielding cover 21 also needs to add spacers inside as a support, which will increase the height and area occupied by the shielding cover 21. This will increase the volume of the system-in-package module 100 and reduce product competitiveness.

In another possible implementation manner of the present application, as shown in FIG. 2 , the system-in-package module 100 may be connected to the printed circuit board 16 through the soldering layer 12 . For example, the chip 11 may be mounted on the printed circuit board 16 by a ball array packaging method or a grid array packaging method. A component group 15 is integrated on the upper surface of the chip 11 , and the sputtering coating 14 can shield the external radiation of the printed circuit board 16 . The plastic sealing layer 13 can wrap the upper surface of the chip 11 and the component group 15 . In this implementation manner, the soldering layer 12 may be an LGA layer.

A shielding structure is formed by sputtering metal coatings on the side and upper surfaces of the chip 11 and the plastic encapsulation layer 13. Based on such a design, the purpose of shielding electromagnetic interference can be achieved. Compared with the implementation in FIG. 1 in which the shielding cover 21 is provided outside the chip 11 , the implementation in FIG. 2 has advantages in height and area. In the above implementation manner, the soldering layer 12 is exposed on the outside of the shielding structure, which will lead to the leakage of EMI radiation of the soldering layer 12 and become the bottleneck of the shielding performance of the sputtering coating scheme.

In another possible implementation manner of the present application, in order to reduce the risk of EMI leakage from the solder layer of the above-mentioned sputtering coating scheme, a ground pad 18 may be added around the outer periphery of the signal pad 17, thereby realizing electromagnetic shielding function. Specifically, as shown in FIG. 3 , it is a part of a top view of a system-in-package module. According to the above-described embodiment of the present application, the plurality of ground pads 18 form a Faraday cage around the signal pad 17 . Such a Faraday cage can prevent electromagnetic waves generated by the signal pads 17 from being radiated to the outside. In addition, the Faraday cage can prevent external electromagnetic waves from entering and interfering with the signal pads 17 . It can be understood that "Faraday cage" can refer to a cage formed by a good conductor such as metal. The cage body is grounded, which can effectively realize the function of electromagnetic shielding and prevent electromagnetic radiation from entering or radiating to the outside.

In the above implementation manner, adding a circle of grounding pads 18 outside the soldering layer needs to occupy a large amount of grid array packaging resources, and the signal pads 17 account for a small proportion. If the chip has many signals and the pad resources are tight, it may be necessary to expand the chip area to obtain enough pads to cover the ground. Taking the 9 pads shown in FIG. 3 as an example, if the chip has multiple signals that need to be connected to the printed circuit board 16 through the grid array packaging layer, and the chip area is the same as the area of the 9 pads, the chip can only be enlarged. area to increase the pad, which will undoubtedly affect the area gain of the system-in-package module. In addition, there is still a certain gap between the bonding pads of the grid array packaging layer. Therefore, in the above-mentioned implementation manner, the shielding performance is limited.

It can be understood that in the above several implementation manners, the LGA layer of the system-in-package module has a risk of EMI radiation leakage, and the above-mentioned ground wrapping scheme will affect the area benefit of the system-in-package module, and the shielding performance is limited. To this end, the embodiments of the present application provide an LGA pad structure and a processing method, a chip, a printed circuit board, and a signal device. The embodiments of the present application can effectively suppress electromagnetic interference in system-level packaging and improve electromagnetic shielding performance. Improve product competitiveness.

Please refer to FIG. 4 , which is a schematic diagram of a signal device 100 according to an embodiment of the present application. The signal device 100 in the embodiment of the present application may establish an electrical connection with the external device 200 . For example, the signaling device 100 may transmit a signal to the external device 200 , or the signaling device 100 may receive a signal from the external device 200 .

It can be understood that, in an implementation manner, the signal device 100 may include a chip module 10 and a printed circuit board 20 . The chip module 10 may be electrically connected to the printed circuit board 20 , and the printed circuit board 20 may be electrically connected to an external device 200 . Based on such a design, the chip module 10 can establish a connection with the external device 200 through the printed circuit board 20. For example, the chip module 10 may send a signal to the external device 200 or receive a signal from the external device 200 , thereby realizing signal transmission between the chip module 10 and the external device 200 .

As shown in FIG. 5 , it is a schematic diagram of a specific application scenario of the system-in-package module 300 according to the embodiment of the present application. Embodiments of the present application provide a system-in-package module 300 , and the system-in-package module 300 may include a chip module 10 and a printed circuit board 20 . In a possible scenario, the chip module 10 may be disposed on the upper surface of the printed circuit board 20 . It can be understood that the chip module 10 is, for example, a high-performance integrated circuit module including one or more chips 101 and possibly passive components. The system-in-package module 300 of the present application can be assembled into a functional system in a single package.

PCBs may include rigid PCB materials (such as glass-filled epoxy), flexible printed circuits (eg, printed circuits formed from flexible polymer sheets such as polyimide), or rigid flexible circuits (eg, including rigid sections and flex leads for both printed circuits). A PCB on which components such as integrated circuit components and discrete components are mounted may sometimes be referred to as a Main Logic Board (MLB). Components can be mounted on the PCB using soldering or other suitable mounting schemes. For example, the component may be a surface mount technology (SMT) component that is mounted directly to the PCB. System-in-package can achieve higher volume efficiency, superior reliability and higher performance.

The chip module 10 may include one or more chips 101 and component groups 102 . It can be understood that, in the embodiments of the present application, one chip 101 is used as an example for description. The component group 102 is integrated on the upper surface of the chip 101 . In a possible situation, the upper surface of the chip 101 and the outer side of the component group 102 are both wrapped with a plastic encapsulation layer 103 .

It can be understood that the plastic encapsulation layer 103 may be a filler, and the plastic encapsulation layer 103 may be used to encapsulate and encapsulate the chip 101 and the component group 102 . The plastic sealing layer 103 in this embodiment may cover the chip module 10 . Optionally, the plastic encapsulation layer 103 may be made of insulating material. As an example, the molding layer 103 may be formed by a filling process or a liquid sealing molding process.

Optionally, in this embodiment, the plastic sealing layer 103 can be formed by a filling process, and the plastic sealing layer 103 can smoothly and quickly fill the gap between the upper surface of the chip 101 and the component group 102 , the stress reliability of the chip 101 and the component group 102 can be guaranteed. Optionally, in one or more embodiments of the present application, the plastic encapsulation layer 103 covering the chip module 10 may have a first width, wherein the first width may be greater than or equal to 50 microns.

It can be understood that the component group 102 can be used to implement the function of a system-in-package. Optionally, in this embodiment, the component group 102 may include devices such as resistors, capacitors, and inductors. In other possible implementation manners, the component group 102 may also include other electronic devices, which are not limited in this application.

In this embodiment, a package body may be formed on the opposite outer side of the chip module 10 to encapsulate the chip module 10 on the printed circuit board 20 . In various embodiments of the present application, the package body may include a shielding layer 104 to implement shielding and encapsulation of the chip module 10 mounted on the printed circuit board 20 , and the shielding layer 104 may be provided where the shielding and encapsulation needs to be performed. The outer surface of the plastic encapsulation layer 103 on the chip module 10 . Further, in order to improve the shielding effect, in the embodiment of the present application, the shielding layer 104 is provided on the outer surface of the plastic sealing layer 103 on the chip module 10 and on both sides of the chip 101 .

In the technical solution of the present application, the metal sputtered shielding layer 104 and the outer surface of the plastic sealing layer 103 are bonded together, so that there is no gap between the shielding layer 104 and the plastic sealing layer 103 . Optionally, in one or more possible embodiments of the present application, the thickness of the shielding layer 104 may be between 2 microns and 10 microns. In this way, the shielding layer 104 can better cover the outer surface of the plastic encapsulation layer 103 and the side surface of the chip 101 , so that the electronic components in the encapsulation area can be well shielded without any influence on the non-encapsulation area. .

It can be understood that, in one usage scenario, the chip 101 is provided with one or more LGA pad structures 105 near the lower surface of the printed circuit board 20 . One or more pins of the chip 101 may be electrically connected to one or more LGA pad structures 105 correspondingly. One or more LGA pad structures 105 are disposed on the upper surface of the printed circuit board 20 close to the chip 101 . The pad structure 105 of the printed circuit board 20 and the pad structure 105 of the chip 101 can be coupled together to realize signal communication. In fact, when the chip 101 is disposed on the printed circuit board 20 , the pad structures 105 of the two can be integrated, that is, a complete pad structure 105 . Soldering technology may be used to couple the chip 101 and the printed circuit board 20, which is not limited in this embodiment.

In one embodiment, the number of the LGA pad structures 105 of the printed circuit board 20 is the same as the number of the LGA pad structures 105 of the chip 101 and is in one-to-one correspondence. The LGA pad structure 105 of the printed circuit board 20 may be electrically connected to the LGA pad structure 105 of the chip 101 . It can be understood that the LGA pad structures 105 and the LGA pad structures 105 shown in FIG. 5 are described by taking five as an example. In some other possible embodiments, the LGA pad structures 105 and the number of the LGA pad structures 105 can be adjusted according to actual needs, which are not limited in this application.

It can be understood that the LGA pad structure 105 may be a single pad structure formed by using an LGA process.

Referring to FIG. 6 , the following will illustrate the LGA pad structure 105 provided by the embodiments of the present application with reference to the accompanying drawings and practical application scenarios. It can be understood that, in the embodiment of the present application, the LGA pad structure 105 of the printed circuit board 20 and the LGA pad structure 105 of the chip 101 have the same structure. FIG. 6 is a schematic cross-sectional view (top view) of the LGA pad structure 105 according to an embodiment of the present application. The LGA pad structure 105 in this embodiment is an LGA coaxial structure, with reference to FIG. 7 for details. The LGA pad structure 105 may include one or more signal portions. The one or more signal portions may include a power signal portion 109 . Furthermore, the LGA pad structure 105 may further include a ground portion 107 and a solder resist portion 108 . It can be understood that a power signal part 109 is shown in FIG. 6 as an example for illustration.

Specifically, the solder resist portion 108 is wrapped around the power signal portion 109 , and the solder resist portion 108 is provided between the power signal portion 109 and the ground portion 107 to isolate the ground portion 107 with the power signal section 109.

Wherein, the power signal part 109 provides an interconnection path for signal transmission between the chip 101 and the printed circuit board 20 . Based on such a design, the chip 101 can transmit signals to the printed circuit board 20 through the power signal part 109 in the LGA pad structure 105 , or the chip 101 can pass the power signal part 109 in the LGA pad structure 105 After receiving the signal of the printed circuit board 20, the signal transmission is more convenient and simple.

It can be understood that the solder resist portion 108 in this embodiment is located between the power signal portion 109 and the ground portion 107. Based on such a design, the solder resist portion 108 can prevent the power signal portion 109 from being grounded by the ground The portion 107 is short-circuited, thereby effectively protecting the power signal portion 109 . In one usage scenario, the ground portion 107 may be used to shield the EMI radiation of the power signal portion 109 .

It can be understood that in the coaxial structure design of the LGA pad structure 105 , the ground portion 107 can tightly wrap the power signal portion 109 and the solder resist portion 108 . Based on such a design, in the LGA pad structure 105 , there will not be any gap between the ground portion 107 and the power signal portion 109 . Furthermore, the grounding portion 107 can effectively shield the EMI radiation of the power signal of the power signal portion 109 . Therefore, by adopting the coaxial structure design of the LGA pad structure 105 , an efficient shielding function can be realized for the power signal of the power signal part 109 of the chip 101 or all signals, so as to avoid EMI radiation leakage.

In another possible scenario, when the power signal of the chip 101 is less, that is, the radiation source of the chip 101, as shown in FIG. 7, the embodiment of the present application may adopt the LGA pad structure 105 of the coaxial structure The power signal of the chip 101 is transmitted, and other signals can be transmitted through the conventional pads 106 . It can be understood that, in the application scenario shown in FIG. 7 , the power signal may be a high-current signal of the chip 101 , and the other signals may be low-current signals. With the above design, the number of ground pads can be reduced, thereby increasing the area gain of the system-in-package module. In addition, the present embodiment can also eliminate the gap between the ground pads and improve the shielding performance of the product.

Please refer to FIG. 8 , which is a schematic structural diagram of the LGA pad structure 105 according to another embodiment of the present application. The difference from the embodiment of the LGA pad structure 105 shown in FIG. 6 is that, as shown in FIG. 8 , the LGA pad structure 105 in this embodiment may include a plurality of power signal portions 109 . The LGA pad structure 105 can use one grounding part 107 to shield the EMI leakage of the multiple power signal parts 109, and the shielding efficiency is higher.

It can be understood that four power signal parts 109 are shown in FIG. 8 as an example for description. For example, in this embodiment of the present application, one grounding portion 107 may be used to shield the EMI radiation of the four power signal portions 109 at the same time. In the application scenario shown in FIG. 8 , the solder resist portions 108 are wrapped around the plurality of power signal portions 109 , and the plurality of power signal portions 109 are arranged at intervals, and between every two power signal portions 109 The solder resist portion 108 is provided with the solder resist portion 108 , and the ground portion 107 is wrapped around the solder resist portion 108 . Based on such a design, the grounding portion 107 can effectively shield the EMI radiation of multiple power signals, and the solder resist portion 108 can effectively ensure that the multiple power signal portions 109 are not short-circuited by the grounding portion 107 . Thus, the LGA pad structure 105 in this embodiment can implement an efficient shielding design by using the coaxial architecture for power signals or all signals.

In a possible application scenario, the chip 101 may also include power signals and sensitive signals. For example, a radio frequency chip may include both uplink signals and downlink signals, and the uplink signals and downlink signals may be collectively referred to as sensitive signals. It can be understood that, in some possible implementations, the power of the power signal may be greater than the power of the sensitive signal. To this end, the LGA pad structures 105 provided by other embodiments of the present application can also effectively protect sensitive signals from interference by power signals.

Please refer to FIG. 9 , which is a schematic structural diagram of the LGA pad structure 105 according to another embodiment of the present application. The difference from the embodiment of the LGA pad structure 105 shown in FIG. 6 is that, as shown in FIG. 9 , the LGA pad structure 105 in this embodiment may include one or more sensitive signal portions 110 and one or more Power signal section 109.

In the embodiment of the present application, multiple signals of the chip 101 may also be isolated by the grounding portion 107 . It can be understood that the application scenario of FIG. 9 shows one sensitive signal part 110 and five power signal parts 109 as an example for description. In this embodiment, the sensitive signal part 110 may be arranged at intervals from the above-mentioned five power signal parts 109 , and every two power signal parts 109 are also arranged at intervals. That is, there is a gap between the sensitive signal part 110 and the five power signal parts 109 , and there is a gap between each power signal part 109 .

In the scenario shown in FIG. 9 , the solder resist portion 108 is further disposed between the power signal portion 109 and the sensitive signal portion 110 to surround the power signal portion 109 and the sensitive signal portion 110 . The sensitive signal portion 110 and the five power signal portions 109 are all wrapped with the solder resist portion 108 . , the solder resist portion 108 is wrapped with the ground portion 107 . Furthermore, the solder resist portion 108 surrounding the power signal portion 109 and the solder resist portion 108 surrounding the sensitive signal portion 110 may be isolated by the ground portion 107 .

It can be understood that the power signal part 109 in this embodiment provides an interconnection path for power signal transmission between the chip 101 and the printed circuit board 20 . The sensitive signal portion 110 provides interconnection paths for sensitive signal transmission between the chip 101 and the printed circuit board 20 . The ground portion 107 can effectively shield the EMI radiation of the power signal. It can be understood that the power signal is a large current signal, and the sensitive signal is a small current signal. It can be understood that, in some possible scenarios, the anti-interference ability of the sensitive signal is weaker than that of the power signal. In some scenarios, the sensitive signal is susceptible to interference by the power signal. Thus, the ground portion 107 can also protect sensitive signals from EMI interference of power signals. It can be understood that the solder resist portion 108 can effectively ensure that the power signal portion 109 and the sensitive signal portion 110 are not short-circuited. Based on such a design, the embodiment of the present application can isolate the power signal and the sensitive signal of the chip 101, thereby protecting the sensitive signal from EMI interference of the power signal.

Please refer to FIG. 10 , which is a flowchart of a method for fabricating an LGA pad structure provided by an embodiment of the present application. The method can fabricate an LGA pad structure on a chip module, and a flowchart of a method for fabricating the LGA pad structure The following steps may be included: Step S101 : providing a substrate. Step S102 : forming a soldering copper layer on the substrate. For example, in this embodiment, a solder pattern can be formed by brushing a layer of copper on the bottom layer of the substrate, etching off the excess portion, and then adding a solder resist layer and curing it. Step S103 : a solder resist portion is formed, and based on the solder resist portion, an LGA process is used to generate one or more signal portions and a ground portion.

It can be understood that in the embodiments of the present application, the solder resist portion 108 can be formed on the substrate, and based on the solder resist portion 108 , one or more signal portions 109 and the ground portion 107 can be generated by using an LGA process, wherein the solder resist portion 108 May be located between ground portion 107 and one or more signal portions 109 .

Please refer to FIG. 11 , which is a flowchart of a method for fabricating an LGA pad structure provided by an embodiment of the present application. The method can fabricate an LGA pad structure on a PCB, and the flowchart of the method for fabricating the LGA pad structure can be The following steps are included: Step S111 : providing a PCB. Step S112 : forming a soldered copper layer on the PCB. For example, in this embodiment, a layer of copper can be brushed on the surface of the PCB, the excess part is etched away, and then a solder resist layer is added and cured to form a solder pattern. Step S113 : a solder resist portion is formed, and based on the solder resist portion, an LGA process is used to generate one or more signal portions and a ground portion. It can be understood that in the embodiments of the present application, the soldering portion 108 can be formed on the substrate, and based on the soldering portion 108, one or more signal portions 109 and the ground portion 107 can be generated by an LGA process, wherein the soldering portion 108 can be Located between ground portion 107 and one or more signal portions 109 . Further, step S114 is performed, and a layer of solder paste is brushed on the soldering pattern to form a pad.

Using the coaxial structure design of the LGA pad structure 105 in the embodiment of the present application, since the ground portion 107 can tightly wrap the power signal portion 109 and the solder resist portion 108, the ground portion 107 can effectively shield the The EMI radiation of the power signal of the power signal part 109 improves the electromagnetic shielding performance and enhances the product competitiveness. In the above method, since the solder resist portion is formed in step S113, referring to the structure of FIG. 7 in detail, when one or more signal portions 109 and the ground portion 107 are generated by the LGA process in S114, metal, such as copper, can be directly used, One or more signal portions 109 and ground portions 107 are formed, and due to the presence of the solder resist portion 108 , the portion will not form metal, thereby isolating one or more signal portions 109 and ground portions 107 .

In the above two method flows, the pad structure is a single pad structure formed by the LGA process, that is, it is not necessary to form a solder resist portion surrounding one or more signal portions 109 by combining a plurality of different pads, Instead, the solder mask part is realized through a single process, and the formed product is small in size, low in cost, and simple in implementation.

Those of ordinary skill in the art should realize that the above embodiments are only used to illustrate the present application, rather than being used to limit the present application, as long as the above embodiments are appropriately made within the spirit and scope of the present application Variations and variations are within the scope of the claims of this application.

Claims

A grid array package LGA pad structure for electrically connecting a chip module and a printed circuit board, wherein the LGA pad structure comprises: one or more signal parts, a ground part and a solder resist part;

the one or more signal sections are used to transmit signals between the chip module and the printed circuit board;

the ground portion is used to encapsulate the one or more signal portions;

The solder resist portion is disposed between the ground portion and the one or more signal portions to isolate the ground portion from the one or more signal portions.
The LGA pad structure of claim 1, wherein,

The one or more signal portions include one or more first signal portions for communicating a first signal between the chip and the printed circuit board.
The LGA pad structure of claim 2, wherein,

The one or more signal sections include one or more second signal sections for transmitting second signals between the chip and the printed circuit board, the second signal sections The anti-interference ability of the signal is weaker than that of the first signal.
The LGA pad structure according to any one of claims 1-3, wherein,

The solder resist portion is also disposed between two of the one or more signal portions to surround the two signal portions.
The LGA pad structure of claim 4, wherein,

The two signal portions include a first signal portion and a second signal portion, and the solder resist portion surrounding the first signal portion and the solder resist portion surrounding the second signal portion are connected by the ground portion. isolation.
The LGA pad structure according to any one of claims 1-5, wherein,

The pad structure is a single pad structure formed by the LGA process.
A chip module, characterized in that the chip module comprises one or more chips and one or more LGA pad structures according to any one of claims 1-6; the one or more chips pass through the The one or more LGA pad structures are electrically connected to the printed circuit board.
The chip module according to claim 7, wherein,

The one or more chips are in one-to-one correspondence with the one or more LGA pad structures.
A printed circuit board, characterized in that the printed circuit board comprises one or more LGA pad structures according to any one of claims 1-6, and the printed circuit board passes through the one or more LGA pad structures The pad structure is electrically connected to the chip module.
A signal device, characterized in that the signal device comprises the chip module as claimed in claim 7 or 8 and the printed circuit board as claimed in claim 9 , the printed circuit board is electrically connected to the chip module.
A method for making an LGA pad structure, characterized in that,

providing a substrate;

generating a solder resist portion on the substrate;

Based on the solder mask portion, one or more signal portions and a ground portion are generated using an LGA process;

Wherein, the one or more signal parts are used to transmit signals between the chip module and the printed circuit board, the ground part is used to cover the one or more signal parts, and the solder resist part is located in the between the ground portion and the one or more signal portions to isolate the ground portion from the one or more signal portions.