WO2022206397A1 - Buffering method and integrated circuit - Google Patents

Abstract

Provided in the present application are a buffering method and an integrated circuit, which can avoid a false hit. The buffering method comprises: acquiring a first packet, wherein the first packet comprises a destination internet protocol (IP) address; searching a buffer for a routing prefix that matches the destination IP address; in response to the fact that the routing prefix is not stored in the buffer, searching, according to the destination IP address, for a tree structure corresponding to a routing table, and determining a prefix node that matches the destination IP address; in response to the fact that the prefix node is not a leaf node, a processor determining a first prefix match length, wherein the first prefix match length is equal to the length between a root node and a tail node of the tree structure; determining a first routing prefix according to the first prefix match length and the destination IP address; and triggering the buffer to store a first correspondence, wherein the first correspondence is a correspondence between the first routing prefix and routing information that corresponds to the prefix node.

Description

A cache method and integrated circuit

This application claims the priority of the Chinese patent application with the application number 202110361730.4 and the application title "A Cache Method and Integrated Circuit" filed on April 2, 2021, the entire contents of which are incorporated into this application by reference.

technical field

The present application relates to the field of communication technologies, and in particular, to a caching method and an integrated circuit.

Background technique

When forwarding packets, network devices such as routers or switches can obtain the destination Internet Protocol (Internet Protocol, IP) address carried in the packet, and look up the routing information corresponding to the destination IP address from the routing table. routing information to forward packets. The routing table is an entry that records routing prefixes and routing information, and is pre-stored in the network device. The routing prefix is used to determine routing information matching the destination IP address, for example, it can be the first n bits of the IP address, and n is the length of the routing prefix. The routing information may be an identifier of a network interface, indicating the network interface through which the network device needs to forward the packet.

When looking up the routing table, determine whether the destination IP address matches the routing prefix. For example, assuming that the length of a routing prefix is m, and the first m bits of the destination IP address are consistent with the routing prefix, it can be considered that the destination IP address matches the routing prefix, and the corresponding routing information is the routing prefix. routing information. When the destination IP address matches two or more routing prefixes at the same time, the routing prefix can be determined according to the Longest Prefix Match (LPM) principle. That is, the routing information of the routing prefix with the longest length among the multiple routing prefixes matching the destination IP address may be used as the routing information corresponding to the destination IP address.

Since looking up the routing table needs to compare whether the routing prefix matches the destination IP address, the network device needs to look up the routing table. Obviously, the faster the routing table is called, the faster the network device can forward packets. At present, in order to improve the speed at which the network device calls the routing table, the corresponding relationship between some routing prefixes and routing information may be stored in the cache. But this method often suffers from false hits.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a caching method and an integrated circuit, which avoid false hits by recording the correspondence between the first routing prefix and routing information whose length is greater than that in the routing table and the destination IP address.

In a first aspect, an embodiment of the present application provides a caching method, which can be applied to a processor in a network device. When executing the caching method, the processor may first obtain the first packet, and determine the destination IP address carried in the first packet. Next, the processor can look up a routing prefix that matches the destination IP address from the cache. If there is no routing prefix matching the destination IP address stored in the cache, the processor can look up the tree structure corresponding to the routing table from other memories according to the destination IP address, so as to determine the prefix node in the tree structure that matches the destination IP address, That is, the node in the tree structure corresponding to the routing table with the routing prefix matching the destination IP address. When the prefix node is not a leaf node in the tree structure, that is, when the prefix node has child nodes, the processor may determine the length from the root node to the tail node of the tree structure as the first prefix matching length. The tail node is the last node on the search path in the tree structure. The search path is a path from the root node along the tree structure corresponding to the destination IP address in the tree structure corresponding to the routing table to the leaf node in the tree structure corresponding to the routing table. After obtaining the first prefix matching length, the processor may determine the first routing prefix according to the destination IP address and the first prefix matching length, and trigger the cache to store the first correspondence. The corresponding relationship is the corresponding relationship between the first routing prefix and the routing information corresponding to the prefix node. That is to say, when the prefix node is not a leaf node, the routing prefix in the corresponding relationship is different from the routing prefix recorded in the routing table. That is, when there are other routing prefixes including and longer than the routing prefix corresponding to the destination IP address in the routing table, the processor may determine a new first routing prefix according to the matching length of the first prefix, and store the new routing prefix in the cache The correspondence between prefixes and routing information. In this way, the length of the first routing prefix may be greater than the length of the routing prefix matching the destination IP address in the memory routing table. In this way, compared with the prior art, it can play a role in reducing the probability of false hits.

In a possible implementation, the length of the first routing prefix may be greater than the first prefix matching length. It is easy to understand that the longer the length of the first routing prefix, the smaller the probability of false hits. When the length of the first routing prefix is greater than the first prefix matching length, the probability of false hits is 0.

In a possible implementation, when the destination IP address is a leaf node in the tree structure corresponding to the routing table, the length of the first routing prefix may be equal to the matching length of the first prefix.

In a possible implementation, the tree structure corresponding to the routing table may be divided into a virtual tree structure and multiple sub-tree structures. The processor can determine the prefix node matching the destination IP address through the virtual tree structure and the subtree structure. The virtual tree structure may include any number of nodes in the tree structure corresponding to the routing table, and the root node of each sub-tree structure in the multiple sub-tree structures corresponds to a node in the virtual tree structure respectively. Specifically, the processor may first look up the virtual tree structure corresponding to the routing table according to the destination IP address, and determine the virtual prefix that matches the destination IP address the longest. Next, the processor may determine, according to the virtual prefix, that the routing prefix corresponding to the root node is a subtree structure of the virtual prefix, and search for a prefix node matching the destination IP address from the subtree structure. Then, assuming that the first length is the length from the root node of the virtual book structure to the virtual prefix, and the second length is the length of the tail node on the search path from the virtual prefix to the subtree structure, then the sum of the first length and the second length is the aforementioned The first prefix matches the length. In this way, dividing the tree structure corresponding to the routing table into a virtual tree structure and a plurality of subtrees can improve the search efficiency of routing prefixes.

In some possible implementations, the processor may also store the correspondence between the second routing prefix and the routing information. The nodier routing prefix is the routing prefix corresponding to the only-child node on the forwarding path, and the only-child node is a child node with only a left child node or a right child node. Specifically, when the prefix node matching the destination IP address is not a leaf node, the processor may determine the only child node on the forwarding path according to the forwarding path of the destination IP address, and determine the second prefix matching length according to the stomach node. The second prefix matching length is equal to the length from the root node to the only child node. After determining the second prefix matching length, the processor may determine the second routing prefix according to the second prefix matching length, so as to store the second correspondence.

In some possible implementations, the processor may further trigger the cache to store the type of the first routing prefix. Then after the processor receives other packets, if the destination IP address of the packet hits the first routing prefix, the processor can obtain the first routing prefix from the cache according to the first corresponding relationship according to the indication of the type of the first routing prefix. The routing information corresponding to the prefix.

In some possible implementations, when the processor determines the prefix node through the virtual tree structure and the subtree structure, the processor may trigger the cache to store a third correspondence relationship, where the third correspondence relationship is the virtual prefix, the type of the virtual prefix, and the subtree structure. Correspondence between information. Similarly, if the destination IP address of the packet hits the virtual prefix, the processor may search the subtree structure from the information of the subtree structure according to the indication of the type of the virtual prefix, so as to determine the routing information corresponding to the first routing prefix.

In some possible implementations, considering the maximum length matching principle, the processor may further trigger the cache to store the length of the first routing prefix.

In some possible implementations, the length of the first routing prefix is equal to the first prefix matching length plus one.

In some possible implementations, the length of the first routing prefix is less than the length of the destination IP address.

In some possible implementations, the destination IP address includes the first routing prefix.

In some possible implementations, the cache includes at least one of the following: a ternary content addressable memory (Ternary Content Addressable Memory, TCAM), a register, a line card board, and a die.

In a second aspect, an embodiment of the present application provides an integrated circuit, which is applied to a processor and includes an interface circuit and a control circuit; wherein the interface circuit is used to acquire a first message, the first The message includes a destination Internet Protocol IP address; the control circuit is configured to look up a routing prefix matching the destination IP address from the cache; in response to that the routing prefix is not stored in the cache, according to the destination IP address Look up the tree structure corresponding to the routing table, and determine the prefix node matching the destination IP address; in response to the prefix node not being a leaf node, determine the first prefix matching length, and the first prefix matching length is equal to the tree The length between the root node of the structure and the tail node, where the tail node is the last node on the search path of the tree structure; according to the first prefix matching length and the destination IP address, determine the first routing prefix ; Trigger the cache to store a first correspondence, where the first correspondence is the first routing prefix and routing information corresponding to the prefix node.

In some possible implementations, the length of the first routing prefix is greater than or equal to the first prefix matching length.

In some possible implementations, the control circuit is configured to look up a virtual tree structure corresponding to the routing table according to the destination IP address, and determine the virtual prefix that matches the destination IP address with the longest length; according to the destination IP address Find the subtree structure corresponding to the virtual prefix, and determine the prefix node that matches the destination IP, and the virtual prefix is the root node of the subtree structure; the first prefix matching length is equal to the first length and The sum of the second lengths, the first length is the length from the root node of the virtual tree structure to the virtual prefix, the second length is the length from the virtual prefix to the tail node, the tail node is the last node on the search path of the subtree structure.

In some possible implementations, the control circuit is further configured to, in response to the prefix node not being a leaf node, determine a second prefix matching length, where the second prefix matching length is equal to the root node to the only child of the tree structure The length between nodes, the single-child node is a node with only a left child node or only a right child node between the prefix node and the tail node; match the length and the destination IP according to the second prefix address, determine a second routing prefix, the length of the second routing prefix is greater than the matching length of the second prefix; trigger the cache to store a second correspondence, the second correspondence is the second routing prefix and all The routing information corresponding to the prefix node described above.

In some possible implementations, the control circuit is further configured to trigger the cache to store the type of the first routing prefix, where the type of the first routing prefix is used to indicate when the first routing prefix is hit , and obtain the routing information corresponding to the first routing prefix in the cache according to the first corresponding relationship.

In some possible implementations, the control circuit is further configured to trigger the cache to store a third correspondence relationship, where the third correspondence relationship is the virtual prefix, the type of the virtual prefix, and the subtree structure. The corresponding relationship between the information, the type of the virtual prefix is used to indicate that when the virtual prefix is hit, the sub-tree structure is searched according to the information of the sub-tree structure.

In some possible implementations, the control circuit is further configured to trigger the cache to store the length of the first routing prefix.

In some possible implementations, the length of the first routing prefix is equal to the first prefix matching length plus one.

In some possible implementations, the length of the first routing prefix is less than the length of the destination IP address.

In some possible implementations, the destination IP address includes the first routing prefix.

In some possible implementations, the cache includes at least one of the following: a TCAM, a register, a line card board, and a die.

In a third aspect, an embodiment of the present application provides a cache device, where the cache device includes an acquisition unit and a processing unit. Wherein, the obtaining unit is configured to obtain a first packet, where the first packet includes a destination Internet Protocol IP address. The processing unit is configured to look up a routing prefix matching the destination IP address from the cache; in response to the routing prefix not being stored in the cache, look up a tree structure corresponding to the routing table according to the destination IP address, determining a prefix node matching the destination IP address; in response to the prefix node not being a leaf node, determining a first prefix matching length, where the first prefix matching length is equal to the length between the root node and the tail node of the tree structure The length of the tail node is the last node on the search path of the tree structure; according to the first prefix matching length and the destination IP address, determine the first routing prefix; trigger the cache to store the first corresponding The first corresponding relationship is the first routing prefix and routing information corresponding to the prefix node.

In a fourth aspect, an embodiment of the present application provides a chip, the chip includes a memory and a processor, the memory is used for storing instructions or program codes, and the processor is used for calling and running the instructions or program codes from the memory to execute The caching method according to the aforementioned first aspect.

In a fifth aspect, an embodiment of the present application provides a device, the device includes a processor chip and a memory, the memory is used to store instructions or program codes, and the processor chip is used to call and run the instructions or program codes from the memory , so as to execute the caching method described in the first aspect.

In a sixth aspect, embodiments of the present application provide a computer-readable storage medium, including instructions, programs, or codes, which, when executed on a computer, cause the computer to execute the caching method described in the foregoing first aspect.

Description of drawings

FIG. 1 is a schematic structural diagram of a processor provided by an embodiment of the present application;

2 is a schematic structural diagram of a tree structure corresponding to a routing prefix provided by an embodiment of the present application;

FIG. 3-a is a schematic structural diagram of a network system 300 provided by an embodiment of the present application;

FIG. 3-b is a schematic structural diagram of a network device 350 according to an embodiment of the present application;

FIG. 3-c is another schematic structural diagram of a network device 350 provided by an embodiment of the present application;

FIG. 3-d is another schematic structural diagram of a network device 350 provided by an embodiment of the present application;

FIG. 3-e is a schematic structural diagram of a network device 360 provided by an embodiment of the present application;

FIG. 3-f is a schematic structural diagram of a chip 370 of a network device provided by an embodiment of the present application;

FIG. 3-g is a schematic structural diagram of a virtual router 380 provided by an embodiment of the present application;

4 is a schematic flowchart of a caching method provided by an embodiment of the present application;

5 is a schematic structural diagram of a tree structure corresponding to a routing table provided in an embodiment of the present application;

6 is a schematic structural diagram of a subtree structure provided by an embodiment of the present application;

7 is a schematic structural diagram of a tree structure corresponding to a routing table provided in an embodiment of the present application;

FIG. 8 is a schematic structural diagram of an integrated circuit 800 provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a cache device 900 provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of a chip 1000 provided by an embodiment of the present application;

FIG. 11 is a schematic structural diagram of a device 1100 provided by an embodiment of the present application;

FIG. 12 is a schematic structural diagram of a device 1200 provided by an embodiment of the present application.

Detailed ways

The traditional technology and the caching method provided by the embodiments of the present application will be introduced below with reference to the accompanying drawings.

First, the basic structure of the device including the cache is introduced. Referring to FIG. 1 , the figure is a schematic structural diagram of the device 100 . The device 100 includes a processor 110 and a memory 120 , and the processor 110 includes a processing unit 111 and a cache 112 . The cache 112 can be used to load data from the memory 120, and the processing unit 111 can be used to read data from the cache 112 and process the data. Optionally, when the processor 110 is packaged as a chip, the chip may be referred to as a central processing unit (CPU).

Cache, the full name of the cache (cache), is mostly composed of storage devices with faster data exchange speed. In the embodiments of the present application, the cache may also be referred to as temporary memory (temporary memory) or temporary storage (temporary storage). The cache is respectively connected with the processing unit inside the processor and the memory outside the processor, and can store part or all of the data stored in the memory.

Memory can be divided into external memory and internal memory. External memory is, for example, storage devices such as hard disk drives (HDD), and memory is, for example, synchronous dynamic random-access memory (SDRAM) or double-speed synchronous memory. Dynamic random access memory (Double Data Rate SDRAM, DDR) and other storage devices. The cache is, for example, a storage device such as a static memory (Static Random Access Memory, SRAM). In the process of data exchange with the processor, the data exchange speed of the SRAM is greater than that of the DDR (or SDRAM), and the data exchange speed of the DDR is greater than that of the hard disk. When the network device stores part or all of the routing table through the cache, you can first create a routing table with empty content in the cache. In this embodiment of the present application, the routing table stored in the cache may be referred to as a cache routing table, and the routing table stored in the memory may be referred to as a memory routing table.

When the processor determines that the destination IP address matches a routing prefix in the memory routing table, the processor may store the routing prefix and routing information in the cache routing table. In this way, when the network device receives a new packet and the destination IP address of the new packet matches the routing prefix stored in the cached routing table, the processor can obtain the corresponding routing information from the cached routing table. In this way, since the data exchange speed between the processor and the cache is faster, the search speed of the routing table is improved. When the first n bits of the IP address are respectively consistent with the routing prefix, the IP address can be said to match the routing prefix

Optionally, the cache routing table may include a cache tag (Cache Tag) item and a cache data (Cache Data) item. The cache label item may include a routing prefix, and the cache data item may be used to store routing information. Correspondingly, the corresponding relationship between the cache label item and the cache data item may represent the corresponding relationship between the routing prefix and the routing information.

Considering that the network device needs to determine the route prefix matching the destination IP address according to the longest matching principle, the cache label item may further include the length of the route prefix (length, len for short below). In this way, when the destination IP address matches multiple routing prefixes in the routing table in the cache at the same time, the processor can determine the routing prefix with the longest length as the routing prefix matching the destination IP address.

for example. It is assumed that the network device has network interface A and network interface B, and the memory of the network device records the correspondence between the routing prefix 0001010* and the network interface A, and the correspondence between the routing prefix 0* and the network interface B.

If the network device receives the packet M, and the destination IP address of the packet M is 0001010010100010. The processor of the network device may first look up the routing prefix and routing information matching the destination IP address from the routing table in the memory. After determining that the destination IP address 0001010010100010 matches the routing prefix 0001011*, the processor may store the routing prefix 0001010*, the length of the routing prefix 0001010* and the routing information (ie network interface A) corresponding to the routing prefix 0001010* in the cache routing table middle. The cache routing table may be as shown in Table 1.

Table 1

Cache tag	Cache data
0001010*, len=7	A

Among them, the first row of Table 1 indicates that the routing prefix 000101101* corresponds to network interface A, then the packets whose destination IP address is the first 0 can be forwarded through network interface A. For example, the packets whose destination IP address is 0001010010100010 can be forwarded through network interface A. Network interface A forwards.

If the network device receives packet N again, the destination IP address of packet N is 0001011010010001. Since the first 7 digits of the destination IP address are 0001011, which is inconsistent with the routing prefix 0001010*, the processor of the network device can look up the routing prefix matching the destination IP address 0001011010010001 from the memory routing table. After determining that the destination IP address 0001011010010001 matches the routing prefix 0*, the processor may store the routing prefix 0*, the length of the routing prefix 0*, and the routing information (ie, network interface A) corresponding to the routing prefix 0* in the cache routing table middle. The cache routing table may be as shown in Table 2.

Table 2

Cache tag	Cache data
0001010*, len=7	A
0*, len=1	B

If the network device receives another packet whose destination IP address is 0001011011110100, since the first digit of the destination IP address is consistent with the routing prefix 0*, and the first seven digits of the destination IP address are inconsistent with the routing prefix 0001010*, the processor can It is determined that the packet corresponds to the routing prefix 0*, so that the packet is forwarded through the network interface B. Obviously, since the processor obtains data from the cache faster, storing part or all of the correspondence between routing prefixes and routing information in the cache routing table can improve the packet forwarding speed of the network device.

However, since the information in the cache routing table is gradually increased along with the forwarding of the message, in this process, the cache routing table and the memory routing table are not consistent. Then, if the longer route prefix has not been stored in the cache routing table, and the shorter route prefix has been stored in the cache routing table, the processor may mistakenly assign the shorter route prefix to the cache routing table. The prefix is determined as the routing prefix that matches the packet, so that the packet is forwarded according to the wrong routing information. This situation is called a false hit.

For example, suppose that the destination IP address of a packet matches routing prefix X and routing prefix Y, and routing prefix X has been stored in the cache routing table, but routing prefix Y has not been stored in the cache routing table. If the length of the routing prefix X is shorter than the length of the routing prefix Y, the routing information corresponding to the packet should be the routing information corresponding to the routing prefix Y in theory. However, after receiving the packet, the processor preferentially looks up the routing prefix matching the destination IP address from the cached routing table. Since the cached routing table includes the routing prefix X, the processor may be able to find the routing prefix X that matches the destination IP address from the cached routing table, so as to forward the packet by using the routing information corresponding to the routing prefix X. It can be seen that since the routing prefixes stored in the cache routing table and the storage routing table are different, the network device may have false hits when forwarding packets whose destination IP addresses match multiple routing prefixes.

The description is still made by taking the network device receiving the packet M and the packet N as an example. Assuming that the network device receives the packet N first, the cache routing table can be as shown in Table 3:

table 3

Cache tag		Cache data
0*, len=1	B

If the network device receives the packet M again, since the destination IP address of the packet M is 0001010010100010 and the first bit is 0, which is consistent with the routing prefix 0* recorded in the cache routing table, the processor can consider that the packet M is the same as the route. The prefix 0* matches, so that the packet M is forwarded by the network interface B. Obviously, the network interface actually corresponding to the packet M should be the network interface A. Because the information included in the cache routing table is incomplete, there are cases of false hits.

In order to solve the above problem, an embodiment of the present application provides a caching method, which can record in the cache the correspondence between the first routing prefix whose length is greater than the destination IP address in the routing table and the routing information, thereby avoiding false hits happened.

Below, first briefly introduce the terms involved in this application:

Tree structure: A tree structure is a non-linear data structure. A tree structure can include multiple nodes, and each node can be used to store data. The connection relationship between each node of the tree structure represents the relationship between the data stored by each node, for example, it can represent the sequence relationship or the subordination relationship of the data. The topmost node in the tree structure is called the root node. A tree structure may include multiple sub-tree structures, and each sub-tree structure may include one or more sub-tree structures. The topmost node of each subtree structure may be referred to as the root node of the subtree structure. Typical tree structures may include binary trees, ternary trees, and quad trees.

In this embodiment of the present application, the routing prefix may be represented by a tree structure such as a binary tree, and the specific value of each bit of the routing prefix is represented by the connection relationship between two adjacent layers of nodes in the tree structure. Similarly, routing tables can also be represented by a tree structure with similar rules. For example, each routing prefix in the routing table can be represented by a tree structure, and then the root nodes of these tree structures are superimposed together, and the finally obtained tree structure is the corresponding tree structure of the routing table. In order to distinguish each routing prefix in the routing table, the node corresponding to the last digit of each routing prefix may be marked as a prefix node. The tree structure corresponding to the routing table can be used to express the distribution of prefix nodes in the routing table.

In this embodiment of the present application, the routing prefix and the routing table may be represented by a binary tree, or may be represented by a quad tree or a hexadecimal tree. The following is an introduction to the binary tree. It should be noted that, for ease of understanding, the following description takes the tree structure of the routing table as a binary tree as an example, which does not mean that the tree structure of the routing table in all embodiments of the present application is a binary tree. When the routing prefix is represented by a quad-tree structure, each child node corresponds to two digits in the routing prefix, for example, the four child nodes of the root node can represent "00", "01", "10" and "11" respectively. If the routing table is represented in a tree structure, the tree structure can be split into a virtual tree structure and multiple subtree structures. The introduction of the virtual tree structure can be found below, and will not be repeated here.

Binary tree: A binary tree is an ordered tree in which the degree of nodes in the tree structure is not greater than 2. That is, a binary tree has one root node, and any node in the binary tree has at most two child nodes. When a node has two child nodes, the left child node can be called the left child node, and the right child node can be called the left child node. is the right child node. any node in a binary tree. A binary tree can contain multiple sub-binary trees.

When the routing prefix is represented by a binary tree, starting from the child node of the root node, each IP address corresponds to one level of the binary tree. If a certain bit of the IP address is 0, the binary tree extends to the left at this layer, and if a certain bit of the routing prefix is 1, the binary tree extends to the right at this layer. That is, if the first bit of a routing prefix is 0, then the root node of the binary tree corresponding to the routing prefix has a left child node and no right child node.

For example, the tree structure corresponding to the routing prefix 10010* may be as shown in FIG. 2 . Among them, node 2 is the right child node of root node 1, and the first bit of the connection indicates that the IP address is 1; node 3 is the left child node of node 2, and the second bit of the connection indicates that the IP address is 0; node 4 is node 3 The left child node of the connection indicates that the third bit of the IP address is 0; node 5 is the right child node of node 4, and the fourth bit of the connection indicates that the IP address is 1; node 6 is the left child node of node 5, and the connection indicates IP The fifth bit of the address is 0.

Similarly, when the routing table is represented by a binary tree, the routing table can be as shown in FIG. 5 . This part of the content can be found later, and will not be repeated here.

Only child node: An only child node is a node in a binary tree that has only left child nodes or only right child nodes.

Leaf node: A leaf node is a node in the tree structure that does not have child nodes.

Prefix node: The prefix node is the node corresponding to the routing prefix in the tree structure corresponding to the routing table.

Search path: The search path is the path from the root node along the tree structure corresponding to the destination IP address to the leaf node in the tree structure corresponding to the routing table in the tree structure corresponding to the routing table.

Tail node: The tail node is the last node in the search path.

The method provided by this embodiment of the present application can be applied to the system 300 shown in FIG. 3-a. The system 300 includes a network device 310 , a network device 320 , a network device 330 and a network device 340 .

In this embodiment of the present application, the network device 320 includes a processor 321 , a cache 322 and a memory 323 . The processor 321 is a unit with data processing capability inside the network device 320, for example, it may be a unit for data processing in a processor core (core), the cache 322 may be a high-speed storage device such as SRAM, and the memory 323 may include memory and Any one or more of the external storage.

It should be noted that the cache 320 in FIG. 3-a is independent of the processor 321, which does not mean that the cache provided in the embodiment of the present application is necessarily encapsulated in the processor. In some possible implementations, the cache may also be a storage device packaged inside the processor. In addition, in the embodiment shown in FIG. 1, the network device 320 includes a processor 321 and a cache 322, which does not mean that the device provided in this embodiment of the present application can only include a processor and a cache. In some possible implementations, a device may include one or more processors, which may include one or more processing units, and one or more caches. One cache may correspond to one processing unit or multiple processing units, and one processing unit may also correspond to one or more caches. This embodiment of the present application does not limit the specific architecture of the processor.

In some possible implementations, the network device may have a multi-level cache structure, that is, multiple caches with different levels are constructed by using multiple storage media, and the caches with higher levels have faster data exchange speed and smaller size. Then, for a computer with a multi-level cache structure, the cache in this embodiment of the present application may be a level-1 cache (the level-1 cache is the cache with the highest level), and the memory may include other caches with a level lower than the level-1 cache, such as level-2 cache cache, L3 cache, etc. That is, in the embodiment of the present application, the cache is a storage device with the fastest data exchange speed, and the memory is a general term for all other storage devices whose data exchange speed is lower than that of the cache.

In the embodiment of the present application, in order to facilitate the fast lookup of routing table entries, the cache may further include hardware modules such as a ternary content addressable memory (Ternary Content Addressable Memory, TCAM), a register, a line card board, and a die.

Some application scenarios of the caching method provided by the embodiments of the present application are first introduced below. It should be noted that the application scenarios provided by the embodiments of the present application are only some typical application scenarios, which does not mean that the caching methods provided by the embodiments of the present application can only be used in these application scenarios.

Referring to FIG. 3-b, the figure is a schematic structural diagram of a network device provided by an embodiment of the present application. In the embodiment shown in FIG. 3-b , the network device 350 includes a processor 351 , a TCAM 352 and a memory 353 . The processor 351 is connected to the TCAM 352 and the memory 353 respectively. The memory 353 can be used to store the main routing table; the TCAM 352 can be used as a cache to store the cached routing table, or to look up the corresponding routing information according to the destination IP address; the processor 351 can be used to store the routing prefix and route in the TCAM 352 according to the destination IP address. information, or forward packets according to the routing information found by the TCAM352.

Optionally, when the network device has multiple processors, each processor may correspond to a respective TCAM, and the multiple processors may correspond to the same memory. Specifically, referring to FIG. 3-c, when the network device 350 further includes the processor 354, the network device 350 may further include the TCAM 355. The processor 351 is connected to the TCAM 355 and the memory 353 respectively. TCAM 355 may act as a cache for storing routing tables used by processor 354 . Similarly, TCAM 352 may be used to store routing tables used by processor 351. In this way, each processor has a relatively independent TCAM for storing the routing table required by itself, and does not need to store the entire routing table. In this way, not only storage space is saved, but also because less content is stored in the TCAM, the speed at which the processor reads the routing table is improved. It should be noted that, in the embodiment shown in Figure 3-c, the speed at which the processor 351 reads data from the TCAM 352 may not be faster than the speed at which the processor 351 reads data from the memory 353.

For the working mode of the TCAM352, reference may be made to the introduction of the embodiment in Table 7 below, which will not be repeated here.

Optionally, the role played by the aforementioned TCAM can be implemented by comparing logic circuits and registers in parallel. Specifically, referring to FIG. 3-d, the role of the TCAM 352 in the embodiment shown in FIG. 3-b can be realized by a parallel comparison logic circuit 356 and a register 357. The processor 351 is connected to the parallel comparison logic circuit 356 , and the parallel comparison logic circuit 356 is connected to the register 357 . The register 357 is used to store the routing table, and the parallel comparison logic circuit is used to determine the routing information corresponding to the destination IP address.

Optionally, in the embodiments shown in FIGS. 3-b, 3-c and 3-d, the processor 351 and/or the processor 352 may refer to a processor core.

Referring to FIG. 3-e, the figure is a schematic structural diagram of a network device provided by an embodiment of the present application. In the embodiment shown in FIG. 3-e , the network device 360 includes a line card board 361 , a line card board 362 , a line card board 363 , a switch fabric board 364 and a switch fabric board 365 . The switch fabric board 364 is respectively connected with the line card board 361 , the line card board 362 and the line card board 363 , and the switch fabric board 365 is connected with the line card board 361 , the line card board 362 and the line card board 363 respectively.

In the embodiment shown in FIG. 3-e, each line card board may include a cache for storing the cache routing table that the line card board needs to use. For example, the line card board 361 includes a cache 361-1 for storing the cache routing table that the line card board 361 needs to use; the line card board 362 includes a cache 362-1 for storing the cache routing table that the line card board 362 needs to use; The line card board 363 includes a cache 363-1 for storing a cache routing table that the line card board 363 needs to use. The switching fabric board can store a routing table containing all routing information, that is, the aforementioned main routing table. The main routing table may be stored in the switch fabric board 364 and/or the switch fabric board 352 , or may be split into two parts and stored in the switch fabric board 364 and the switch fabric board 352 respectively. Optionally, the main routing table can be stored in the cache of the switch fabric.

Referring to FIG. 3-f, the figure is a schematic structural diagram of a chip of a network device provided by an embodiment of the present application. In the embodiment shown in FIG. 3-f , chip 370 includes die 371 , die 372 , die 373 , and die 374 . The die 371 is connected to the die 372 and the die 374 respectively, and the die 373 is connected to the die 372 and the die 374 respectively. Of course, in some other implementation manners, the dies in the chip may also be connected in other ways.

A cache may be included in any die in the chip. For example, die 371 may include cache 371-1, die 372 may include cache 372-1, die 373 may include cache 373-1, and die 374 may include cache 374-1. Any one or more of the cache 371-1, the cache 372-1, the cache 373-1, and the cache 374-1 may be used to store the cache routing table, and any one or more of the caches may be used to store the main routing table.

In practical application scenarios, multiple network devices can act as a virtual router to forward packets. For example, refer to FIG. 3-g, which is a schematic structural diagram of a virtual router provided by an embodiment of the present application. In the embodiment shown in FIGS. 3-g, virtual router 380 includes network device 381, network device 382, network device 383, network device 384, and network device 385. The network device 383 is connected to the network device 381 , the network device 382 , the network device 384 and the network device 385 respectively. In the virtual router 380, the network device 385 may be used to store the main routing table, and the network device 381, the network device 382, the network device 384, and the network device 385 may store their respective required cache routing tables. Optionally, network device 383 may store the master routing table in a cache of network device 383 .

Referring to FIG. 4 , FIG. 4 is a data interaction diagram of a caching method provided by an embodiment of the present application. The caching method provided by the embodiment of the present application includes the following steps:

S401: The processor obtains the first packet.

In this embodiment of the present application, the processor may be a processor in a network device. For example, the processor may be the processor 321 in the network device 320 in FIG. 3-a, or may be a processing unit in the processor 321 for processing data. The processor may receive the first packet sent by other devices through the network interface. For example, when the processor is the processor 321 in FIG. 3-a, the processor 321 may receive the first packet sent by the network device 310. Certainly, in some possible implementations, the processor may also receive the first packet sent by the terminal device. Of course, the cache described below may be a cache in a network device, for example, the cache 322 in FIG. 3-a. The memory may be memory in a network device. For example, it may be memory 323 in Figure 3-a.

The IP address of the destination device of the first packet is called the destination IP address of the first packet, and indicates to which device the first packet needs to be sent. Then, after receiving the first packet, the processor may parse the first packet to determine the destination IP address of the first packet.

S402: The processor searches the cache for a routing prefix matching the destination IP address.

After determining the destination address of the first packet, the processor may look up the routing prefix matching the destination IP address from the cache, for example, the processor may look up the routing prefix matching the destination IP address from the cached routing table. When there are multiple routing prefixes matching the destination IP address in the cache routing table, the processor can determine the routing prefix with the longest length as the routing prefix matching the destination IP address. In some possible implementations, the processor may also convert the cache routing table into a corresponding tree structure such as a binary tree or a polytree, and determine a routing prefix matching the destination IP address through the tree structure.

If the processor can find a routing prefix matching the destination IP address from the cache, the processor can obtain routing information corresponding to the destination IP address from the cache, and forward the first packet through the routing information. If the processor cannot find a routing prefix matching the destination IP address from the cache, it means that the routing prefix corresponding to the destination IP address is not stored in the cache routing table. Then the processor can look up the routing prefix and routing information matching the destination IP address from the memory, and update the cache routing table according to the found routing prefix and routing information.

Optionally, before updating the cache routing table, the processor may first determine whether there is a storage space for storing routing prefixes and routing information in the cache routing table. If the storage space of the cache is full, the processor may not update the cache routing table, or delete the routing prefix and routing information already stored in the cache, so as to use the new storage space to store the new routing prefix and routing information.

The following describes a method for the processor to update the cache routing table in the case that the routing prefix matching the destination IP address is not included in the slave cache.

S403: In response to the cache not storing the routing prefix, the processor searches the memory for a prefix node and routing information corresponding to the destination IP address.

If the routing prefix corresponding to the destination IP address is not stored in the cache, the processor may look up the routing prefix and routing information corresponding to the destination IP address from the memory. Optionally, the processor may determine the routing prefix corresponding to the destination IP address through the tree structure corresponding to the routing table. Then, the processor can determine the prefix node corresponding to the destination IP address from the tree structure corresponding to the routing table, and obtain the routing information of the prefix node.

The method by which the processor determines the prefix node is described below.

Assume that the routing table stored in the memory is shown in Table 4:

Table 4

routing prefix		routing information
0*	network interfaceX
11*	network interface A
0000*	network interface B
0001010*	network interface C
00010111*	network interface D
0001011111*	network interface E
00010110000*	network interface F
00010110010*	network interface G

A schematic diagram of the attribute structure corresponding to the routing table may be shown in FIG. 5 . The numbers in each node in FIG. 5 represent the number of the node. Then, node 2 is the prefix node corresponding to routing prefix 0*; node 2 is the prefix node corresponding to routing prefix 11*; node 7 is the prefix node corresponding to routing prefix 0000*; node 11 is the prefix node corresponding to routing prefix 0001010* ; node 14 is the prefix node corresponding to the routing prefix 00010111*; node 19 is the prefix node corresponding to the routing prefix 0001011111*; node 20 is the prefix node corresponding to the routing prefix 00010110000*; 21 Node 21 is the prefix node corresponding to the routing prefix 00010110010*.

If the destination IP address of the first packet is 0001011010010001, since the destination IP address only matches the routing prefix 0*, the processor can determine that the prefix node corresponding to the destination IP address is node 2, and the corresponding routing information is network interface X . If the destination IP address of the first packet is 0001010010100010, since the destination IP matches the route prefix 0* and the route prefix 0001010*, and the length of the route prefix 0001010* is greater than the length of the route prefix 0*, the processor can determine that the destination IP address is the same as the destination IP address. The prefix node corresponding to the IP address is node 11, and the corresponding routing information is network interface C.

In practical application scenarios, the number of correspondences stored in the routing table is often large, and the corresponding tree structure is also complex. Then, in order to quickly find the prefix node corresponding to the destination IP address, the tree structure corresponding to the routing table can be divided into multiple sub-tree structures, and the tree structure composed of the root nodes of these sub-tree structures is called a virtual tree structure. The root node of each subtree structure corresponds to a virtual prefix. The routing prefix represented by each node in the subtree structure can be determined according to the virtual prefix and the position of the node in the virtual tree structure. For example, if the virtual prefix of a subtree structure is 1000*, then the routing prefix corresponding to the right child node of the root node of the subtree structure is 10001*.

When searching for the routing prefix corresponding to the destination IP address, the processor can first search the virtual prefix with the longest matching destination IP address from the virtual tree structure, and determine the virtual prefix with the longest length from the virtual prefixes matching the destination IP address. . Next, the processor may determine a prefix node matching the destination IP address from the sub-tree structure corresponding to the virtual prefix. If there is no prefix node matching the destination IP address in the subtree corresponding to the virtual prefix, the processor may determine the prefix node corresponding to the virtual prefix as the prefix node of the destination IP address.

for example. For the binary tree shown in Figure 5, it can be divided into three subtree structures. The root nodes of the three subtree structures are root node 1, node 6, and node 12, respectively, and the virtual prefixes are *, 00*, and 0001011*, respectively. Then, when the virtual tree structure is represented in the form of a table, the table can be as shown in Table 6. The three subtrees can be shown in Figure 6.

Table 6

virtual prefix	prefix length	subtree information
*	0	subtree 0
00*	2	subtree 1
0001011*	7	subtree 2

Among them, the first row of Table 6 indicates that the virtual prefix of length 0 is * and corresponds to subtree 0, that is, if the destination IP address does not match other virtual prefixes in Table 6, the processor can determine from subtree 0 that the The prefix node identified by the destination IP address. The second row of Table 6 indicates that the virtual prefix 00* of length 2 corresponds to subtree 1. The third row of Table 6 indicates that the virtual prefix 0001011* of length 7 corresponds to subtree 2.

When receiving the first packet with the destination IP address of 0001010010100010, since the destination IP address matches the virtual prefix 00* the longest, the processor can search for a prefix node matching the destination IP address from subtree 1. Since the routing prefix of node 11 in subtree 1 is 0001010* which matches the destination IP address, and node 11 is a prefix node, then the processor can determine the routing prefix 0001010* as the routing prefix matching the destination IP address 0001010010100010, the node 11 is the corresponding prefix node.

When receiving the first packet with the destination IP address 0001011010010001, since the destination IP address matches the virtual prefix 00* the longest, the processor can search for the prefix node matching the destination IP address from subtree 1. Since there is no prefix node matching the destination IP address in the subtree 1, the processor may determine the prefix node corresponding to the virtual prefix 00* as the prefix node corresponding to the destination IP address. Then the processor can determine that the prefix node matching the destination IP address 0001011010010001 is node 2, and the matching route prefix is 0*.

S404: The processor determines a correspondence set according to the prefix node and routing information.

After determining the prefix node and routing information corresponding to the destination IP address, the processor may determine the corresponding relationship set according to the prefix node and the routing information. The correspondence set may include the correspondence between the routing prefix of the prefix node and the routing information, and may also include the correspondence between the first routing prefix and the routing information. In this embodiment of the present application, the correspondence between the first routing prefix and the routing information may be referred to as the first correspondence. Specifically, when the prefix node matching the destination IP address is a leaf node, the corresponding relationship may include the corresponding relationship between the routing prefix of the prefix node and the routing information; when the prefix node matching the destination IP address is not a leaf node, The correspondence may include a first correspondence. For the introduction of the first routing prefix, please refer to the following.

The two cases are described below.

In the first possible implementation, the prefix node matching the destination IP address is the leaf node, that is, the tail node of the search path is the prefix node, then the processor can determine that the corresponding relationship is between the routing prefix of the prefix node and the routing information corresponding relationship.

Since a leaf node is a node without child nodes, the prefix node does not have child nodes either. That is, in one or more routing prefixes recorded in the routing table, there is no other routing prefix whose first n bits are consistent with the routing prefix and whose length is greater than n. Among them, n is the length of the routing prefix.

Still taking FIG. 5 as an example for description, assuming that the destination IP address is 0001010010100010, the prefix node matching the destination IP address is node 11 . Node 11 is a leaf node and has no child nodes. If node 11 has a left child node or a right child node, the routing prefix corresponding to the left child node of node 11 is 00010100*, and the queue routing prefix corresponding to the right child node of node 11 is 00010101*. Since these two child nodes do not exist, it means that the routing table does not include the two routing prefixes 00010100* and 00010101*, and naturally does not include other routing prefixes whose first 7 digits are 0001010 and whose length is greater than 7.

It can be seen that there are no other routing prefixes whose first n bits are consistent with the routing prefix of the prefix node and whose length is greater than n (n is the length of the routing prefix) in the routing table. Naturally, the destination IP address matching the routing prefix of this prefix node cannot possibly match other routing prefixes whose length is greater than n. Therefore, after the routing prefix of the prefix node is stored in the cache routing table, there will be no false hits, that is, the destination IP address should match a routing prefix with a length greater than n, but the route stored in the cache routing table will not occur. When the prefix does not exactly match the prefix of the route.

Then, the processor may obtain the routing information corresponding to the routing prefix of the prefix node from the memory, so as to store the corresponding relationship between the routing prefix and the routing information in the cache in a subsequent step.

In the second possible implementation, the prefix node matching the destination IP address is not a leaf node, that is, the tail node of the search path is not a prefix node, then the correspondence set may include the first correspondence. When determining the first correspondence, the processor may first determine the first routing prefix. The first routing prefix matches the destination IP address, and its length is determined according to the first prefix matching length. The first prefix matching length is the length from the root node of the tree structure to the tail node of the search path, that is, the search path The number of nodes between the tail node and the root node is incremented by 1.

In this embodiment of the present application, the length of the first routing prefix may be greater than the first prefix matching length, may also be equal to the first prefix matching length, or may be smaller than the first prefix matching length. They are introduced separately below.

First, the case where the first routing prefix is greater than the matching length of the first prefix is introduced.

In the tree structure corresponding to the routing table, since the prefix node corresponding to the destination IP address is not a leaf node, it means that the subtree of the prefix node includes other prefix nodes, that is, the cache routing table contains the routing prefix corresponding to the destination IP address. Other routing prefixes, and these routing prefixes do not match the destination IP address. Therefore, in order to avoid false hits, the processor may determine a routing prefix that is outside the tree structure corresponding to the routing table and that matches the destination IP address as the first routing prefix.

Specifically, the processor may select a portion of the destination IP address whose length is greater than the matching length of the first prefix as the first routing prefix. The first prefix matching length is the length of the tail node of the search path from the root node of the tree structure to the destination IP address, that is, the length of the routing prefix corresponding to the tail node. Since the prefix node corresponding to the destination IP address is not a leaf node, and the tail node in the search path is not a prefix node, it means that the tree structure corresponding to the destination IP address and the tree structure corresponding to the forwarding table are different from the position of the tail node. Therefore, selecting the part of the destination IP address whose length is greater than the matching length of the first prefix as the first routing prefix can ensure that the tail node corresponding to the first routing prefix is outside the tree structure corresponding to the forwarding table, that is, the first routing prefix and the routing table Any route prefix in the corresponding tree structure does not overlap. In this way, the first routing prefix is not recorded in the routing table, and naturally it is impossible to record other routing prefixes whose length is longer than that of the first routing prefix and includes the first routing prefix. That is to say, assuming that the length of the first routing prefix is n, then there is no other routing prefix whose first n bits are consistent with the destination IP address and whose length is greater than n in the routing table. Naturally, any IP address including the first routing prefix cannot match the routing prefix whose length is greater than n in the destination routing table. Therefore, after the routing prefix of the prefix node is stored in the cache routing table, there will be no false hits, that is, the destination IP address should match a routing prefix with a length greater than n, but the route stored in the cache routing table will not occur. When the prefix does not exactly match the prefix of the route.

Still take FIG. 5 as an example for description. Assuming that the destination IP address is 0001011010010001, the routing prefix matching the destination IP address is 0*, and the search path of the destination IP address in the tree structure is "1-2-4-6-8-9-10-12- 13". Its tail node is node 13, and the first prefix matching length is 8. The part of the destination IP address outside the routing table is represented by a tree structure, and the obtained tree structure may be as shown in FIG. 7 . On the basis of the embodiment shown in FIG. 5 , node 22 , node 23 , node 24 , node 25 , node 26 , node 27 , package node 28 , and node 29 are newly added to the tree structure shown in FIG. 7 . These nodes correspond to bits 9-16 of the destination IP address, respectively. Since these nodes do not exist in the tree structure corresponding to the routing table, these nodes can also be called virtual nodes.

Since the virtual node is located in a part of the tree structure corresponding to the destination IP address outside the tree structure of the routing table, the routing prefix corresponding to the virtual node is greater than the first prefix matching length. Therefore, when determining the first routing prefix, the processor may determine the routing prefix corresponding to any virtual node as the first routing prefix. For example, the processor may determine the routing prefix corresponding to the virtual node directly connected to the tail node as the first routing prefix. In the embodiment shown in FIG. 6 , the processor may determine the routing prefix 000101101* corresponding to the node 22 as the first routing prefix, and the length of the first routing prefix is the first prefix matching length plus one. Certainly, in some possible implementation manners, the processor may also determine the routing prefix corresponding to any other virtual node as the first routing prefix. For example, the routing prefix 00010110100* corresponding to the node 24 may be determined as the first routing prefix.

According to the above description, when determining the prefix node matching the destination IP address, the processor can first determine the virtual prefix and subtree structure corresponding to the destination IP address according to the virtual tree structure, and then determine the prefix matching the destination IP address according to the subtree structure. node. Similarly, the processor may also determine the first routing prefix through the virtual tree structure.

Specifically, it is assumed that the first length is the length from the root node of the virtual tree structure to the virtual prefix corresponding to the destination IP address, that is, the length of the virtual prefix matching the destination IP address, and the second length is the virtual prefix to the end of the search path The length between nodes, that is, the length from the root node to the tail node in the subtree structure corresponding to the destination IP address. Since the search path of the destination IP address is from the root node of the virtual tree structure to the root node of the subtree structure corresponding to the virtual prefix, and then from the root node of the subtree structure to the tail node, the sum of the first length and the second length is The first prefix matches the length. When determining the first routing prefix, the processor may determine the virtual prefix as the first half of the first routing prefix, and then select the part whose length is greater than the second length from the destination IP address to determine the second half of the first routing prefix.

Taking the embodiment shown in FIG. 6 as an example for description, assuming that the destination IP address is 0001011010010001, the virtual prefix matching the destination IP address is the virtual prefix corresponding to the node 12, that is, 0001011*. The processor may determine the first 7 bits of the first routing prefix as 0001011*. Since the tail node of the destination IP address in subtree 2 is node 13, and the length from node 12 to node 13 is 1, that is, the second length is 1, the processor can intercept the length greater than 1 from the 8th bit of the destination IP address. part as the second half of the first routing prefix. For example, the processor may use the 8th and 9th digits of the destination IP address as the second half of the first routing prefix, and the obtained first routing prefix is 000101101*.

The following describes the case where the length of the first routing prefix is equal to the matching length of the first prefix.

In an actual application scenario, since the modification of the routing table may not be synchronized with the modification of the tree structure, the leaf nodes in the tree structure may not be prefix nodes. Then, when the prefix node corresponding to the destination IP address is not a leaf node, and the tail node of the search path of the destination IP address in the tree structure is a leaf node, the processor may determine the route prefix corresponding to the leaf node as the first route prefix. In this way, the length of the first routing prefix may also be equal to the matching length of the first prefix.

Specifically, after a certain routing prefix in the routing table is deleted, the node (hereinafter referred to as node A) corresponding to the routing prefix in the tree structure may not be deleted. But since the routing table has been modified, node A is not a prefix node. If node A has no child nodes, then node A is a leaf node that is not a prefix node in the tree structure.

For example, in the embodiment shown in Figure 5, it is assumed that the routing prefix 0000* is deleted from the routing table, but node 7 may still remain in the tree structure. Then the node 7 is a leaf node of the non-prefix node.

After receiving the first packet, if the destination IP address of the first packet is 0000101010101010, the route prefix matching the destination IP address is 0*, the corresponding prefix node is node 2, and the tail node of the search path is Node 7, the routing prefix of node 7 is 0000*, and the first prefix matching length is 4. Then, the processor may determine the routing prefix 0000* of the node 7 as the first routing prefix. It can be seen that in this case, the length of the first routing prefix is the same as the matching length of the first prefix.

The following describes the case where the length of the first routing prefix is smaller than the matching length of the first prefix.

In some possible implementations, the length of the first routing prefix may also be less than the first prefix matching length and greater than the length of the routing prefix corresponding to the prefix node, that is, the length of the routing prefix matching the destination IP address in the memory routing table. That is to say, the node corresponding to the first routing prefix in the tree structure is the node in the lower layer of the prefix node and the upper layer of the tail node in the search path. In this way, although the length of the first routing prefix is less than the matching length of the first prefix, since the length of the first routing prefix is still greater than the length of the routing prefix matching the destination IP address in the memory routing table, compared with the prior art, Storing the correspondence between the first routing prefix and the routing information in the cache can still play a role in reducing the probability of false hits. It is easy to understand that the longer the length of the first routing prefix, the smaller the probability of false hits. When the length of the first routing prefix is greater than the first prefix matching length, the probability of false hits is 0.

for example. Assuming that the destination IP address is 0001011010010001, the prefix node matching the destination IP address is node 2, the length of the corresponding routing prefix is 1, the tail node is node 12, and the corresponding first prefix matching length is 8. Then, the processor can use the first m bits of the destination IP address as the first routing prefix, where m is a positive integer greater than 1 and less than 8. For example, the processor may determine the routing prefix 00010110* as the first routing prefix.

The method for the processor to determine the first routing prefix is described above. After determining the first routing prefix, the processor can look up routing information from the routing table stored in the memory according to the routing prefix matching the destination IP address, and then use the routing prefix. The correspondence between the information and the first routing prefix is determined as the first correspondence.

Optionally, when the processor determines the prefix node matching the destination IP address through the virtual tree structure, the correspondence set may further include a third correspondence. Wherein, the third corresponding relationship may include information about virtual prefixes, types of virtual prefixes, and subtree structures. The virtual prefix is a virtual prefix matching the destination IP address, and the information of the subtree structure is used to indicate which subtree the destination IP address corresponds to. The type of the virtual prefix is used to indicate that when the virtual prefix is hit, the corresponding subtree structure is searched according to the information of the subtree structure.

That is to say, after receiving a new packet, if the destination IP address of the packet matches the virtual prefix stored in the cache, the processor can search for the subtree structure corresponding to the virtual prefix according to the type of the virtual prefix. Therefore, the sub-tree structure corresponding to the virtual prefix is determined according to the third correspondence, and the routing prefix matching the destination IP address is further determined according to the sub-tree structure.

To improve search efficiency, in some possible implementations, the set of correspondences may further include a second correspondence. The second correspondence is the correspondence between the second routing prefix and the routing information. The routing information is routing information of a routing prefix corresponding to the destination IP address of the first packet.

The following describes a method for the processor to determine the second routing prefix.

After determining that the prefix node corresponding to the destination IP address is not a leaf node, the processor can determine all the only-child nodes after the prefix node in the search path according to the tree structure, that is, nodes with only left child nodes or right child nodes. Next, the processor may determine the length of the routing prefix corresponding to the single-child node as the second prefix matching length. That is, the length of the second prefix matching is equal to the length between the root node of the tree structure and the single-child node. Next, the processor may determine the second routing prefix according to the second prefix matching length and the destination IP address. Assuming that the matching length of the second prefix is n, the processor may determine the first n of the destination IP address as the second routing prefix.

Since the only-child node is the node after the prefix node in the search path of the destination IP address, it means that the routing prefix corresponding to any single-child node is not in the cache routing table, and the prefix node corresponding to the packet matching the only-child node is the destination IP address The prefix node for the address. Therefore, the routing prefixes of the IP addresses matching these only-child nodes are the routing prefixes of the prefix nodes. Also, because the only-child node is located on the search path of the destination IP address, the destination IP address includes the routing prefix of each only-child node. Therefore, the second prefix matching length is determined according to the only-child node, and then the second routing prefix is selected from the destination IP address according to the second prefix matching length, and the obtained second routing prefix matches the routing information corresponding to the prefix node of the destination IP address. Therefore, the processor may record the correspondence between the second routing prefix and the routing information as the second correspondence, and add the correspondence set for cache storage.

The embodiment shown in FIG. 5 is still taken as an example for description. After receiving the first packet with the destination IP address of 0001011010010001, the processor may determine that the prefix node is node 2. The tail node is node 13 , and the only child nodes between the prefix node and the tail node include node 4 , node 8 and node 9 . The second prefix matching length corresponding to node 4 is 2, the second prefix matching length of node 8 is 4, and the second prefix matching length of node 9 is 5. Then, the processor can determine the first 2 digits, the first 4 digits and the first 5 digits of the destination IP address as the second routing prefix respectively, that is, the routing prefix 00*, the routing prefix 0001* and the routing prefix 00010* are all the second routing prefix. . Next, the processor may determine the correspondence between the three routing prefixes and the routing information "network interface X" corresponding to the routing prefix 0* as the second correspondence.

S405: The processor triggers the cache to store the corresponding relationship set.

After obtaining the corresponding relationship set, the processor may trigger the cache to store the corresponding relationship set. Optionally, considering the longest prefix matching principle, the processor may further trigger the cache to store the length of the first routing prefix.

In addition, when the correspondence set includes the first correspondence, the processor may further trigger the cache to store the type of the first routing prefix. The type of the first routing prefix is used to instruct the processor to obtain routing information corresponding to the first routing prefix in the cache according to the first correspondence when the first routing prefix is hit. That is to say, after receiving a new packet, if the destination IP address of the packet matches the first routing prefix stored in the cache, the processor can look up the first routing prefix from the cache routing table according to the type of the first routing prefix. For the routing information corresponding to a routing prefix, it is not necessary to search the routing information corresponding to the first routing prefix from the memory.

The following describes the process of searching for the corresponding routing information by the destination IP address of the TCAM.

Assume that the TCAM serving as the cache routing table stores the correspondence between the routing prefix 000101101* and the network interface X, and the correspondence between the routing prefix 0001011* and the routing prefix 0000* and the network interface B. Then the entries stored in the TCAM can be as shown in Table 7.

Table 7

TCAM key	TCAM mask	TCAM AD
000101101*	1111111110000000	network interfaceX
0000*	1111000000000000	network interface B

Among them, the first item of the header in Table 7 is the TCAM mask (TCAM key), which is used to record the routing prefix to be matched. The first item of the header in Table 7 is a TCAM mask (TCAM mask), which is used to detect the matching degree between the destination IP address and the TCAM keyword. The first item of the header in Table 7 is TCAM Associated Data (AD), which is used to record routing information corresponding to TCAM keywords.

The first row in Table 7 indicates that TCAM can use the TCAM mask 1111111110000000 to determine whether the destination IP address of the packet matches the TCAM keyword 000101101*, and send it through network interface X after determining that the destination IP address TCAM keyword 000101101* matches. The second row in Table 7 indicates that the TCAM can use the TCAM mask 1111000000000000 to determine whether the destination IP address of the packet matches the TCAM keyword 0000*, and send the packet through network interface B after determining that the destination IP address TCAM keyword 0000* matches.

When judging whether the destination IP address of the packet matches the TCAM keyword, the TCAM can perform an "AND" operation on the TCAM mask and the destination IP address bit by bit, and also perform an "AND" with the TCAM keyword and the TCAM mask bit by bit. operation. Finally, compare whether the results obtained by the two operations are completely consistent bit by bit. If the results obtained by the two operations are completely consistent, the TCAM can determine that the destination IP address matches the TCAM keyword, so as to send the packet according to the routing information recorded in the TCAM associated data.

for example. Assuming that the network device receives the packet with the destination IP address 0001011010010001, the processor can perform a bit-by-bit AND operation on the destination IP address 0001011010010001 with the TCAM keyword 1111111110000000 and the TCAM mask 1111000000000000 respectively.

During the bit-by-bit AND operation, if the value of the destination IP address and the TCAM mask in a certain bit is 1, the result is 1; otherwise, the result is 0. For example, the first bit of the destination IP address is 0, the first bit of the TCAM mask 1111111110000000 is 1, and the result of the AND operation between the two is 0. The fourth bit of the destination IP address is 1, the fourth bit of the TCAM mask 1111111110000000 is 1, and the result of the AND operation between the two is 1.

By analogy, the result of the bitwise AND operation between the destination IP address 0001011010010001 and the TCAM mask 1111111110000000 is 0001011010000000. The result of the bitwise AND operation between the destination IP address 0001011010010001 and the TCAM mask 1111000000000000 is 0001000000000000. Similarly, the bitwise AND operation of the TCAM keyword 000101101* and the TCAM mask 1111111110000000 results in 0001011010000000. The bit-wise AND operation of the TCAM keyword 0000* and the TCAM mask 1111111110000000 results in 0000000000000000.

Next, since the result obtained by the operation of the destination IP address is exactly the same as the result obtained by the operation of the TCAM keyword 000101101*, the TCAM can determine that the destination IP address matches the routing prefix 000101101*, so that the packet is sent through the network interface X. Since the result obtained by the operation based on the destination IP address is inconsistent with the result obtained by the operation based on the TCAM keyword 0000*, the TCAM can determine that the destination IP address does not match the routing prefix 0000*, so that the packet is not sent through the network interface B.

Referring to FIG. 8 , an embodiment of the present application further provides an integrated circuit 800 , and the integrated circuit 800 can implement the functions of the processor in the embodiment shown in FIG. 4 . The integrated circuit includes an interface circuit 801 and a control circuit 802 . The control circuit 801 and the interface circuit 802 are connected through a communication line 803 . The interface circuit 802 is used to connect the chip 800 with other devices through a communication link. The interface circuit 601 is used to implement S401 , S402 , S403 and S405 in the embodiment shown in FIG. 4 , and the control circuit 802 is used to implement S402 , S403 , S404 and S405 in the embodiment shown in FIG. 4 .

Specifically, the interface circuit 801 is configured to acquire a first packet, where the first packet includes a destination Internet Protocol IP address.

The control circuit 802 is configured to look up a routing prefix matching the destination IP address from the cache; in response to the routing prefix not being stored in the cache, look up a tree structure corresponding to the routing table according to the destination IP address , determine the prefix node matching the destination IP address; in response to the prefix node not being a leaf node, determine the first prefix matching length, the first prefix matching length is equal to the length between the root node and the tail node of the tree structure The length between the two, the tail node is the last node on the search path of the tree structure; according to the first prefix matching length and the destination IP address, determine the first routing prefix; trigger the cache to store the first routing prefix A corresponding relationship, where the first corresponding relationship is the first routing prefix and routing information corresponding to the prefix node.

For the specific execution process, please refer to the detailed description of the corresponding steps in the above-mentioned embodiment shown in FIG. 4 , which will not be repeated here.

Optionally, the integrated circuit 800 provided in this embodiment of the present application may further include a cache. The interface circuit 801 and the control circuit 802 in the integrated circuit 800 may be one or more.

Exemplarily, the integrated circuit 600 may be an FPGA, an ASIC, a system on chip (system on chip, SoC), a CPU, an NP, or a digital signal processing circuit (digital signal processor). , DSP), can also be a microcontroller (micro controller unit, MCU), can also be a programmable logic device (programmable logic device, PLD) or other integrated chips.

Referring to FIG. 9 , an embodiment of the present application further provides an apparatus 900 , and the cache apparatus 900 can implement the function of the processor in the embodiment shown in FIG. 4 . The cache device 900 includes an acquisition unit 901 and a processing unit 902 . The acquiring unit 901 is used to implement S401 in the embodiment shown in FIG. 4 , and the processing unit 402 is used to implement S402 , S403 , S404 and S405 in the embodiment shown in FIG. 4 .

Specifically, the obtaining unit 901 is configured to obtain a first packet, where the first packet includes a destination Internet Protocol IP address.

The processing unit 902 is configured to look up a routing prefix matching the destination IP address from the cache; in response to the routing prefix not being stored in the cache, look up a tree structure corresponding to the routing table according to the destination IP address, and determine A prefix node matching the destination IP address; in response to the prefix node not being a leaf node, determine a first prefix matching length, and the first prefix matching length is equal to the length between the root node and the tail node of the tree structure. length, the tail node is the last node on the search path of the tree structure; determine the first routing prefix according to the first prefix matching length and the destination IP address; trigger the cache to store the first correspondence , the first correspondence is the first routing prefix and routing information corresponding to the prefix node.

For the specific execution process, please refer to the detailed description of the corresponding steps in the above-mentioned embodiment shown in FIG. 4 , which will not be repeated here.

It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical function division, and other division methods may be used in actual implementation. Each functional unit in the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. For example, in the above embodiment, the acquiring unit and the processing unit may be the same unit or different units. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

Referring to FIG. 10 , an embodiment of the present application further provides a chip 1000 , and the chip 1000 can implement the functions of the processor in the embodiment shown in FIG. 4 . The chip includes a memory 1001 and a processor 1002 . The memory 1001 is used to store instructions or program codes, and the processor 1002 is used to call and run the instructions or program codes from the memory 1001 to implement S401 , S402 , S403 , S404 and S405 in the embodiment shown in FIG. 4 .

Optionally, the processor 1002 may be the integrated circuit 800 shown in FIG. 8 . The processor 1002 may include a cache. When the processor 1002 does not include a cache, the memory 1001 may include a cache.

FIG. 11 is a schematic structural diagram of a device 1100 provided by an embodiment of the present application. The device where the processor is located in the above can be implemented by the device shown in FIG. 11 . Referring to FIG. 11 , the device 11900 includes at least one processor chip 1101 and at least one memory 1102 . Optionally, the device 1100 may further include a communication bus 1103 and at least one network interface 1104 .

The processor chip 1101 may be a general-purpose central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits (integrated circuits) used to control the execution of the programs of the present application. circuit, IC). The processor chip 901 may be used to implement the data caching method provided in the embodiments of the present application.

For example, when the network device in FIG. 1 is implemented by the device shown in FIG. 11 , the processor can be used to obtain a first packet, where the first packet includes the destination Internet Protocol IP address; search from the cache A routing prefix matching the destination IP address; in response to the routing prefix not being stored in the cache, look up a tree structure corresponding to the routing table according to the destination IP address, and determine a prefix node matching the destination IP address ; In response to the prefix node not being a leaf node, determine the first prefix matching length, the first prefix matching length is equal to the length between the root node and the tail node of the tree structure, and the tail node is the tree The last node on the search path of the structure; determine the first routing prefix according to the matching length of the first prefix and the destination IP address; trigger the cache to store the first correspondence, and the first correspondence is the A first routing prefix and routing information corresponding to the prefix node.

Optionally, the processor chip 1101 may be the chip 1000 in the embodiment shown in FIG. 10 , or may be the integrated circuit 800 in the embodiment shown in FIG. 8 . When the processor chip 1001 does not include a cache, the memory 1102 may include a cache, a memory and an external memory; when the processor chip 1101 includes a cache, the memory 1102 may include a memory and an external memory.

The memory 1102 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, and the memory 902 can also be a random access memory (RAM) or can store information and other types of dynamic storage devices for instructions, also can be compact disc read-only Memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray optical disks, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, without limitation. The memory 1102 may exist independently, and is connected to the processor 1101 through the communication bus 1103 . The memory 1102 may also be integrated with the processor 1101 . Optionally, memory 1102 may include a cache.

Optionally, the memory 1102 is used for storing program codes or instructions for executing the solution of the present application, and the execution is controlled by the processor 1101 . The processor 1101 is used to execute program codes or instructions stored in the memory 1102 . One or more software modules may be included in the program code. Optionally, the processor 1101 may also store program codes or instructions for executing the solutions of the present application, in which case the processor 1101 does not need to read the program codes or instructions from the memory 1102 .

Optionally, the memory 1102 may be used to implement the role of the memory 120 in the device shown in FIG. 1 .

The communication bus 1103 is used to transfer information between the processor chip 1101 , the network interface 1104 and the memory 1102 .

The network interface 1104 may be a device such as a transceiver for communicating with other devices or a communication network, which may be Ethernet, a radio access network (RAN), or a wireless local area network (WLAN), or the like. In this embodiment of the present application, the network interface 904 may be configured to receive packets sent by other nodes in the segment routing network, and may also send packets to other nodes in the segment routing network. The network interface 1104 may be an ethernet (ethernet) interface, a fast ethernet (FE) interface, or a gigabit ethernet (GE) interface, or the like.

In a specific implementation, as an embodiment, the device 1100 may include multiple processor chips, such as the processor chip 1101 and the processor chip 1105 shown in FIG. 9 . Each of these processor chips can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. Optionally, different steps in the caching method shown in FIG. 4 may be performed by different processor chips. A processor chip herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).

FIG. 12 is a schematic structural diagram of a device 1200 provided by an embodiment of the present application. The device 100 in FIG. 1 can be implemented by the device shown in FIG. 12 . Referring to the schematic diagram of the device structure shown in FIG. 12 , the device 1200 includes a main control board and one or more interface boards. The main control board communicates with the interface board. The main control board is also called the main processing unit (MPU) or the route processor card (route processor card). The main control board includes a CPU and memory. The main control board is responsible for the control and management of various components in the device 1000, including Route calculation, device management and maintenance functions. Interface boards, also known as line processing units (LPUs) or line cards, are used to receive and send messages. In some embodiments, the communication between the main control board and the interface board or between the interface board and the interface board is through a bus. In some embodiments, the interface boards communicate through a switch fabric board. In this case, the device 1200 also includes a switch fabric board. The switch fabric board is communicatively connected to the main control board and the interface board. The switch fabric board is used to forward the interface board. The data between them, the switch fabric board can also be called a switch fabric unit (SFU). The interface board includes a CPU, a memory, a forwarding engine, and an interface card (IC), wherein the interface card may include one or more network interfaces. The network interface can be an Ethernet interface, an FE interface, or a GE interface. The CPU is connected in communication with the memory, the forwarding engine and the interface card, respectively. The memory is used to store the forwarding table. The forwarding engine is used to forward the received packet based on the forwarding table stored in the memory. If the destination address of the received packet is the IP address of the device 1200, the packet is sent to the CPU of the main control board or interface board for processing. Processing; if the destination address of the received message is not the IP address of the device 1200, then look up the forwarding table according to the destination, if the next hop and outgoing interface corresponding to the destination address are found from the forwarding table, the message Forwarding to the outbound interface corresponding to the destination address. The forwarding engine may be a network processor (NP). The interface card, also called a daughter card, can be installed on the interface board and is responsible for converting photoelectric signals into data frames, and after checking the validity of the data frames, forwards them to the forwarding engine for processing or the interface board CPU. In some embodiments, the CPU can also perform the function of a forwarding engine, such as implementing soft forwarding based on a general-purpose CPU, so that a forwarding engine is not required in the interface board. In some embodiments, the forwarding engine may be implemented by an ASIC or a field programmable gate array (FPGA). In some embodiments, the memory that stores the forwarding table may also be integrated into the forwarding engine as part of the forwarding engine.

Optionally, the number of processors in the chip system may be one or more. The processor can be implemented by hardware or by software. When implemented in hardware, the processor may be a logic circuit, an integrated circuit, or the like. When implemented in software, the processor may be a general-purpose processor implemented by reading software codes stored in memory.

Optionally, there may also be one or more memories in the chip system. The memory may be integrated with the processor, or may be provided separately from the processor, which is not limited in this application. Exemplarily, the memory can be a non-transitory processor, such as a read-only memory ROM, which can be integrated with the processor on the same chip, or can be provided on different chips. The setting method of the processor is not particularly limited.

Exemplarily, the chip system may be an FPGA, an ASIC, a system on chip (system on chip, SoC), a CPU, an NP, or a digital signal processing circuit (digital signal processor, DSP), can also be a microcontroller (micro controller unit, MCU), can also be a programmable logic device (programmable logic device, PLD) or other integrated chips.

It should be understood that, each step in the above method embodiments may be implemented by a hardware integrated logic circuit in a processor or an instruction in the form of software. The method steps disclosed in conjunction with the embodiments of the present application may be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

Embodiments of the present application further provide a computer-readable storage medium, including instructions, which, when executed on a computer, cause the computer to execute the caching method provided by the above method embodiments and executed by a processor.

Embodiments of the present application also provide a computer program product containing instructions, which, when running on a computer, cause the computer to execute the caching method provided by the above method embodiments and executed by a processor.

The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is to be understood that data so used may be interchanged under appropriate circumstances so that the embodiments described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above may refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical module division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be acquired according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each module unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware, or may be implemented in the form of software module units.

The integrated unit, if implemented in the form of a software module unit and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .

Those skilled in the art should appreciate that, in one or more of the above examples, the functions described in the present invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.

The specific embodiments described above further describe the objectives, technical solutions and beneficial effects of the present invention in further detail, and it should be understood that the above descriptions are only specific embodiments of the present invention.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: The technical solutions described in the embodiments are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims (25)

1. A caching method, characterized in that the method comprises:

   The processor obtains a first packet, where the first packet includes a destination Internet Protocol IP address;

   The processor searches the cache for a routing prefix matching the destination IP address;

   In response to the routing prefix not being stored in the cache, the processor searches a tree structure corresponding to the routing table according to the destination IP address, and determines a prefix node matching the destination IP address;

   In response to that the prefix node is not a leaf node, the processor determines a first prefix matching length, the first prefix matching length is equal to the length between the root node and the tail node of the tree structure, and the tail node is the last node on the search path of the tree structure;

   The processor determines a first routing prefix according to the first prefix matching length and the destination IP address;

   The processor triggers the cache to store a first correspondence, where the first correspondence is the first routing prefix and routing information corresponding to the prefix node.
2. The method according to claim 1, wherein the length of the first routing prefix is greater than or equal to the first prefix matching length.
3. The method according to claim 1 or 2, wherein the processor searches a tree structure corresponding to the routing table according to the destination IP address, and determining a prefix node matching the destination IP address comprises:

   The processor searches the virtual tree structure corresponding to the routing table according to the destination IP address, and determines the virtual prefix that matches the destination IP address longest;

   The processor searches for a subtree structure corresponding to the virtual prefix according to the destination IP address, and determines a prefix node matching the destination IP address, where the virtual prefix is the root node of the subtree structure;

   The first prefix matching length is equal to the sum of the first length and the second length, the first length is the length from the root node of the virtual tree structure to the virtual prefix, and the second length is the virtual prefix The length to the tail node, where the tail node is the last node on the search path of the subtree structure.
4. The method according to claim 1 or 2, wherein the method further comprises:

   In response to that the prefix node is not a leaf node, the processor determines a second prefix matching length, the second prefix matching length is equal to the length between the root node of the tree structure and the only child node, and the only child node is a node between the prefix node and the tail node that only has left child nodes or only has right child nodes;

   The processor determines a second routing prefix according to the second prefix matching length and the destination IP address, where the length of the second routing prefix is greater than the second prefix matching length;

   The processor triggers the cache to store a second correspondence, where the second correspondence is routing information corresponding to the second routing prefix and the prefix node.
5. The method according to any one of claims 1-4, wherein the method further comprises:

   The processor triggers the cache to store the type of the first routing prefix, where the type of the first routing prefix is used to indicate that when the first routing prefix is hit, according to the first correspondence The routing information corresponding to the first routing prefix is obtained in the cache.
6. The method according to claim 3, wherein the method further comprises:

   The processor triggers the cache to store a third correspondence, where the third correspondence is the correspondence between the virtual prefix, the type of the virtual prefix, and the information of the subtree structure, and the virtual prefix The type of is used to indicate that when the virtual prefix is hit, the subtree structure is searched according to the information of the subtree structure.
7. The method according to any one of claims 1-6, wherein the method further comprises:

   The processor triggers the cache to store the length of the first routing prefix.
8. The method according to claim 2, wherein the length of the first routing prefix is equal to the first prefix matching length plus 1.
9. The method according to any one of claims 1-8, wherein the length of the first routing prefix is smaller than the length of the destination IP address.
10. The method according to any one of claims 1-9, wherein the destination IP address includes the first routing prefix.
11. The method according to any one of claims 1-10, wherein the cache includes at least one of the following:

    Tri-state content addressable memory TCAM, registers, line card boards and die.
12. An integrated circuit, characterized in that the integrated circuit includes an interface circuit and a control circuit;

    Wherein, the interface circuit is used to obtain a first packet, and the first packet includes a destination Internet Protocol IP address;

    The control circuit is configured to look up a routing prefix matching the destination IP address from the cache; in response to the routing prefix not being stored in the cache, look up a tree structure corresponding to the routing table according to the destination IP address, determining a prefix node matching the destination IP address; in response to the prefix node not being a leaf node, determining a first prefix matching length, where the first prefix matching length is equal to the length between the root node and the tail node of the tree structure The length of the tail node is the last node on the search path of the tree structure; according to the first prefix matching length and the destination IP address, determine the first routing prefix; trigger the cache to store the first corresponding The first corresponding relationship is the first routing prefix and routing information corresponding to the prefix node.
13. The integrated circuit of claim 12, wherein the length of the first routing prefix is greater than or equal to the first prefix matching length.
14. The integrated circuit according to claim 12 or 13, wherein,

    The control circuit is configured to search the virtual tree structure corresponding to the routing table according to the destination IP address, and determine the virtual prefix that matches the destination IP address the longest; search for the virtual prefix corresponding to the destination IP address according to the destination IP address subtree structure, determine the prefix node matching the destination IP address, and the virtual prefix is the root node of the subtree structure; the first prefix matching length is equal to the sum of the first length and the second length, so the virtual prefix is the root node of the subtree structure; The first length is the length from the root node of the virtual tree structure to the virtual prefix, and the second length is the length between the virtual prefix and the tail node, and the tail node is the length of the subtree structure. Find the last node on the path.
15. The integrated circuit according to claim 12 or 13, wherein,

    The control circuit is further configured to determine a second prefix matching length in response to that the prefix node is not a leaf node, where the second prefix matching length is equal to the length between the root node of the tree structure and the single-child node, so The single-child node is a node with only a left child node or only a right child node between the prefix node and the tail node; according to the second prefix matching length and the destination IP address, determine the second routing prefix , the length of the second routing prefix is greater than the matching length of the second prefix; trigger the cache to store a second correspondence, where the second correspondence is the routing information corresponding to the second routing prefix and the prefix node .
16. The integrated circuit according to any one of claims 12-15, wherein,

    The control circuit is further configured to trigger the cache to store the type of the first routing prefix, where the type of the first routing prefix is used to indicate that when the first routing prefix is hit, according to the first corresponding The relationship obtains routing information corresponding to the first routing prefix in the cache.
17. The integrated circuit of claim 14, wherein:

    The control circuit is further configured to trigger the cache to store a third correspondence, where the third correspondence is the correspondence between the virtual prefix, the type of the virtual prefix, and the information of the subtree structure, The type of the virtual prefix is used to indicate that when the virtual prefix is hit, the subtree structure is searched according to the information of the subtree structure.
18. The integrated circuit according to any one of claims 12-17, wherein,

    The control circuit is further configured to trigger the cache to store the length of the first routing prefix.
19. The integrated circuit of claim 13, wherein the length of the first routing prefix is equal to the first prefix matching length plus one.
20. The integrated circuit according to any one of claims 12-19, wherein the length of the first routing prefix is smaller than the length of the destination IP address.
21. The integrated circuit according to any one of claims 12-20, wherein the destination IP address includes the first routing prefix.
22. The integrated circuit according to any one of claims 12-21, wherein the cache includes at least one of the following:

    Tri-state content addressable memory TCAM, registers, line card boards and die.
23. A chip, characterized in that the chip includes a memory and a processor, the memory is used to store instructions or program codes, and the processor is used to call and run the instructions or program codes from the memory, so as to execute the instructions or program codes according to claims 1-11 Any of the caching methods described above.
24. A device, characterized in that the device comprises a processor chip and a memory, the memory is used to store instructions or program codes, and the processor chip is used to call and run the instructions or program codes from the memory to execute the instructions or program codes as claimed in the claims The caching method described in any one of 1-11.
25. A computer-readable storage medium, characterized in that it includes instructions, programs or codes, which, when executed on a computer, cause the computer to execute the caching method according to any one of claims 1-11.

Images