WO2022199483A1

WO2022199483A1 - Compiling method and apparatus, electronic device, and computer-readable storage medium

Info

Publication number: WO2022199483A1
Application number: PCT/CN2022/081695
Authority: WO
Inventors: 沈杨书; 何伟; 祝夭龙; 华宝洪
Original assignee: 北京灵汐科技有限公司
Priority date: 2021-03-26
Filing date: 2022-03-18
Publication date: 2022-09-29

Abstract

A compiling method and apparatus, an electronic device, and a computer-readable storage medium. The method comprises: acquiring fault processing core information of a target chip (S101), wherein the target chip comprises a plurality of processing cores, the plurality of processing cores comprising normal cores and/or fault cores; on the basis of the fault processing core information and preset fault information, determining whether the target chip meets a regrouping condition (S102); and when the target chip meets the regrouping condition, grouping, on the basis of the fault processing core information, an algorithm compiling result corresponding to the target chip, so as to obtain a current grouping result, such that the normal cores of the target chip implement, on the basis of the current grouping result and the algorithm compiling result, an algorithm that is prepared to be borne (S103). By means of the method, the utilization rate of chip resources can be effectively improved, and the manufacturing costs of a chip can be reduced.

Description

Compiling method and apparatus, electronic device, computer-readable storage medium

technical field

The embodiments of the present disclosure relate to the field of computer technologies, and in particular, to a compilation method and apparatus, an electronic device, a computer-readable storage medium, and a computer program product.

Background technique

A chip (such as an artificial intelligence chip) can be composed of one or more processors, and a processor usually integrates multiple complete computing engines (or processing cores), and the multiple processing cores in a processor are combined. The processing cores of different processors can cooperate with each other to complete tasks together.

In an actual production process, some processing cores of a chip fail due to manufacturing and other reasons, and these faulty processing cores cannot execute algorithms (or cannot map algorithms to these faulty processing cores).

In a scenario where a multi-chip architecture is used (such as a cloud computing center), when there is a chip that handles core failures in the multi-chip architecture, the chip may not be used, and even the entire multi-chip architecture chip needs to be discarded. manufacturing cost.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide a compilation method and apparatus, an electronic device, a computer-readable storage medium, and a computer program product.

In a first aspect, an embodiment of the present disclosure provides a compilation method, including:

Acquire fault processing core information of the target chip; the target chip includes multiple processing cores, and the multiple processing cores include normal cores and/or faulty cores;

determining whether the target chip meets the regrouping condition based on the fault processing core information and the preset fault information;

In the case that the target chip meets the regrouping condition, based on the fault processing core information, perform grouping processing on the algorithm compilation result corresponding to the target chip to obtain the current grouping result, so that the normal core of the target chip can be processed into groups. An algorithm for implementing a preparatory bearer based on the current grouping result and the algorithm compilation result;

The algorithm compilation result includes an executable file corresponding to the algorithm prepared to be carried by the target chip.

In some embodiments, the method further includes:

Based on the preset fault information, perform the grouping process on the algorithm compilation result corresponding to the target chip to obtain a preset grouping result;

In the case that the target chip does not meet the regrouping condition, the preset grouping result is used as the current grouping result, so that the normal core of the target chip implements a preparatory bearer based on the current grouping result and the algorithm compilation result algorithm.

In some embodiments, the fault handling core information includes an actual number of faulty cores; the preset fault information includes a preset number of faulty cores; the The steps to describe whether the target chip meets the regrouping conditions include:

In the case that the actual number of the faulty cores is inconsistent with the preset number of the faulty cores, determining that the target chip meets the regrouping condition;

Alternatively, in the case that the actual number of the faulty cores is greater than the preset number of the faulty cores, it is determined that the target chip meets the regrouping condition.

In some embodiments, the fault processing core information includes the actual number of faulty cores; the step of performing grouping processing on the algorithm compilation result corresponding to the target chip based on the fault processing core information to obtain the current grouping result ,include:

determining the target number of the normal cores based on the actual number of the faulty cores;

Based on the target number of the normal cores, grouping the algorithm compilation results corresponding to the target chips to obtain the current grouping result; the current grouping result includes the target number of compilation result groups, each of the The compilation result group is used to indicate the executable file to be mapped to a normal core execution.

In some embodiments, the step of acquiring the fault handling core information of the target chip includes:

The one-time programmable memory of the target chip is read to obtain fault processing core information of the target chip.

In some embodiments, the method is applied to a target chip; the fault processing core information further includes absolute coordinates of the faulty core; the algorithm compilation result corresponding to the target chip is performed based on the target number of the normal cores After the grouping process to obtain the current grouping result, it also includes:

According to the absolute coordinates of the faulty core, determine the absolute coordinates of the normal core;

Based on the absolute coordinates of the normal cores, the target number of the compilation result groups included in the current grouping result are mapped to the normal cores, wherein the absolute coordinates of the normal cores mapped by any two of the compilation result groups are The coordinates are different from each other.

In some embodiments, the step of grouping a target number of the compilation results included in the current grouping result to the normal kernel based on the absolute coordinates of the normal kernel includes:

Based on the absolute coordinates of the normal cores and the computing capability parameter of the normal cores, a target number of the compilation result groups included in the current grouping result are grouped and mapped to the normal cores.

In some embodiments, the method is applied to a target chip; the method further includes:

The algorithm compilation result sent by the electronic device outside the target chip is received.

In some embodiments, the method is applied to an electronic device external to the target chip, and the method further includes:

Compile the algorithm to be carried by the target chip to obtain the algorithm compilation result.

In some embodiments, the method is applied to an electronic device outside the target chip, and the algorithm compilation result corresponding to the target chip is grouped based on the fault processing core information, so as to obtain the current grouping result, the The method also includes:

The current grouping result and the algorithm compilation result are sent to the target chip, so that the normal core of the target chip implements the algorithm for preparing the bearer based on the current grouping result and the algorithm compilation result.

Based on the fault processing core information of each target chip in the multiple target chips and the respective corresponding algorithm compilation results, determine the same type of chips; wherein, the fault processing core information in the multiple target chips is consistent and the corresponding algorithm compilation results are consistent. called the same chip;

After performing grouping processing on the algorithm compilation result corresponding to the target chip based on the fault processing core information to obtain the current grouping result, the method further includes:

The current grouping result is used as the current grouping result corresponding to the same chip of the target chip.

In some embodiments, the method is applied to an electronic device outside the target chip, the fault processing core information includes absolute coordinates of the faulty core; the algorithm corresponding to the target chip based on the target number of the normal cores After the compilation results are grouped to obtain the current grouping results, the method further includes:

Obtain the absolute coordinates of the normal core according to the absolute coordinates of the faulty core;

One-to-one correspondence between the compilation result grouping and the absolute coordinates of the normal core is obtained, and the corresponding relationship between the compilation result grouping and the absolute coordinates of the normal core is obtained;

Based on the corresponding relationship between the compilation result grouping and the absolute coordinates of the normal core, route compilation is performed on the route of the target chip, and the route compilation result is obtained;

Sending the current grouping result, the routing compilation result and the algorithm compilation result to the target chip.

In a second aspect, an embodiment of the present disclosure provides a compiling apparatus, including:

an acquisition module, configured to acquire fault processing core information of a target chip; the target chip includes multiple processing cores, and the multiple processing cores include normal cores and/or faulty cores;

a decision-making module, configured to determine whether the target chip meets the regrouping condition based on the fault processing core information and the preset fault information;

The processing module is configured to perform grouping processing on the algorithm compilation result corresponding to the target chip based on the fault processing core information under the condition that the target chip meets the regrouping condition, so as to obtain a current grouping result, so that the The normal core of the target chip implements the algorithm to be carried by the current grouping result and the algorithm compilation result; wherein the algorithm compilation result includes an executable file corresponding to the algorithm to be carried by the target chip.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the embodiment of the present disclosure when executing the computer program Either compilation method.

In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements any one of the compilation methods in the embodiment of the present disclosure.

The compilation method provided by the embodiments of the present disclosure can improve the flexibility of the chip usage process, ensure that the faulty core of the target chip does not need to process the algorithm compilation result, and thus effectively avoid the situation that the target chip cannot implement the algorithm prepared for carrying due to the faulty core. Effectively improve the utilization of chip resources and reduce the manufacturing cost of chips.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a flowchart of a compilation method provided by an embodiment of the present disclosure.

FIG. 2 is a flowchart of a grouping processing method provided by an embodiment of the present disclosure.

FIG. 3 is a flowchart of a compilation method provided by an embodiment of the present disclosure.

FIG. 4 is a flowchart of a compilation method applied to a target chip according to an embodiment of the present disclosure.

FIG. 5 is a flowchart of a compiling method applied to a target chip according to an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a compilation method applied to a target chip according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a compilation method applied to a target chip according to an embodiment of the present disclosure.

FIG. 8 is a flowchart of a compilation method applied to an electronic device outside a target chip according to an embodiment of the present disclosure.

FIG. 9 is a flowchart of a compilation method applied to an electronic device outside a target chip according to an embodiment of the present disclosure.

FIG. 10 is a schematic diagram of a compilation method applied to an electronic device outside a target chip according to an embodiment of the present disclosure.

FIG. 11 is a schematic diagram of a compilation method applied to an electronic device outside a target chip according to an embodiment of the present disclosure.

FIG. 12 is a schematic diagram of a compilation method applied to an electronic device outside a target chip according to an embodiment of the present disclosure.

FIG. 13 is a flowchart of a compilation method applied to an electronic device outside a target chip according to an embodiment of the present disclosure.

FIG. 14 is a schematic diagram of a compiling apparatus in an embodiment of the disclosure.

FIG. 15 is a block diagram of an electronic device according to an embodiment of the present disclosure.

Detailed ways

The present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure, but not to limit the present disclosure. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all structures related to the present disclosure.

In a first aspect, an embodiment of the present disclosure provides a compilation method.

The compiling method in the embodiment of the present disclosure may be executed by a corresponding compiling apparatus, which may be implemented in software and/or hardware, and may generally be integrated into an electronic device. The electronic device may be an electronic device where the target chip is located, or may be an electronic device outside the target chip, which is not limited in the present disclosure.

FIG. 1 is a flowchart of a compilation method provided by an embodiment of the present disclosure. Referring to FIG. 1 , the compiling method according to the embodiment of the present disclosure includes the following steps S101-S103.

Step S101 , acquiring fault processing core information of the target chip.

The target chip is a chip including multiple processing cores, such as a many-core chip or a multi-core chip. The multiple processing cores of the target chip include normal cores and/or faulty cores. The faulty core is a processing core in the target chip that is faulty or temporarily unavailable due to various reasons. The faulty core is, for example, a processing core that fails due to manufacturing reasons, a processing core that fails during the use of the chip, or a processing core that fails due to overheating or errors. A processing core that cannot be used temporarily; a normal core is a processing core in the target chip that can normally perform computing tasks. It should be noted that, since the processing core routing of the chip is not prone to failure, although the faulty core does not have the computing power, such as the ability to run the executable file corresponding to the algorithm, the faulty core usually still has the routing function, that is, the faulty core still has the routing function. information can be delivered.

The fault processing core information of the target chip refers to the information of the fault core in the target chip. The fault handling core information includes: the actual number of faulty cores, the absolute coordinates of the faulty core in the target chip, the identity document (ID) of the faulty core and other information.

After the target chip is manufactured and produced, the processing core information such as the total number of processing cores included in the target chip, the absolute coordinates and identification of each processing core have been determined, and these information will be written into the memory of the target chip. For example, write into one-time programmable memory (efuse). Basic information of the target chip is also stored in the memory of the target chip, for example, information such as power supply voltage, version number, production date, etc. that can be used by the target chip.

In some embodiments, after the target chip is fabricated, the target chip usually needs to be tested. Through the testing process of the target chip, it is possible to determine the fault processing core information of the target chip (such as the actual number of faulty cores, the absolute coordinates of the faulty core in the target chip, the ID of the faulty core, etc.), the fault processing of the target chip The core information is written into the memory of the target chip, eg, into the efuse of the target chip.

In one embodiment, the step of acquiring the fault handling core information of the target chip (step S101 above) includes: reading the one-time programmable memory of the target chip to obtain the fault handling core information of the target chip.

Step S102 , based on the fault processing core information and the preset fault information, determine whether the target chip meets the regrouping condition.

Wherein, the preset fault information is preset information of faulty cores of the target chip. The preset failure information includes one or more kinds of information, such as a processing core failure rate, a preset number of faulty cores, and preset coordinates of the faulty cores.

In some embodiments, the preset fault information can be set based on the characteristics of the target chip. The characteristics of the target chip are, for example, whether a processing core failure is likely to occur in the process of manufacturing the target chip, whether the manufacturing process for manufacturing the target chip is complicated, and the like. Take the manufacturing process of manufacturing the target chip as an example to illustrate: in the case of a simple manufacturing process for manufacturing the target chip, the parameter values such as the processing core failure rate or the preset number of faulty cores in the preset fault information can be set to a small value. Some, such as the processing core failure rate can be set to 5%, or, in the case that the target chip includes 100 processing cores, the preset number of faulty cores can be 5; in the case of complex manufacturing processes for the target chip, Parameter values such as the preset proportion of faulty cores or the preset number of faulty cores in the preset fault information can be set larger, for example, the processing core fault rate can be set to 10%, or, if the target chip includes 100 processing cores In this case, the preset number of faulty cores can be 10.

In one embodiment, after the preset fault information of the target chip is determined in the design stage of the target chip, the algorithm compilation result corresponding to the target chip may be grouped based on the preset fault information to obtain the preset grouping result.

The algorithm compilation result includes an executable file (eg, a binary executable file) corresponding to the algorithm prepared to be carried by the target chip. The algorithm to be carried by the target chip refers to the algorithm to be implemented on the target chip. The algorithm is a method and process for solving a problem, and it is a piece of logic, while the target chip is a physical device that actually implements the method and process for solving the problem. The process of converting the pre-hosted algorithm into an executable file is the process of compiling the pre-hosted algorithm.

The target chip can implement the pre-carried algorithm by running the executable file corresponding to the pre-carried algorithm. Since the target chip is a chip including multiple processing cores, it is the multiple processing cores of the target chip that finally execute the executable file corresponding to the algorithm. Therefore, in this embodiment, by estimating a certain processing core failure rate or a preset number of faulty cores in the chip design stage, and then grouping the algorithm compilation results including the executable file based on the preset failure information, the The algorithm compilation result is divided into multiple compilation result groups, and each compilation result group is used to indicate the executable file to be mapped to a normal core for execution, which can facilitate the preset normal cores in the multiple processing cores of the target chip based on the preset grouping The result and the algorithm compilation result implement the algorithm for preparatory bearing, and ensure that in the case of certain faults in the multiple processing cores of the target chip, the preset grouping results of the algorithm compilation result corresponding to the target chip can still be used, which can improve the performance of the target chip. The utilization rate is reduced, the waste of target chip resources is reduced, and the cost of chip manufacturing is also reduced.

The regrouping condition includes whether it is necessary to perform grouping processing on the algorithm compilation result corresponding to the target chip again. It should be noted that, since the preset number of fault processing cores is determined according to the characteristics of the target chip, that is to say, for multiple target chips manufactured in batches, the actual number of fault cores of most target chips may be The preset number, that is, the preset grouping result can be used as the grouping result of most target chips, which greatly reduces the compilation workload of the chip and saves the computing resources of the chip. However, in an actual application process, there may be differences between the preset fault information and the fault processing core information of the target chip. In many cases where there is a difference between the preset fault information and the fault processing core information, the target chip cannot implement the pre-loading algorithm based on the preset grouping results and algorithm compilation results, and the target chip may be discarded, which will still cause a waste of chip resources. Therefore, in order to further improve the utilization rate of the target chip, reduce the waste of target chip resources, and reduce the manufacturing cost of the target chip, it is necessary to regroup the algorithm compilation results.

In one embodiment, the above-mentioned step of determining whether the target chip meets the regrouping condition based on the fault processing core information and the preset fault information (the above-mentioned step S102 ) includes:

Determine whether the actual number of faulty cores in the fault handling core information is greater than the preset number of faulty cores in the preset fault information. When the actual number of faulty cores is greater than the preset number of faulty cores, it is determined that the target chip meets the regrouping condition; when the actual number of faulty cores is less than or equal to the preset number of faulty cores, it is determined that the target chip does not meet the regrouping condition. grouping conditions.

Among them, the actual number of faulty cores in the fault processing core information is greater than the preset number of faulty cores in the preset fault information, indicating that the failure rate of the processing cores in the target chip is higher than expected, and the target chip cannot be based on the preset grouping results and algorithms. The compilation result implements the algorithm for preparing the bearer. Therefore, when the actual number of faulty cores is greater than the preset number of faulty cores, it is determined that the target chip meets the regrouping condition.

The actual number of faulty cores in the fault processing core information is less than or equal to the preset number of faulty cores in the preset fault information, indicating that the failure rate of the processing cores in the target chip is not higher than expected, and the target chip can be based on the preset grouping results and algorithms. The compilation result implements the algorithm for preparing the bearer. Therefore, it is not necessary to regroup the algorithm compilation result, that is, it is determined that the target chip does not meet the regrouping condition.

In an implementation scenario, the target chip has 100 processing cores, and the estimated processing core failure rate of the target chip is 5%, that is, it is estimated that among the 100 processing cores of the target chip, 5 processing cores are faulty and 95 are normal. nuclear. When the actual number of faulty cores in the target chip is less than or equal to 5, the actual number of normal cores in the target chip is greater than or equal to 95, and the 95 normal cores in the target chip can still be compiled based on the preset grouping results and algorithm results After implementing the algorithm for preparing the bearer, the target chip can still be used continuously, that is, it is determined that the target chip does not meet the regrouping conditions. When the actual number of faulty cores in the target chip is greater than 5, and the actual number of normal cores in the target chip is less than 95, the pre-loading algorithm cannot be implemented based on the preset grouping results and algorithm compilation results, and the target chip cannot continue For use, the algorithm compilation result corresponding to the target chip needs to be regrouped, that is, it is determined that the target chip meets the regrouping condition.

In another embodiment, the above-mentioned step of determining whether the target chip meets the regrouping condition based on the fault processing core information and the preset fault information (the above-mentioned step S102 ) includes:

Determine whether the actual number of fault cores in the fault handling core information is consistent with the preset number of fault cores in the preset fault information. When the actual number of faulty cores is inconsistent with the preset number of faulty cores, it is determined that the target chip meets the regrouping conditions; when the actual number of faulty cores is consistent with the preset number of faulty cores, it is determined that the target chip does not meet the regrouping conditions. grouping conditions.

Wherein, the actual number of faulty cores is inconsistent with the preset number of faulty cores, which indicates that there is a difference between the fault situation in the multiple processing cores of the target chip and the preset fault situation. In order to improve the utilization rate of the processing cores in the target chip, in the case where there is a difference between the fault conditions in the multiple processing cores of the target chip and the preset fault conditions, the algorithm compilation results corresponding to the target chip can be regrouped deal with. In the case where the actual number of faulty cores is consistent with the preset number of faulty cores, it means that there is no difference between the faults in the multiple processing cores of the target chip and the preset faults, and the utilization rate of the processing cores can be ensured. In this case, the algorithm for preparing the bearer is implemented based on the preset grouping result and the algorithm compilation result.

In an implementation scenario, the target chip has 100 processing cores, and the estimated processing core failure rate of the target chip is 5%, that is, it is estimated that among the 100 processing cores of the target chip, 5 processing cores are faulty and 95 are normal. nuclear. Since the preset grouping result is obtained based on the preset fault information, in fact, only 95 normal cores in the target chip are needed to implement the algorithm for preparing the bearer based on the preset grouping result and the algorithm compilation result. When the actual number of faulty cores is inconsistent with the preset number of faulty cores, for example, when the actual number of faulty cores in the target chip is 2, the actual number of normal cores in the target chip is 98, but Only 95 normal cores need to be used to realize the algorithm that the target chip is ready to carry. Therefore, in order to improve the utilization rate of the processing cores, the algorithm compilation results corresponding to the target chip can be regrouped.

The advantages of the two methods for determining whether the target chip meets the regrouping condition provided by this embodiment are different. The method of determining whether the target chip meets the regrouping conditions according to the relationship between the actual number of faulty cores and the preset number is compared with the method of determining whether the target chip meets the regrouping conditions by whether the actual number of faulty cores is consistent with the preset number. In this way, the compilation workload of the chip can be further reduced, and the computing resources of the chip can be saved. The method of determining whether the target chip meets the regrouping conditions by whether the actual number of faulty cores is consistent with the preset number is compared with the method of determining whether the target chip meets the regrouping conditions through the relationship between the actual number of faulty cores and the preset number. In this way, the utilization rate of the processing cores in the target chip can be improved. Therefore, in the actual application process, an appropriate method for determining whether the target chip meets the regrouping condition can be selected based on a specific scenario.

Step S103, in the case that the target chip meets the regrouping condition, based on the fault processing core information, perform grouping processing on the algorithm compilation result corresponding to the target chip to obtain the current grouping result, so that the normal core of the target chip is based on the current grouping result and The algorithm compilation result implements the algorithm for preparing the bearer.

The fault processing core information includes: the actual number of faulty cores, the absolute coordinates of the faulty core in the target chip, the identity document (ID) of the faulty core and other information.

The algorithm compilation result includes executable files (eg, binary executable files) corresponding to the algorithms prepared to be carried by the target chip.

The grouping processing of the algorithm compilation results is to divide the algorithm compilation results into multiple compilation result groups, and the current grouping result is the grouping result of grouping the algorithm compilation results. The current grouping result corresponding to the target chip is the compilation result of the algorithm corresponding to the target chip divided into the compilation result that can be executed by the normal core of the target chip.

The algorithm to be carried by the target chip refers to the algorithm to be implemented on the target chip. The algorithm is a method and process for solving a problem, and it is a piece of logic, while the target chip is a physical device that actually implements the method and process for solving the problem. The process of converting the pre-hosted algorithm into an executable file is the process of compiling the pre-hosted algorithm.

FIG. 2 is a flowchart of a grouping processing method provided by an embodiment of the present disclosure. In one embodiment, referring to FIG. 2 , the above-mentioned steps of performing grouping processing on the algorithm compilation result corresponding to the target chip to obtain the current grouping result include the following steps S201-S202.

Step S201: Determine the target number of normal cores based on the actual number of faulty cores.

The target number of normal cores is the difference between the total number of processing cores in the target chip and the actual number of faulty cores.

Step S202: Based on the target number of normal cores, perform grouping processing on the algorithm compilation result corresponding to the target chip to obtain the current grouping result.

The current grouping result includes a target number of compilation result groups, and each compilation result group is used to indicate an executable file to be mapped to a normal core for execution.

In this embodiment, the algorithm compilation result includes an executable file corresponding to the algorithm prepared to be carried by the target chip, and the target chip can implement the algorithm to be carried by running the executable file corresponding to the algorithm prepared to be carried. Since the target chip is a chip including multiple processing cores, the executable file corresponding to the algorithm is finally executed by a normal processing core among the multiple processing cores of the target chip. Therefore, in this embodiment, performing grouping processing (or folding processing) on the algorithm compilation results corresponding to the target chip is to divide the algorithm compilation results into compilation result groups for execution by the target number of normal cores.

In some embodiments, the algorithm compilation results may include compilation results performed by a plurality of numbers (eg, a first number) of processing cores. In general, the first number is greater than the target number of the above-mentioned normal cores, and the grouping process may group the compilation results performed by a plurality of (for example, the first number) processing cores, and the compilation results that are grouped into the same group are determined by the target A normal core of the chip to execute. For example, the algorithm compilation result corresponding to the target chip includes executable files for execution by 500 processing cores, and the target chip has 100 processing cores, including 6 faulty processing cores and 94 non-faulty processing cores. Then, the algorithm compilation result is grouped and divided into 94 compilation result groups, and the executable file corresponding to each compilation result group is executed by a normal core.

The compilation method provided by the embodiment of the present disclosure firstly acquires fault processing core information of a target chip, where the target chip includes multiple processing cores, and the multiple processing cores include normal cores and/or faulty cores; then, based on the fault processing core information and a preset The fault information is used to determine whether the target chip meets the regrouping conditions; if the target chip meets the regrouping conditions, based on the fault processing core information, the algorithm compilation results corresponding to the target chip are grouped to obtain the current grouping results, so that the target chip Based on the current grouping results and algorithm compilation results, the normal core implements the algorithm for preparing the bearer, which can improve the flexibility of the chip usage process and ensure that the faulty core of the target chip does not need to process the algorithm compilation result, thereby effectively avoiding the target chip. The implementation of the algorithm for pre-loading can effectively improve the utilization rate of chip resources and reduce the manufacturing cost of the chip.

FIG. 3 is a flowchart of a compilation method provided by an embodiment of the present disclosure. In one embodiment, referring to FIG. 3 , the compiling method further includes the following step S104.

Step S104 , in the case that the target chip does not meet the regrouping conditions, use the preset grouping result as the current grouping result, so that the normal core of the target chip implements the algorithm for preparing the bearer based on the current grouping result and the algorithm compilation result.

Wherein, the target chip does not meet the regrouping conditions, which means that the normal core of the target chip can implement the algorithm for preparing the bearer based on the preset grouping result and the algorithm compilation result. Therefore, it is not necessary to regroup the algorithm compilation results, but directly use the preset grouping results as the current grouping results, so that the normal core of the target chip can implement the preparatory bearer algorithm based on the current grouping results and the algorithm compilation results, and speed up the implementation of the algorithm in the target The implementation process on the chip.

It should be noted that, since the preset number of faulty cores is determined according to the characteristics of the target chip, that is to say, in the batch-manufactured multiple target chips, the number of faulty cores of most of the target chips may be the predetermined number. Set the number, that is, most of the target chips do not meet the regrouping conditions. The preset grouping result can be used as the current grouping result of most target chips, which can greatly reduce the compilation workload of the chip.

In one embodiment, in the process of setting the preset fault information, a variety of different preset fault information can be set, for example, preset fault information with different preset numbers of multiple fault cores can be set.

Based on each preset fault information, the algorithm compilation result corresponding to the target chip is grouped to obtain multiple preset grouping results.

In the above step of determining whether the target chip meets the regrouping condition based on the fault processing core information and the preset fault information, if the target chip does not meet the regrouping condition for a certain preset fault information among a variety of different preset fault information , it is determined that the target chip does not meet the regrouping condition, and if the target chip meets the regrouping condition for all preset fault information, it is determined that the target chip meets the regrouping condition. The step of determining whether the target chip meets the regrouping condition may refer to the foregoing embodiments, which will not be repeated here.

Wherein, when the target chip does not meet the regrouping condition for the first preset fault information, extracts the first preset grouping result corresponding to the first preset fault information from a plurality of preset grouping results, and assigns the first preset fault information to the Set the grouping result as the current grouping result of the target chip.

In this embodiment, by estimating a variety of different preset fault information in the chip design stage, it is ensured that in the case of a certain fault in the multiple processing cores of the target chip, the preset grouping of the algorithm compilation results corresponding to the target chip The result can still be used, which can improve the utilization rate of the target chip, reduce the waste of target chip resources, and also reduce the cost of chip manufacturing.

FIG. 4 is a flowchart of a compilation method applied to a target chip according to an embodiment of the present disclosure. In one embodiment, referring to FIG. 4 , the method is applied to a target chip, and based on the target number of the normal cores, the algorithm compilation result corresponding to the target chip is grouped to obtain the current grouping result (step After S103), the compiling method further includes: the following steps S401-S402.

Step S401 , according to the absolute coordinates of the faulty core, determine the absolute coordinates of the normal core.

The fault processing core information further includes the absolute coordinates of the fault core.

In some embodiments, a unit with computing capability in the target chip, such as the chip's ARM (Advanced RISC Machine) or APU (Accelerated Processing Unit, accelerated processor), extracts the information from the fault processing core The absolute coordinates of the faulty core are determined, and the absolute coordinates of the normal cores are determined according to the absolute coordinates of each processing core of the target chip, wherein the absolute coordinates of each processing core of the target chip are stored in the efuse of the target chip.

Step S402 , based on the absolute coordinates of the normal cores, group-map the target number of compilation results included in the current grouping result to the normal cores, wherein the absolute coordinates of the normal cores mapped by any two compilation result groups are different from each other.

The current grouping result is a grouping result of grouping the algorithm compilation results, and grouping the algorithm compilation results corresponding to the target chip is to divide the algorithm compilation results into compilation results that can be executed by multiple normal cores of the target chip. Since the target chip is a chip that integrates multiple processing cores, the final execution algorithm compilation result (that is, the executable file) is the processing core of the target chip. Therefore, after obtaining the current grouping result, the target number included in the current grouping result needs to be The compilation results are grouped and mapped to normal cores. However, in the current grouping result, each compilation result grouping indicates that the group of executable files is to be mapped to which normal core for execution is not determined. Therefore, after obtaining the current grouping result, the ARM or APU of the target chip can be based on the normal core. The absolute coordinates determine to which normal core execution each compilation result grouping in the current grouping result is mapped to.

In an implementation scenario, the target chip has 100 processing cores, including 6 faulty cores and 94 normal cores, then the current grouping result The current grouping result includes 94 compilation result groups, and each compilation result group is used to indicate to be mapped to An executable file for normal kernel execution. The above-mentioned process of mapping the target number of compilation result groups included in the current grouping result to the normal kernel based on the absolute coordinates of the normal kernel is to assign a normal kernel corresponding to a certain absolute coordinate to each compilation result group in the current grouping result, for example , assign the normal core with absolute coordinates (1,1) to the first compilation result group, then the first compilation result group is used to indicate the executable to be mapped to the normal core execution with absolute coordinates (1,1) file; assign a normal core with absolute coordinates (1,2) to the second compilation result group, then the second compilation result group is used to indicate the executable to be mapped to the normal core with absolute coordinates (1,2). executable file. By analogy, the mapping process of each compilation result grouping can be implemented.

In this implementation scenario, when the target chip actually executes the executable file corresponding to the compilation result grouping, the normal core whose absolute coordinate is (1,1) first executes the executable file corresponding to the first compilation result grouping, and executes the executable file corresponding to the first compilation result grouping. The result is sent to other normal cores according to the routing file, such as the normal core with absolute coordinates (1,2), and the processing core with absolute coordinates (1,2) that receives the execution result, and executes the second compilation result according to the execution result The corresponding executable files are grouped, and so on, until all normal cores have finished executing the executable files corresponding to the grouping of compilation results mapped to them, and the algorithm to be prepared is implemented. It should be noted that the routing file may be the execution result transmission path file that is simultaneously determined by the target chip in the above-mentioned mapping process.

In one embodiment, based on the absolute coordinates of the normal cores, the step of grouping and mapping the target number of compilation results included in the current grouping result to the normal cores (step S402 ) includes: based on the absolute coordinates of the normal cores and the computing capability of the normal cores parameter, which maps the target number of compilation result groups included in the current grouping result to normal cores.

The ARM or APU of the target chip respectively obtains the computing capability parameter of the normal core according to the absolute coordinates of the normal core.

Since the multiple processing cores of the target chip cooperate with each other, in the process of grouping and mapping the target number of compilation results included in the current grouping result to the normal cores, it is necessary to consider not only the rationality of the calculation amount of each normal core, but also the normal The efficiency of cooperation between cores, such as data transmission and information transfer efficiency. The rationality of the calculation amount of the normal core can be obtained according to the calculation capability parameter of the normal core, and the calculation amount divided into each normal core should match the standard calculation amount that the normal core can provide.

For example, the standard calculation amount that a normal core can provide is A (MB). According to actual use experience, the actual calculation amount of the normal core is 70%-80% of the standard calculation amount. If it is too small, the performance of the target chip will be wasted, and if the actual calculation amount is too large, it will cause an excessive computational load of the target chip. Therefore, with reference to the standard calculation amount of the normal core, the target number of compilation result groups included in the current grouping result can be reasonably mapped to the normal core. In addition, the data transmission efficiency between any two normal cores can be obtained according to the absolute coordinates of the normal cores. The farther the two normal cores are, the longer it takes to transmit data and the lower the transmission efficiency. In the process of mapping the target number of compiling result groups included in the grouping result to normal cores, two compiling result groups that require data transmission should be mapped to two normal cores that are close to each other as much as possible.

FIG. 5 is a flowchart of a compiling method applied to a target chip according to an embodiment of the present disclosure. In one embodiment, referring to FIG. 5 , the compiling method includes the following steps S501-S506.

Step S501: Receive an algorithm compilation result sent by an electronic device outside the target chip.

The target chip is a chip including multiple processing cores, such as a many-core chip or a multi-core chip. The electronic device outside the target chip is an external electronic device that has a connection relationship with the target chip, such as a device connected to the target chip with one or more functions of compiling, chip testing, reading and writing, etc. , the external electronic device may be a server or a terminal.

The algorithm compilation result includes executable files (eg, binary executable files) corresponding to the algorithms prepared to be carried by the target chip. The algorithm to be carried by the target chip refers to the algorithm to be implemented on the target chip. The algorithm is a method and process for solving a problem, and it is a piece of logic, while the target chip is a physical device that actually implements the method and process for solving the problem. The electronic device outside the target chip is used to convert the algorithm prepared to be carried by the target chip into an executable file executable by the target chip. compilation process.

Step S502 , acquiring fault processing core information of the target chip.

Wherein, the fault processing core information of the target chip refers to the information of the fault core in the target chip. The fault handling core information includes: the actual number of faulty cores, the absolute coordinates of the faulty core in the target chip, the identity document (ID) of the faulty core and other information.

In some embodiments, the ARM or APU of the target chip can read the one-time programmable memory of the target chip to obtain fault processing core information of the target chip.

After the target chip is manufactured and produced, the processing core information such as the total number of processing cores included in the target chip, the absolute coordinates and identification of each processing core have been determined, and these information will be written into the memory of the target chip. For example, writing into one-time programmable memory. Basic information of the target chip is also stored in the memory of the target chip, for example, information such as power supply voltage, version number, production date, etc. that can be used by the target chip.

After the target chip is fabricated, the target chip usually needs to be tested. Through the testing process of the target chip, it is possible to determine the fault processing core information of the target chip (such as the actual number of faulty cores, the absolute coordinates of the faulty core in the target chip, the ID of the faulty core, etc.), the fault processing of the target chip The core information is written into the memory of the target chip, eg, into the efuse of the target chip.

Step S503 , based on the fault processing core information and the preset fault information, determine whether the target chip meets the regrouping condition.

In some embodiments, the preset fault information can be set based on the characteristics of the target chip. The characteristics of the target chip are, for example, whether a processing core failure is likely to occur in the process of manufacturing the target chip, whether the manufacturing process for manufacturing the target chip is complicated, and the like.

In some embodiments, after determining the preset fault information of the target chip, the electronic device outside the target chip sends the preset fault information to the target chip; after the target chip receives the preset fault information sent by the external electronic device , the algorithm compilation result corresponding to the target chip can be grouped based on the preset fault information to obtain the preset grouping result.

In other embodiments, the electronic device outside the target chip may also, after determining the preset fault information of the target chip, perform grouping processing on the algorithm compilation result corresponding to the target chip based on the preset fault information, and obtain the preset grouping result , and send the preset grouping result to the target chip.

The target chip may implement the pre-carried algorithm by running the executable file corresponding to the pre-carried algorithm. Since the target chip is a chip including multiple processing cores, it is the multiple processing cores of the target chip that finally execute the executable file corresponding to the algorithm. Therefore, in this embodiment, by estimating a certain processing core failure rate or a preset number of faulty cores, and then based on the preset failure information, the algorithm compilation results including the executable file are grouped and processed, and the algorithm compilation results are divided into groups. Grouping multiple compilation results, each compilation result group is used to indicate an executable file to be mapped to a normal core for execution, which can facilitate the compilation of the preset normal cores in the multiple processing cores of the target chip based on the preset grouping results and algorithms As a result, the algorithm for pre-loading is implemented, and in the case of certain failures in the multiple processing cores of the target chip, the preset grouping results of the algorithm compilation results corresponding to the target chip can still be used, which can improve the utilization rate of the target chip and reduce the The waste of target chip resources also reduces the cost of chip manufacturing.

The regrouping condition includes whether it is necessary to perform grouping processing on the algorithm compilation result corresponding to the target chip again. The steps of how to determine whether the target chip meets the regrouping condition can be found in the foregoing embodiments, which will not be repeated here. In the actual application process, there may be differences between the preset fault information and the fault processing core information of the target chip. In many cases where there is a difference between the preset fault information and the fault processing core information, the target chip cannot implement the pre-loading algorithm based on the preset grouping results and algorithm compilation results, and the target chip may be discarded, which will still cause a waste of chip resources. Therefore, in order to further improve the utilization rate of the target chip, reduce the waste of target chip resources, and reduce the manufacturing cost of the target chip, it is necessary to regroup the algorithm compilation results.

Step S504 , in the case that the target chip meets the regrouping condition, based on the fault processing core information, perform grouping processing on the algorithm compilation result corresponding to the target chip to obtain the current grouping result.

Step S505 , in the case that the target chip does not meet the regrouping condition, use the preset grouping result as the current grouping result.

In this embodiment, since the preset number of faulty cores is determined according to the characteristics of the target chip, that is to say, among multiple target chips manufactured in batches, the number of faulty cores of most of the target chips may be the predetermined number. Set the number, that is, most of the target chips do not meet the regrouping conditions. The preset grouping result can be used as the current grouping result of most target chips, which can greatly reduce the compilation workload of the chip and save the computing resources of the target chip.

Step S506 , grouping and mapping the target number of compilation results included in the current grouping result to normal cores.

Among them, the absolute coordinates of the normal kernels mapped by any two compilation result groups are different from each other.

The steps of grouping and mapping the target number of compilation results included in the current grouping result to normal cores may refer to the foregoing embodiments, which will not be repeated here.

The compiling method provided by the embodiment of the present disclosure can improve the flexibility of the chip usage process, ensure that the faulty core of the target chip does not need to process the algorithm compilation result, and thus effectively avoid the situation that the target chip cannot implement the algorithm prepared for carrying due to the faulty core. It can effectively improve the utilization rate of chip resources and reduce the manufacturing cost of the chip.

FIG. 6 is a schematic diagram of a compilation method applied to a target chip according to an embodiment of the present disclosure. 6, the target chip 61 includes a plurality of processing cores 62, the target chip 61 performs grouping processing on the algorithm compilation result, obtains the current grouping result, and maps the current grouping result to the normal core of the target chip.

FIG. 7 is a schematic diagram of a compilation method applied to a target chip according to an embodiment of the present disclosure. 7, the ARM or APU of the target chip obtains the algorithm compilation result, groups the algorithm compilation results according to the actual number of faulty cores, obtains the current grouping result, and maps the current grouping result to the normal cores of the target chip. Among them, the current grouping results and algorithm compilation results can be stored in the storage space of the target chip, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR, Double Data Rate Synchronous Dynamic Random Access Memory).

FIG. 8 is a flowchart of a compilation method applied to an electronic device outside a target chip according to an embodiment of the present disclosure. In one embodiment, referring to FIG. 8 , the compiling method further includes: the following steps S801-S802.

Step S801 , compiling the algorithm to be carried by the target chip to obtain an algorithm compilation result.

Among them, the algorithm to be carried by the target chip refers to the algorithm to be implemented on the target chip. The algorithm is the method and process of solving the problem, and it is a piece of logic, and the target chip is the physical device that actually implements the method and process of solving the problem. . The target chip implements the pre-carried algorithm by running an executable file (eg, a binary executable file) that corresponds to the pre-carried algorithm and is executable by the target chip. The process of converting the pre-loaded algorithm into an executable file is the process of compiling the pre-loaded algorithm, and the executable file executable by the target chip is the algorithm compilation result.

In one embodiment, after obtaining the algorithm compilation result, the electronic device outside the target chip may obtain the current grouping result based on the above steps S101-S103. For the process of obtaining the current grouping result, reference may be made to the foregoing embodiments, and details are not described herein again. After obtaining the current grouping result, the electronic device outside the target chip further includes the following step S802.

Step S802: Send the current grouping result and the algorithm compilation result to the target chip, so that the normal core of the target chip implements the algorithm for preparing the bearer based on the current grouping result and the algorithm compilation result.

The current grouping result includes multiple compilation result groups, and each compilation result group is used to indicate an executable file to be mapped to a normal core for execution. The algorithm compilation result includes an executable file corresponding to the algorithm prepared to be carried by the target chip.

The process for the normal core of the target chip to implement the algorithm for preparing the bearer based on the current grouping result and the algorithm compiling result may refer to the foregoing embodiments, which will not be repeated here.

In this embodiment, since each compilation result group in the current grouping result is used to indicate an executable file to be mapped to a normal core for execution, the chip can group the compilation result after receiving the current grouping result and the algorithm compilation result The corresponding executable file is mapped to the normal core, but not to the faulty core, which can ensure that the faulty core of the target chip does not need to process the compilation result of the algorithm, thereby effectively avoiding the situation that the target chip cannot implement the algorithm prepared for carrying due to the faulty core. , which can effectively improve the utilization rate of chip resources and reduce the manufacturing cost of chips.

FIG. 9 is a flowchart of a compilation method applied to an electronic device outside a target chip according to an embodiment of the present disclosure. In an implementation scenario, for a multi-target chip architecture, referring to FIG. 9 , the compilation method further includes the following steps S901-S903.

Step S901 , based on the fault processing core information of each target chip in the plurality of target chips and the respective corresponding algorithm compilation results, determine the same type of chips.

Among them, among the multiple target chips, the target chips whose fault processing core information is consistent and the corresponding algorithm compilation results are consistent are called similar chips.

In some embodiments, for a multi-target chip architecture, an electronic device outside the target chip may acquire information on fault processing cores of each target chip in the multiple target chips, where the fault processing core information includes a processing core failure rate, a fault processing core One or more kinds of information, such as the preset number and the preset coordinates of the fault core. In this embodiment, a target chip whose actual number of fault processing cores included in the fault processing core information in the multiple target chips is the same and whose corresponding algorithm compilation results are the same may also be referred to as the same type of chip.

Step S902 , in the case that the target chip meets the regrouping condition, based on the fault processing core information, perform grouping processing on the algorithm compilation result corresponding to the target chip to obtain the current grouping result.

The current grouping result is a grouping result of grouping the algorithm compilation results, and the grouping processing of the algorithm compilation results is that the algorithm compilation results are divided into compilation results that can be executed by a plurality of normal cores. The current grouping result of the target chip is to divide the algorithm compilation result into compilation results that can be executed by the normal core of the target chip.

Step S903, taking the current grouping result as the current grouping result corresponding to chips of the same type of the target chip.

In some implementation scenarios, for a structure including multiple target chips, after acquiring the fault handling core information of one or more target chips, the electronic device outside the target chip can, for each target chip, The core information is processed, the algorithm compilation result corresponding to the target chip is grouped, and the current grouping result corresponding to the target chip is obtained. With the compiling method of this embodiment, it is not necessary to perform the grouping processing of the algorithm compilation results once for each target chip, but only need to perform the grouping processing of the algorithm compilation results once for the same type of chips. In this embodiment, the electronic device outside the target chip can determine the same type of chip of the target chip from multiple chips. Since the same type of chip is the target chip with the same actual number of fault processing cores and the same corresponding algorithm compilation results, therefore, in the When a target chip meets the regrouping conditions, the same chips of the target chip also meet the regrouping conditions. The electronic device outside the target chip only needs to perform a grouping process on the algorithm compilation result according to the fault processing core information of the target chip. For the multi-target chip structure scenario, the compilation workload of the chip can be greatly reduced, the computing resources of external electronic devices can be saved, and the manufacturing cost of the chip can be reduced.

FIG. 10 , FIG. 11 , and FIG. 12 are schematic diagrams of a compilation method applied to an electronic device outside a target chip provided by an embodiment of the present disclosure. Referring to FIG. 10 , FIG. 11 , and FIG. 12 , the multi-chip architecture 1001 includes a plurality of target chips 1002 that are prepared to carry the same algorithm. The electronic device outside the target chip performs grouping processing on the algorithm compilation result corresponding to each target chip 1002 according to the fault processing core information of each target chip 1002, and obtains the current grouping result corresponding to each target chip 1002, as shown in Figure 10 and Figure 10. 11 and ID1, ID2, ID3...IDn in Figure 12.

In one embodiment, referring to FIG. 11 , the electronic device outside the target chip sends each current grouping result to the corresponding target chip 1002 . After receiving the current grouping result corresponding to itself, the target chip 1002 stores the current grouping result in its own DDR.

In some embodiments, for a multi-target chip architecture, an electronic device outside the target chip may, after obtaining the current grouping result corresponding to a target chip, send the obtained current grouping result to the target chip, and then obtain the next target The current grouping result corresponding to the chip.

In other embodiments, for the multi-target chip architecture, the electronic device outside the target chip may, after obtaining the current grouping results corresponding to all target chips, send the obtained current grouping results to the corresponding target chips respectively.

In the compilation method provided by the embodiment of the present disclosure, in the architecture of a multi-target chip, the normal core of each target chip is an algorithm that implements a preparatory bearer based on its corresponding current grouping result and algorithm compilation result, so it can ensure the failure of the target chip. The core does not need to process the algorithm compilation result, thereby effectively avoiding the situation that the target chip cannot implement the algorithm prepared for carrying due to the faulty core, effectively improving the utilization of chip resources, reducing the manufacturing cost of the chip, and ensuring the stability of the multi-target chip architecture.

In another embodiment, referring to FIG. 12 , for a multi-target chip architecture, an electronic device outside the target chip can send all the current grouping results to each target chip after acquiring the current grouping results corresponding to all target chips, and each Each target chip can select its own corresponding current grouping result from all the current grouping results. Compared with the method of only sending the current grouping result corresponding to the target chip to each target chip, if the electronic device outside the target chip sends all the current grouping results to each chip, the electronic device sends the current grouping result to each target chip. The contents are the same, so after obtaining all the current grouping results, the electronic device can send the current grouping results to all target chips after one memory read.

In some embodiments, for any target chip that has received all the current grouping results, after the target chip has received all the current grouping results, the ARM or APU of the target chip has a computing capability, from all the current grouping results. The current grouping result corresponding to the own fault handling core information is extracted from the grouping result, and the algorithm for preparing the bearer is implemented based on the current grouping result and the algorithm compilation result. At the same time, the ARM or APU of the target chip can also save all the current grouping results. Although saving all the current grouping results will occupy the storage space of the chip, if the target chip has other failures during subsequent use (for example, a normal core becomes a faulty core), the ARM or APU of the target chip can directly An appropriate current grouping result is selected from a plurality of saved current grouping results, and an algorithm for preparatory bearer is implemented based on the re-selected current grouping result and the algorithm compilation result, which further improves the utilization of chip resources and reduces the cost of chip manufacturing. Of course, if the storage space of the target chip is insufficient, all the remaining current grouping results can also be directly discarded.

In the compilation method provided in this embodiment, after obtaining all the grouping results, all the current grouping results are sent to each target chip, which is equivalent to providing an alternative solution for the target chip, and the target chip can filter from multiple current grouping results Therefore, compared with the method of only sending the current grouping result corresponding to the chip to each chip, this method can improve the success rate of the algorithm for the target chip to implement the preparatory bearer, and avoid the target chip that cannot be used. The emergence of the situation has improved the utilization rate of chip resources and reduced the cost of chip manufacturing.

FIG. 13 is a flowchart of a compilation method applied to an electronic device outside a target chip according to an embodiment of the present disclosure. In one embodiment, based on the target number of normal cores, grouping processing is performed on the algorithm compilation results corresponding to the target chips to obtain the current grouping results (step S202 ). Referring to FIG. 13 , the compilation method further includes: the following step S1301 - Step S1304.

Step S1301: Acquire the absolute coordinates of the normal core according to the absolute coordinates of the faulty core.

In some embodiments, after the electronic device outside the target chip is connected to the target chip, the one-time programmable memory of the target chip is read to obtain the fault handling core information of the target chip. The fault processing core information includes: the actual number of faulty cores, the absolute coordinates of the faulty core in the target chip, and the identity of the faulty core. The electronic device outside the target chip can also obtain the absolute coordinates of all processing cores of the target chip from the one-time programmable memory of the target chip, and then obtain the absolute coordinates of the normal core based on the absolute coordinates of all the processing cores and the absolute coordinates of the faulty core. .

Step S1302 , make a one-to-one correspondence between the compilation result group and the absolute coordinates of the normal core, and obtain the corresponding relationship between the compilation result group and the absolute coordinates of the normal core.

Wherein, each compilation result group is used to indicate an executable file to be mapped to a normal core for execution. The correspondence between the compilation result group and the absolute coordinates of the normal core is used to indicate which normal core executes the executable file corresponding to the compilation result group.

In this embodiment, the current grouping result obtained after the algorithm compilation result is grouped includes multiple compilation result groups. It can be known from the foregoing description of grouping the algorithm compilation results that the number of compilation result groups included in the current grouping result is less than or equal to the target number of normal cores. Therefore, the same number of absolute coordinates as the number of compilation result groups can be selected from the target number of absolute coordinates, and an absolute coordinate of a normal core can be assigned to each compilation result group, so as to realize the combination of the compilation result group and the absolute coordinates of the normal core. One-to-one correspondence.

In an implementation scenario, the target chip has 100 processing cores, including 6 faulty cores and 94 normal cores, then the current grouping result The current grouping result includes 94 compilation result groups, and each compilation result group is used to indicate to be mapped to An executable for normal kernel execution. In this implementation scenario, the first compilation result can be grouped to correspond to absolute coordinates (1, 1); the second compilation result can be grouped to absolute coordinates (1, 2) ... until the compilation result is grouped with the normal The absolute coordinates of the cores are in one-to-one correspondence, and the corresponding relationship between the compilation result group and the absolute coordinates of the normal core is obtained. The corresponding relationship between the compilation result group and the absolute coordinates of the normal core is used to indicate which normal core executes the executable file corresponding to the compilation result group. 1,1) for normal kernel execution.

Step S1303 , based on the corresponding relationship between the compilation result group and the absolute coordinates of the normal core, perform route compilation on the route of the target chip, and obtain a route compilation result.

The process of routing and compiling the route of the target chip is the process of determining the order in which the normal core of the target chip executes the executable file and determining the execution result transmission path and other information. The routing compilation result includes information such as the order in which the normal core of the target chip executes the executable file and the execution result transmission path.

Step S1304: Send the current grouping result, the routing compilation result and the algorithm compilation result to the target chip, so that the target chip can implement the algorithm for preparing the bearer based on the current grouping result, the routing compilation result and the algorithm compilation result.

In an implementation scenario, in the process that the target chip implements the algorithm for preparing the bearer based on the current grouping result, the routing compilation result and the algorithm compilation result, the normal core whose absolute coordinate is (1,1) first executes the first compilation result corresponding to the grouping. Executable file, and send the execution result to the next normal core according to the routing compilation result (the route of the faulty core is generally not damaged, so the execution result can be transferred through the faulty core in the process of sending it to the next normal core), such as A normal kernel with absolute coordinates (1,2). Receive the normal core whose absolute coordinates of the execution result are (1, 2), execute the executable file corresponding to the second compilation result group according to the execution result, and so on, until all the normal cores corresponding to the compilation result grouping After executing the executable file corresponding to the compilation result group mapped to it, the algorithm to be carried is prepared to be implemented.

The compilation method provided by the embodiment of the present disclosure sends the current grouping result, the routing compilation result, and the algorithm compilation result to the target chip, so that the target chip can realize the pre-bearing algorithm based on the current grouping result, the routing compilation result and the algorithm compilation result, which can effectively The efficiency of the process of implementing the preparatory bearing algorithm for the target chip is improved, and the manufacturing cost of the chip is reduced.

It should be understood that the above embodiments can also be used in combination with any other manners of the embodiments of the present disclosure. The above embodiment is only a specific example of the present disclosure, rather than limiting the protection scope of the present disclosure.

In a second aspect, an embodiment of the present disclosure provides a compiling apparatus, which is a corresponding apparatus for implementing the compiling method provided by the above-mentioned embodiments of the present disclosure. The apparatus can be implemented in software and/or hardware, and can generally be integrated into electronic equipment. middle.

FIG. 14 is a schematic diagram of a compiling apparatus in an embodiment of the disclosure. Referring to FIG. 14 , a compilation apparatus provided by an embodiment of the present disclosure includes: an acquisition module 1401 , a decision module 1402 , and a processing module 1403 .

Among them, the obtaining module 1401 is used for obtaining the fault processing core information of the target chip.

The target chip is a chip including multiple processing cores, such as a many-core chip or a multi-core chip. The multiple processing cores of the target chip include normal cores and/or faulty cores. The faulty core is a processing core in the target chip that is faulty or temporarily unavailable due to various reasons. The faulty core is, for example, a processing core that fails due to manufacturing reasons, a processing core that fails during the use of the chip, or a processing core that fails due to overheating or errors. A processing core that cannot be used temporarily; a normal core is a processing core in the target chip that can normally perform computing tasks. It should be noted that since the routing of the processing core of the chip is not easy to fail, although the faulty core does not have the computing ability, such as the ability to run the executable file corresponding to the algorithm, the faulty core usually still has the routing function, that is, the faulty core can still Send message.

In one embodiment, the obtaining module 1401 reads the one-time programmable memory of the target chip to obtain the fault handling core information of the target chip.

The decision module 1402 is configured to determine whether the target chip meets the regrouping condition based on the fault processing core information and the preset fault information.

In this embodiment, the steps of determining whether the target chip meets the regrouping condition may refer to the foregoing embodiment, and details are not repeated here.

The processing module 1403 is configured to perform grouping processing on the algorithm compilation result corresponding to the target chip based on the fault processing core information under the condition that the target chip meets the regrouping condition, so as to obtain the current grouping result, so that the normal core of the target chip is based on the current The grouping result and the algorithm compilation result implement the algorithm for preparing the bearer.

In this embodiment, based on the fault processing core information, grouping processing is performed on the algorithm compilation result corresponding to the target chip, so as to obtain the current grouping result, reference may be made to the foregoing embodiment, which will not be repeated here.

In one embodiment, after the preset fault information of the target chip is determined in the design stage of the target chip, the processing module 1403 is further configured to perform grouping processing on the algorithm compilation results corresponding to the target chip based on the preset fault information, so as to obtain the preset fault information. Set the grouping result.

The target chip may implement the pre-carried algorithm by running the executable file corresponding to the pre-carried algorithm. Since the target chip is a chip including multiple processing cores, it is the multiple processing cores of the target chip that finally execute the executable file corresponding to the algorithm. Therefore, in this embodiment, by estimating a certain processing core failure rate or a preset number of faulty cores in the chip design stage, and then grouping the algorithm compilation results including the executable file based on the preset failure information, the The algorithm compilation result is divided into multiple compilation result groups, and each compilation result group is used to indicate the executable file to be mapped to a normal core for execution, which can facilitate the preset normal cores in the multiple processing cores of the target chip based on the preset grouping The result and the algorithm compilation result implement the algorithm for preparatory bearing, and ensure that in the case of certain faults in the multiple processing cores of the target chip, the preset grouping results of the algorithm compilation result corresponding to the target chip can still be used, which can improve the performance of the target chip. The utilization rate is reduced, the waste of target chip resources is reduced, and the cost of chip manufacturing is also reduced.

The regrouping condition includes whether it is necessary to perform grouping processing on the algorithm compilation result corresponding to the target chip again.

It should be noted that, since the preset number of fault processing cores is determined according to the characteristics of the target chip, that is to say, for multiple target chips manufactured in batches, the actual number of fault cores of most target chips may be The preset number, that is, the preset grouping result can be used as the grouping result of most target chips, which greatly reduces the compilation workload of the chip and saves the computing resources of the chip. However, in an actual application process, there may be differences between the preset fault information and the fault processing core information of the target chip. In many cases where there is a difference between the preset fault information and the fault processing core information, the target chip cannot implement the pre-loading algorithm based on the preset grouping results and algorithm compilation results, and the target chip may be discarded, which will still cause a waste of chip resources. Therefore, in order to further improve the utilization rate of the target chip, reduce the waste of target chip resources, and reduce the manufacturing cost of the target chip, it is necessary to regroup the algorithm compilation results.

In one embodiment, the processing module 1403 is further configured to use the preset grouping result as the current grouping result in the case that the target chip does not meet the regrouping condition, so that the normal core of the target chip can realize the realization based on the current grouping result and the algorithm compilation result Algorithms for preparing bearers.

In the compiling apparatus provided by the embodiment of the present disclosure, the acquisition module is used to acquire fault processing core information of a target chip, where the target chip includes multiple processing cores, and the multiple processing cores include normal cores and/or faulty cores; the decision module is used for fault-based processing Processing core information and preset fault information to determine whether the target chip meets the regrouping conditions; the processing module is used to perform grouping processing on the algorithm compilation results corresponding to the target chip based on the fault processing core information when the target chip meets the regrouping conditions , to obtain the current grouping result, so that the normal core of the target chip can realize the preparatory bearing algorithm based on the current grouping result and the algorithm compilation result, which can improve the flexibility of the chip usage process and ensure that the faulty core of the target chip does not need to process the algorithm compilation result, and then It can effectively avoid the situation that the target chip cannot implement the algorithm of the preparatory load due to the faulty core, effectively improve the utilization rate of chip resources, and reduce the manufacturing cost of the chip.

15 , an embodiment of the present disclosure provides an electronic device, the electronic device includes: at least one processor 1501 ; at least one memory 1502 , and one or more I/O interfaces 1503 connected between the processor 1501 and the memory 1502 wherein, the memory 1502 stores one or more computer programs executable by the at least one processor 1501, and the one or more computer programs are executed by the at least one processor 1501, so that the at least one processor 1501 can execute the above-mentioned compile method.

Embodiments of the present disclosure also provide a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above-mentioned compiling method when executed by a processor. Computer-readable storage media can be volatile or non-volatile computer-readable storage media.

Embodiments of the present disclosure also provide a computer program product, including computer-readable codes, or a non-volatile computer-readable storage medium carrying computer-readable codes, when the computer-readable codes are stored in a processor of an electronic device When running in the electronic device, the processor in the electronic device executes the above compiling method.

Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, functional modules/units in the systems, and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components Components execute cooperatively. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit . Such software may be distributed on computer-readable storage media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).

As is known to those of ordinary skill in the art, the term computer storage media includes both volatile and non-volatile memory media implemented in any method or technology for storage of information, such as computer readable program instructions, data structures, program modules or other data. volatile, removable and non-removable media. Computer storage media include, but are not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical disk storage, magnetic cartridge, magnetic tape, magnetic disk storage or other magnetic storage device, or which can be used to store desired information and which can be accessed by a computer any other medium. In addition, communication media typically embodies computer readable program instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery, as is well known to those of ordinary skill in the art medium.

The computer readable program instructions described herein may be downloaded to various computing/processing devices from a computer readable storage medium, or to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer-readable program instructions from a network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing/processing device .

Computer program instructions for carrying out operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or instructions in one or more programming languages. Source or object code, written in any combination, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as the "C" language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server implement. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (eg, using an Internet service provider through the Internet connect). In some embodiments, custom electronic circuits, such as programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can be personalized by utilizing state information of computer readable program instructions. Computer readable program instructions are executed to implement various aspects of the present disclosure.

The computer program product described herein may be embodied in hardware, software, or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), etc. Wait.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer or other programmable data processing apparatus to produce a machine that causes the instructions when executed by the processor of the computer or other programmable data processing apparatus , resulting in means for implementing the functions/acts specified in one or more blocks of the flowchart and/or block diagrams. These computer readable program instructions can also be stored in a computer readable storage medium, these instructions cause a computer, programmable data processing apparatus and/or other equipment to operate in a specific manner, so that the computer readable medium storing the instructions includes An article of manufacture comprising instructions for implementing various aspects of the functions/acts specified in one or more blocks of the flowchart and/or block diagrams.

Computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other equipment to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other equipment to produce a computer-implemented process , thereby causing instructions executing on a computer, other programmable data processing apparatus, or other device to implement the functions/acts specified in one or more blocks of the flowcharts and/or block diagrams.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more functions for implementing the specified logical function(s) executable instructions. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It is also noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented in dedicated hardware-based systems that perform the specified functions or actions , or can be implemented in a combination of dedicated hardware and computer instructions.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should only be construed in a general descriptive sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments, unless expressly stated otherwise. Features and/or elements are used in combination. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

A compiling method, comprising:

Acquire fault processing core information of the target chip; the target chip includes multiple processing cores, and the multiple processing cores include normal cores and/or faulty cores;

determining whether the target chip meets the regrouping condition based on the fault processing core information and the preset fault information;

In the case that the target chip meets the regrouping condition, based on the fault processing core information, perform grouping processing on the algorithm compilation result corresponding to the target chip to obtain the current grouping result, so that the normal core of the target chip can be processed into groups. An algorithm for implementing a preparatory bearer based on the current grouping result and the algorithm compilation result;

The algorithm compilation result includes an executable file corresponding to the algorithm prepared to be carried by the target chip.
The method according to claim 1, wherein the method further comprises:

Based on the preset fault information, perform the grouping process on the algorithm compilation result corresponding to the target chip to obtain a preset grouping result;

In the case that the target chip does not meet the regrouping condition, the preset grouping result is used as the current grouping result, so that the normal core of the target chip implements a preparatory bearer based on the current grouping result and the algorithm compilation result algorithm.
The method according to claim 1 or 2, wherein the fault processing core information includes an actual number of faulty cores; the preset fault information includes a preset number of faulty cores; information and preset fault information, and the steps of determining whether the target chip meets the regrouping conditions include:

In the case that the actual number of the faulty cores is inconsistent with the preset number of the faulty cores, determining that the target chip meets the regrouping condition;

Alternatively, in the case that the actual number of the faulty cores is greater than the preset number of the faulty cores, it is determined that the target chip meets the regrouping condition.
The method according to claim 1, wherein the fault processing core information includes the actual number of fault cores; and the algorithm compilation result corresponding to the target chip is grouped based on the fault processing core information, The steps to obtain the current grouping result include:

determining the target number of the normal cores based on the actual number of the faulty cores;

Based on the target number of the normal cores, grouping the algorithm compilation results corresponding to the target chips to obtain the current grouping result; the current grouping result includes the target number of compilation result groups, each of the The compilation result group is used to indicate the executable file to be mapped to a normal core execution.
The method according to claim 1, wherein the step of acquiring the fault handling core information of the target chip comprises:

The one-time programmable memory of the target chip is read to obtain fault processing core information of the target chip.
The method according to claim 4, wherein the method is applied to a target chip; the fault processing core information further includes absolute coordinates of the fault core; the target number based on the normal core is After the algorithm compilation result corresponding to the chip is grouped to obtain the current grouping result, it further includes:

According to the absolute coordinates of the faulty core, determine the absolute coordinates of the normal core;

Based on the absolute coordinates of the normal cores, the target number of the compilation result groups included in the current grouping result are mapped to the normal cores, wherein the absolute coordinates of the normal cores mapped by any two of the compilation result groups are The coordinates are different from each other.
The method according to claim 6, wherein the step of grouping and mapping a target number of the compilation results included in the current grouping result to the normal cores based on the absolute coordinates of the normal cores comprises: :

Based on the absolute coordinates of the normal cores and the computing capability parameter of the normal cores, a target number of the compilation result groups included in the current grouping result are grouped and mapped to the normal cores.
The method according to claim 1, wherein the method is applied to a target chip; the method further comprises:

The algorithm compilation result sent by the electronic device outside the target chip is received.
The method according to claim 1, wherein the method is applied to an electronic device outside the target chip, and the method further comprises:

Compile the algorithm to be carried by the target chip to obtain the algorithm compilation result.
The method according to claim 1, wherein the method is applied to an electronic device outside the target chip, and the algorithm compilation result corresponding to the target chip is grouped based on the fault processing core information, so as to After obtaining the current grouping result, the method further includes:

The current grouping result and the algorithm compilation result are sent to the target chip, so that the normal core of the target chip implements the algorithm for preparing the bearer based on the current grouping result and the algorithm compilation result.
The method according to claim 1, wherein the method is applied to an electronic device outside the target chip, and the method further comprises:

Based on the fault processing core information of each target chip in the multiple target chips and the corresponding algorithm compilation results, the same type of chips are determined; among them, the fault processing core information in the multiple target chips is consistent and the corresponding algorithm compilation results are consistent. called the same chip;

After performing grouping processing on the algorithm compilation result corresponding to the target chip based on the fault processing core information to obtain the current grouping result, the method further includes:

The current grouping result is used as the current grouping result corresponding to the same chip of the target chip.
The method according to claim 4, wherein the method is applied to an electronic device outside the target chip, and the fault processing core information includes absolute coordinates of the fault core; After the algorithm compilation result corresponding to the target chip is grouped to obtain the current grouping result, the method further includes:

Obtain the absolute coordinates of the normal core according to the absolute coordinates of the faulty core;

One-to-one correspondence between the compilation result grouping and the absolute coordinates of the normal core is obtained, and the corresponding relationship between the compilation result grouping and the absolute coordinates of the normal core is obtained;

Based on the corresponding relationship between the compilation result grouping and the absolute coordinates of the normal core, route compilation is performed on the route of the target chip, and the route compilation result is obtained;

Sending the current grouping result, the routing compilation result and the algorithm compilation result to the target chip.
A compiling device, characterized in that the compiling device comprises:

an acquisition module, configured to acquire fault processing core information of a target chip; the target chip includes multiple processing cores, and the multiple processing cores include normal cores and/or faulty cores;

a decision-making module, configured to determine whether the target chip meets the regrouping condition based on the fault processing core information and the preset fault information;

The processing module is configured to perform grouping processing on the algorithm compilation result corresponding to the target chip based on the fault processing core information under the condition that the target chip meets the regrouping condition, so as to obtain a current grouping result, so that the The normal core of the target chip implements the algorithm to be carried by the current grouping result and the algorithm compilation result; wherein the algorithm compilation result includes an executable file corresponding to the algorithm to be carried by the target chip.
An electronic device, comprising a memory, a processor and a computer program stored in the memory and running on the processor, characterized in that, when the processor executes the computer program, any one of claims 1 to 12 is implemented the compilation method described.
A computer-readable storage medium on which a computer program is stored, characterized in that, when the computer program is executed by a processor, the compiling method according to any one of claims 1 to 12 is implemented.
A computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is executed in a processor of an electronic device, all The processor in the electronic device executes the compilation method for implementing any one of claims 1-12.