WO2022183921A1

WO2022183921A1 - Neural model mapping method of brain-like computer operating system

Info

Publication number: WO2022183921A1
Application number: PCT/CN2022/077079
Authority: WO
Inventors: 吕攀; 张本浩; 杨国青; 李红; 邓水光; 潘纲; 吴朝晖
Original assignee: 浙江大学
Priority date: 2021-03-01
Filing date: 2022-02-21
Publication date: 2022-09-09
Also published as: CN112561042B; CN112561042A

Abstract

The present invention provides a neural model mapping method of a brain-like computer operating system, comprising the following steps: obtaining a directed graph G of a spiking neural network model, and taking a node of the directed graph G as a logic neuron cluster v; calculating a topological sequence O(G) of the directed graph, and calculating a mappable region R of the logic neuron cluster v according to hardware constraints of the brain-like computer; and according to the topological sequence O(G), for the logic neuron cluster v, selecting a physical neuron cluster in the mappable region R for mapping. The mapping method provided by the present invention is used, such that the spiking neural network can be reliably mapped into the brain-like computer, the deployment and operation of the spiking neural network on a larger scale can be met, and the network congestion is effectively reduced.

Description

A neural model mapping method for brain-like computer operating system

technical field

The invention belongs to the technical field of brain-like computers, and in particular relates to a method for mapping an impulse neural network model of a brain-like computer operating system.

Background technique

Neuron clusters are borrowed from the concept of neuron clusters in the human brain and represent a collection of neurons. A physical neuron is the smallest computing unit in a brain-like chip, and a physical neuron cluster is composed of several physical neurons. The logical neuron cluster refers to the logical neuron cluster represented in the brain-like computing model, and this part of the neuron cluster has not been assigned to the physical neuron cluster.

With the development of brain-like computing models and new brain-like architecture hardware, the research on brain-like computing software systems has also achieved preliminary results. The model deployment system in the brain-like computing software is responsible for deploying the compiled computing model to the brain-like computing chip. The model deployment system determines the usability and convenience of the brain-like computing hardware platform.

BrainScaleS OS developed by Heidelberg University in Germany uses PyNN to build a neural network model and provides two ways to map neurons to hardware neuron circuits. One is that the developer directly specifies the hardware neuron coordinates, that is, manual binding. The other is that BrainScaleS OS uses a greedy algorithm for mapping, that is, automatic binding. Mapping core process: (1) Neurons are sorted in descending order according to in-degree. Map neurons in descending order of in-degree. (2) Sort the HICANN chips according to the coordinates. The coordinates represent the actual physical communication distance, and the chip closest to the wafer center will be used first.

The SpiNNaker software system architecture of the University of Manchester in the United Kingdom provides the software operating environment for the system host and the PCB board-level system containing 48 SpiNNaker chips. The work of Jonathan Heathcote et al. abstracted the mapping problem in the SpiNNaker system into a circuit layout design to meet the hardware constraints of ARM processor resources and memory resources, with the goal of reducing the data traffic within and between boards, using a simulated annealing algorithm. Implement model mapping.

With the TrueNorth chip as the core, IBM has established a complete software and hardware ecosystem. For the model mapping part, TrueNorth proposed two mapping schemes successively. One solution is to map the logical neuron computing core to the physical neuron computing core with the goal of minimizing the distance of impulse communication. Four kinds of algorithms are used to calculate four kinds of results respectively, and the scheme with the shortest pulse communication distance is selected. The four algorithms are Multilevel Partitioning-driven algorithm, Analytical Constraint Generation algorithm, Hierarchical Quadratic Placement algorithm and Quadric-based Force-directed Analytical algorithm. Another scheme aims at minimizing the inter-chip pulse communication traffic, minimizing the intra-chip pulse communication distance and maximizing the input and output, and uses a heuristic algorithm to map the logical neuron computing core to the physical neuron computing core.

Intel provides the Loihi development toolchain, which provides a Python-based API, compiler, runtime, software simulator, and FPGA emulator. Loihi's compiler first splits the spiking neural network. The goal of splitting is to use as few neuron computing cores as possible, and map neurons to neuron computing cores in a greedy way. The compiler then generates the final binary, which in addition to being deployed on the Loihi chip, can also be used for simulation testing.

The Chinese invention patent with publication number CN105469143A proposes an on-chip network resource mapping method based on the dynamic characteristics of neural network. The communication volume of each core is calculated. If the ratio of the communication volume between any two cores does not meet the preset value, half of the neurons of the two cores are exchanged and remapped. This method can effectively balance the load and reduce the congestion of the on-chip network, but its final effect depends too much on the quality of the initialization rules and needs to run the SNN network multiple times for optimization.

The Darwin brain-like computer consists of 66 brain-like computing nodes, each brain-like computing node consists of 3 Darwinian brain-like computing chipsets, and each Darwinian brain-like computing chipset consists of 4 Darwinian brain-like chips through chip expansion technology. , the chip set realizes impulse communication by forwarding logic neuron clusters. The four brain-like computing chips in the chipset are addressed uniformly, and the address spaces between the chipsets are independent of each other.

As the size of the spiking neural network model increases, its demand for brain-like computing resources also expands, and the original single-chip-oriented model mapping method can no longer meet the demand. Research on the neural model mapping method based on the brain-like computer operating system can better support the development of brain-like computer hardware and meet the deployment and operation of larger-scale spiking neural networks, which is a necessary condition for the development of brain-like computer technology.

SUMMARY OF THE INVENTION

In order to solve the above-mentioned problems of the prior art, the present invention proposes a neural model mapping method for a brain-like computer operating system, which performs mapping according to the hardware constraints of the Darwinian brain-like computer. After the mapping, the original model performance can be maintained, and no SNN network needs to be performed. re-optimization.

The neural model mapping method of a brain-like computer operating system proposed by the present invention includes the following steps:

(1) Obtain the directed graph G of the spiking neural network model, whose nodes are logical neuron clusters v;

(2) Calculate the topological sequence of the directed graph O(G)=v1, v2, v3...vn, where n is the number of logical neuron clusters, and determine V ⁱⁿ (v) and V of each logical neuron cluster v ^out (v), where V ⁱⁿ (v) represents the set of logical neuron clusters pointing to v, and V ^out (v) represents the set of logical neuron clusters pointed to by v;

(3) According to the hardware constraints of the brain-like computer, calculate the mappable region R of the logical neuron cluster v, where R is the set of mappable physical neuron clusters U={u _0,0 ,u _0,1 ,... , u _{x, y} }, where the subscripts x and y represent the coordinates of the physical neuron cluster;

(4) According to the topological sequence O(G), for the logical neuron cluster v in it, select the physical neuron cluster in the mappable region R for mapping;

(5) According to the above mapping scheme, the mapping from the logical neuron cluster to the physical neuron cluster of the brain-like computer is obtained.

Further, in step (3), the mappable area is calculated according to the cross-chipset impulse communication constraints of the brain-like computer and the routing relationship between the chip sets.

Further, in the above step (4), for the logical neuron cluster transmitted in the chipset, select the physical neuron cluster to do the mapping according to the following method: According to the topology sequence O(G), for the logical neuron cluster v1, Calculate the communication power consumption of each physical neuron cluster in the corresponding mappable region R, and select the physical neuron cluster with the lowest power consumption for mapping; for the logical neuron cluster whose topology sequence is after v1, repeat the previous steps and select the mappable neuron cluster physical neuron clusters for mapping.

If a logical neuron cluster v in the topological sequence cannot find the corresponding physical neuron cluster for mapping, the mapping fails. According to the topological sequence O(G), remapping starts from v1. The specific method is as follows: For logical neuron In the mappable area R of the cluster v1, find the value with the smallest abscissa in all physical neuron clusters from the mappable area R, and select the physical neuron with the smallest ordinate from the set of physical neuron clusters whose abscissa is equal to the minimum value. Cluster mapping; for logical neuron clusters whose topological sequence is after v1, repeat the above steps to select a mappable physical neuron cluster until all logical neuron clusters find the corresponding physical neuron cluster for mapping.

Further, in step (4), for the logical neuron cluster transmitted in the chipset, select the physical neuron cluster for mapping according to the following method: for the mappable area R of the logical neuron cluster v1, from the mappable area R Find the value with the smallest abscissa in all physical neuron clusters, and select the physical neuron cluster with the smallest ordinate from the set of physical neuron clusters whose abscissa is equal to the minimum value for mapping; for the logical neuron cluster whose topological sequence is after v1 , repeat the above steps to select a mappable physical neuron cluster until all logical neuron clusters find the corresponding physical neuron cluster for mapping.

Further, for the logical neuron cluster transmitted between the chipsets, the upper left in the mappable region R is used as the initial point, and the layers are expanded outward in turn. In each layer, the mappable physical neuron cluster is selected in the direction from the upper right to the lower left. .

According to the above mapping scheme, the mapping from logical neuron clusters to Darwinian brain-like computer physical neuron clusters is obtained. Using this method, the spiking neural network can be reliably mapped to the Darwinian brain-like computer, which can reasonably deal with various models of different scales, effectively reduce network congestion, and can be extended to multiple computing nodes.

Description of drawings

In order to illustrate the technical solutions of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, which are of great significance to the art For those of ordinary skill, other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is a schematic flowchart of a neural model mapping process of a brain-like computer operating system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of region division of a Darwinian brain-like chipset according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a Darwinian brain-like computing node model mapping according to an embodiment of the present invention.

FIG. 4 is an effect diagram of a model mapping in a Darwinian brain-like chipset according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of the mapping sequence of the output area of the Darwinian brain-like chip according to an embodiment of the present invention.

FIG. 6 is a rendering effect diagram of the output model of the Darwinian brain-like chip according to the embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

As shown in FIG. 1 , a neural model mapping method for a brain-like computer operating system of the present embodiment includes the following steps:

First, obtain the directed graph G of the spiking neural network model, whose nodes are logical neuron clusters v.

Then, calculate the topological sequence of the directed graph O(G)=v1, v2, v3...vn, where n is the number of logical neuron clusters, and determine V ⁱⁿ (v) and V ^out of each logical neuron cluster v (v), where V ⁱⁿ (v) represents the set of logical neuron clusters pointing to v, and V ^out (v) represents the set of logical neuron clusters pointed to by v. And according to the hardware constraints of the brain-like computer, calculate the mappable region R of the logical neuron cluster v, where R is the set of mappable physical neuron clusters U={u _0,0 ,u _0,1 ,...,u _{x, y} }, where the subscripts x, y represent the coordinates of the physical neuron cluster.

Finally, according to the topological sequence O(G), for the logical neuron cluster v, select the physical neuron cluster in the mappable region R for mapping. In this embodiment, the pulse routing distance mapping is used for the transmission neuron clusters within the chipset, and the hierarchical spiral mapping method is used for the transmission neuron clusters between the chipsets. According to the above mapping scheme, the mapping from logical neuron clusters to brain-like computer physical neuron clusters is obtained.

Embodiments of the present invention relate to Darwinian brain-like computers and spiking neural network models. Specifically, the neural model splitting method used in the embodiments of the present invention needs to meet the hardware constraints of the Darwinian brain-like computer. At the same time, two models are used in the specific implementation of the embodiments of the present invention, namely, a handwritten digit recognition model (MNIST) and a voice recognition model (VOICE). in and running normally.

According to the different functions of physical neuron clusters, the chipset is divided into seven regions, as shown in Figure 2. In Figure 2, the upper left corner is the origin of coordinates, the dotted box is the area where the output neuron cluster is located and the area where the forwarding neuron cluster is located, and the solid line box is the area where the common neuron cluster is located. The functions of the output neuron cluster and the forwarding neuron cluster are mainly to send pulses to the inter-chip network outside the brain-like computing chip or other chipsets. The main function of the common neuron cluster node is to simulate neurons by time division multiplexing, process pulses according to the spiking neuron model, and dynamically update data such as membrane voltage. Among them, R ₁ corresponds to the area where the output neuron cluster is located; R ₂ R ₃ corresponds to the area where the forwarding neuron cluster is located; R ₄ R ₅ R ₆ R ₇ corresponds to the area where the common neuron cluster is located. The connection relationship between the chipsets is shown in Figure 3.

Darwinian brain-like nodes have various hardware constraints, among which the constraints that the spiking neural network model mapping needs to satisfy include the chipset impulse output constraint, the cross-chipset impulse communication constraint and the synaptic connection constraint.

Chipset pulse output constraint means that only the common neuron cluster in the region R ₄ ∪ R ₅ ∪ R ₆ can establish a connection relationship with the neuron cluster in the region R ₁ ∪ R ₂ ∪ R ₃ . Since the pulses sent to the region R1∪R2∪R3 will pass through the chipset boundary to the external virtual forwarding neuron node implemented by the FPGA, this connection constraint is called the chipset pulse output constraint.

The cross-chipset impulse communication constraint means that within the same brain-like computing node, for a logical neuron cluster v, its corresponding logical neuron cluster set V ⁱⁿ (v)∪v cannot be distributed on three different chipsets , where ^Vin (v) represents the set of logical neuron clusters pointing to the logical neuron cluster v.

The synaptic connection constraint means that, for the Darwin brain-like chip, the neuron data packet in the synaptic memory uses 8 bits to represent the relative coordinates of the destination logical neuron cluster node, the first 4 bits are used to represent the abscissa, and the last 4 bits are used to represent Y-axis. Therefore, it is assumed that the coordinates represented by the dynamic reference origin register of the logical neuron cluster v are (x _o , y _o ), and the logical neuron cluster area that the neurons in the logical neuron cluster v can connect to is Region(x _o , y _{o )} , x _o +15, y _o +15). That is, the logical neuron cluster set V ^out (v) pointed to by the logical neuron cluster v must be in this area.

In the spiking neural network model used in this embodiment, the structure of the MNIST model is 7×4×1, that is, it is divided into 3 layers, and the total number of logical neurons is 12. The structure of the VOICE model is 43x140x150x55x63x18x8x1x1, that is, it is divided into 9 layers, and the total number of logical neuron clusters is 479.

The input of the model mapping is the connection relationship between the logical neuron clusters, that is, the model directed graph G.

Then, calculate V ⁱⁿ (v) and V ^out (v) of each logical neuron cluster v, where V ⁱⁿ (v) represents the set of logical neuron clusters pointing to v, and V ^out (v) represents the logical neuron pointed to by v A collection of metaclusters.

According to the connection relationship between the logical neuron clusters, the topological sequence of the directed graph is calculated O(G)=v1, v2, v3...vn, where n is the number of logical neuron clusters. There may be multiple topological sequences of logical neuron clusters. Specifically, there may be multiple choices each time a node with an in-degree of 0 is selected. At this time, one of the nodes with the lowest level is selected. Lower-level nodes map to compute nodes.

According to the cross-chipset impulse communication constraints, the region R that can be mapped by the logical neuron cluster v is calculated. In this embodiment, when the logical neuron clusters in v and V ⁱⁿ (v) are mapped to the same chipset, the mappable area of the logical neuron cluster v is the area where the common neuron cluster is located, that is, R ₄ ∪ R ₅ ∪R ₆ ∪R ₇ .

When the logical neuron clusters in v and V ⁱⁿ (v) are mapped in different chipsets, the corresponding regions are selected according to the chipset pulse forwarding relation RM. Specifically, this embodiment provides six situations: 1) if v is mapped to chipset 1, and V ⁱⁿ (v) is mapped to chipset 2, then the mappable area of logical neuron cluster v is R ₅ ; 2) If v maps to Chipset 1 and ^Vin (v) maps to Chipset 3, then the mappable region for logical neuron cluster v is R4; ₃ ) If v maps to Chipset 2, ^Vin (v) maps to Chipset 1, the mappable area of logical neuron cluster v is R ₄ ; 4) If v is mapped to chipset 2, and V ⁱⁿ (v) is mapped to chipset 3, then the mappable area of logical neuron cluster v is R ₅ ; 5) If v maps to Chipset 3 and ^Vin (v) maps to Chipset 1, then the mappable area for logical neuron cluster v is R ₅ ; 6) If v maps to Chipset 3, ^Vin (v) maps to Chipset 1 (v) mapping to chipset 2, then the mappable area of logical neuron cluster v is R ₄ ;

In order to easily determine the mappable region, the RM matrix can be defined as follows,

Represents the pulse routing relationship between chipsets, let i and j denote the chipset number of the logical neuron cluster mapping in v and V ⁱⁿ (v), respectively, then the element corresponding to the i-th row and the j-th column in the RM is the mappable of v Region R(v). For example, if i=1, j=2, i.e. v maps to chipset 1 and ^Vin (v) maps to chipset 2, then the mappable area of logical neuron cluster v is RM(1,2)= R ₅ ; if i=2, j=2, that is, v maps to chipset 2 and V ⁱⁿ (v) maps to chipset 2, then the mappable area of logical neuron cluster v is RM(2,2)=R ₄ ∪R ₅ ∪R ₆ ∪R ₇ . When v∪V ⁱⁿ (v) does not satisfy the cross-chipset pulse communication constraint, the mappable area is empty, and the mappable area of v cannot be found at this time, and the subsequent mapping steps cannot be performed, and the mapping fails to exit.

According to the synaptic connection constraints, calculate the area that the logical neuron cluster v can map. The specific method is to traverse the logical neuron clusters in the logical neuron cluster set V ⁱⁿ (v). At this time, for the logical neuron cluster u in V ⁱⁿ (v), the connection relationship between u and v is that u points to v. Calculate the minimum area R(u) formed by V ^out (v) corresponding to u, combine with the mapped area R(v) generated by the cross-chip pulse communication constraints, and take the intersection of the two to obtain the mappable area R of v.

If the minimum area R(u) is less than 16x16, then expand it so that any point in the rectangle of the new minimum area R(u) after expansion can form a 16x16 matrix with the original minimum area R(u), and the specific area is expanded. Methods as below:

x _min = max(x _min -(16-(x _max -x _min )), 0)

x _max = min(x _max +(16-(x _max -x _min )), 47)

y _min =max(y _min -(16-(y _max -y _min )), 0)

y _max =min(x _max +(16-(y _max -y _min )), 48)

Region(x _min , y _min , x _max , y _max )

Among them, x _min , x _max , y _min , and y _max are intermediate variables for calculation, and represent the minimum abscissa, maximum abscissa, minimum ordinate, and maximum ordinate of the currently calculated minimum region R(u), respectively. Region(x _min , y _min , x _max , y _max ) represents the smallest region R(u) with (x _min , y _min ) as the lower left vertex and (x _max , y _max ) as the upper right vertex.

Algorithm pseudocode for computing mappable regions:

Input: Logical neuron cluster v, V ⁱⁿ (v) and V ^out (v)

V ⁱⁿ (v) represents the set of logical neuron clusters pointing to the logical neuron cluster v;

V ^out (v) represents the set of logical neuron clusters pointed to by the logical neuron cluster v;

v ⁿ represents the number of the brain-like computing node to which the logical neuron cluster v is mapped;

v ^c represents the chipset number to which the logical neuron cluster v is mapped;

v ^x represents the abscissa of the logical neuron cluster v;

v ^y represents the ordinate of the logical neuron cluster v;

output: mappable region R

Step 1: Calculate the area that can be mapped by the logical neuron cluster v according to the cross-chipset impulse communication constraints

RM represents the pulse routing relationship between chipsets, let i and j represent the chipset numbers of the logical neuron cluster mapping in v and V ⁱⁿ (v), respectively, then the element corresponding to the i-th row and the j-th column in RM is the available value of v. map area.

for u∈V ⁱⁿ (v)do

If u ⁿ is equal to v ⁿ , then R←R∩RM(u ⁿ , v ⁿ )

Step 2: Calculate the area that can be mapped by the logical neuron cluster v according to the synaptic connection constraints

for u∈V ⁱⁿ (v)do

for ^w∈Vout (u)do

x _min ←min(x _min , w ^x )

y _min ←min(y _min , w ^y )

x _max ←max(x _max , w ^x )

y _max ←max(y _max , w ^y )

Extend Region(x _min , y _min , x _max , y _max ) to the surrounding area based on a 16x16 rectangular area R←R∩Region(x _min , y _min , x _max , y _max )

end do

After calculating the mappable region R of the logical neuron cluster v, select the appropriate physical neuron cluster in the mappable region R for mapping. The logical neuron clusters are divided into logical neuron clusters transmitted within the chipset and logical neuron clusters across the chipset through model splitting.

For the logical neuron clusters transmitted in the chipset, there are two selection schemes: one is the selection scheme based on the pulse routing distance, and the other is the sequential selection scheme. The two schemes have their own advantages, and the selection scheme based on the pulse routing distance can make the pulse routing distance the shortest. The sequential selection scheme can make the area occupied by the logical neuron cluster more regular and suitable for larger models. For the MINIST model in this embodiment, the scale is small, and the schemes using pulse routing and sequential selection can be successfully mapped; for the VOICE model in this embodiment, the scale is large, and the mapping scheme using pulse routing may There is a situation where the mapping fails, so a sequential mapping scheme can be used.

For the logical neuron cluster transmitted in the chipset, firstly, the mapping method based on pulse routing distance is selected, and the physical neuron cluster with the least power consumption is selected from the mappable area according to the distance of pulse routing for mapping. In the selection scheme based on pulse routing distance, a basic basis for the selection of physical neuron clusters is the distance of pulse routing. Since the on-chip network of the brain-like computing chip adopts the XY routing algorithm, the distance of the pulse routing can be represented by the Manhattan distance. Denote the Manhattan distance between the physical neuron cluster mapped by v and the physical neuron cluster mapped by V ⁱⁿ (v) as L, and the power consumption is linearly related to L. After calculating the power consumption of all physical neuron clusters in the mappable area, select The physical neuron cluster with the least power consumption is mapped. Then select the logical neuron cluster after the topological sequence v to perform the above steps, until all logical neuron clusters can find the corresponding physical neuron cluster for mapping.

Calculating the Manhattan distance obtained from the logical neuron cluster node v to V ⁱⁿ (v) needs to consider 4 cases:

(1) The logical neuron cluster u and the logical neuron cluster v are mapped on the same chip.

(2) The logical neuron cluster u and the logical neuron cluster v are mapped on the same chip set, but on different chips. Although the chipset is uniformly addressed, there are still boundaries between the four chips inside. When the pulse crosses the chip boundary, it will go through parallel to serial, and there will be great power consumption. The constant C is used to represent this loss relationship.

(3) The logical neuron cluster node u and the logical neuron cluster node v are mapped in the same brain-like computing node, but in different chipsets.

(4) The logical neuron cluster node u and the logical neuron cluster node v are mapped to different brain-like computing nodes.

Since (3) and (4) are not in the same address space, they are not considered. Mainly consider the logical neuron cluster selection of the address space where (1) and (2) are located. Due to the relationship between the pulse routing distance and power consumption established by the Darwinian brain-like computing chip using the XY routing algorithm, the specific formula is as follows:

If two connected logical neuron clusters are on the same brain-like computing chip, the power consumption of pulse routing is a linear function of Manhattan distance. If two connected logical neuron clusters are distributed on different chips, there will be a large power consumption when the pulse passes the chip boundary. To this end, use e to represent the connection relationship of the logical neuron cluster, use n _on to indicate that the two physical logical neuron clusters are on the same brain-like computing chipset, and use n _off to indicate that the two physical neuron clusters are not in the same brain-like computing chip. In a chip set, that is, the pulse will cross the chip boundary. In the formula, x _i and y _i are the x-axis coordinates and y-axis coordinates of the logical neuron cluster vi, E represents the pulse communication constant between adjacent chips, cx _i and cy _i _represent the coordinates of the chip, and the coordinates of the chip can be Calculate the number of times the pulse has to cross the boundary. For the Darwinian brain-like computing chip, there is the following matrix relationship:

The matrix represents the adjacent brain-like computing chips, and the number of pulses crossing the chip boundary is 2, and for two diagonal chips, the number of pulses crossing the chip boundary is 4. For example, if two physical neuron clusters are in the 1st chip and the 2nd chip, respectively, the value 2 corresponds to the first row and the second column of the above matrix, that is, the number of times the pulse has to cross the boundary is 2; For another example, if two physical neuron clusters are in the second chip and the third chip, respectively, the value 4 corresponds to the second row and third column of the above matrix, that is, the number of times the pulse crosses the boundary is 4.

During the specific mapping, the corresponding physical neuron cluster is selected for mapping from the first logical neuron cluster v1 of the topological sequence. The mappable area R of the logical neuron cluster v1 has been calculated. According to the power consumption calculation formula, the communication power consumption of each physical neuron cluster in R and the physical neuron cluster mapped in V ⁱⁿ (v1) is calculated respectively. The physical neuron cluster with the lowest power consumption is selected as the map of v1. Since v1 is the first logical neuron cluster in the topological sequence, and there is no pre-neuron cluster, V ⁱⁿ (v1) is empty. At this time, v1 can select any physical neuron cluster in R for mapping. After calculating the physical neuron clusters that can be mapped by v1, calculate the physical neuron clusters that can be mapped by v2. The calculation method is the same as that of v1. At this time, if v1 points to v2, that is to say, V ⁱⁿ (v2) contains v1, then it is necessary to calculate the difference between all the unmapped physical neuron clusters in the mappable region R corresponding to v2 and the physical neuron clusters mapped by v1. Communication power consumption, and select the one with the lowest communication power consumption for mapping. After calculating the v2 mappable physical neuron clusters, calculate the v3 mappable physical neuron clusters, and so on, until all logical neuron clusters in the topology sequence can find the corresponding physical neuron clusters for mapping.

Pulse routing distance based selection schemes work well for small models, but may fail to map for larger models. When the VOICE model is mapped to the third layer, the mapping may fail. Since the second layer of logical neuron clusters always greedily selects the shortest pulse routing distance, a spike is formed, so that there is not enough 16x16 area for the third layer of logical neuron clusters, that is, the synaptic connection cannot be satisfied. constraint.

If the mapping method based on pulse routing distance is used for mapping, for a logical neuron cluster v in the topological sequence, the corresponding physical neuron cluster cannot be found for mapping, and the mapping fails, starting from v1 in the topological sequence O(G). Remap. In this embodiment, the sequential mapping method is selected. For the logical neuron cluster v in the topological sequence, firstly find all physical neuron clusters with the smallest abscissa x in the mappable region R, and select the physical neuron cluster with the smallest ordinate y as map. Then select the logical neuron cluster after the topological sequence v according to the method analogy, until all logical neuron clusters can find the corresponding physical neuron cluster for mapping. The sequential mapping method can make the area occupied by physical neuron clusters more regular and avoid mapping failures.

The specific implementation method of the sequence selection scheme proposed by the embodiment of the present invention is as follows: according to the mapping order O(G) of the logical neuron cluster determined by topological sorting, map sequentially, and for the mappable area R of the logical neuron cluster node v, firstly from the possible Find the value x' with the smallest abscissa in all physical neuron clusters in the mapping area R, and then select all the nodes in the mappable area R whose abscissa x is equal to the fixed x', from which the physical neuron with the smallest ordinate y is selected cluster. If no such node exists, add one to the value of x' and recalculate the physical neuron clusters that can be mapped.

The following is an example enumerated for the VOICE model. The corresponding physical neuron cluster cannot be found when the third-layer logical neuron cluster is mapped, so the mapping fails. At this time, the method of sequential mapping needs to be used. Starting from v1 in O(G), find the smallest value of the abscissa from the mappable region R corresponding to v1, and the R corresponding to v1 is Region(0,0,16,16) , which is the upper left area of the chipset. The smallest abscissa value is 0, so find the physical neuron cluster with the smallest ordinate from the set of physical neuron clusters whose abscissa is 0 in R, that is, the physical neuron cluster corresponding to the coordinate (0, 0) for mapping . After the physical neuron cluster mapped by v1 is determined, the mapping of v2 is performed. Also determine the minimum abscissa value of 0. Since the physical neuron cluster corresponding to the coordinate (0, 0) has been mapped by v1, the physical neuron cluster corresponding to the coordinate (0, 1) is selected for mapping. . After determining the physical neuron cluster mapped by v2, map v3, and so on. For the VOICE model, the sequential selection scheme mapping results are shown in Figure 4. This scheme can make each layer map in a rectangular area as much as possible. The model can be successfully mapped on the chipset.

For the logical neuron cluster transmitted between chipsets, corresponding to the selection of the physical neuron cluster in the output area, a hierarchical spiral method is used to map from the upper right to the lower left. This method can effectively apply to the situation where there are too many output nodes. Use the physical neuron cluster selection sequence shown in Figure 5 for mapping, and the specific selection methods are as follows:

1) First, let the level L=1 initially;

2) Select the physical neuron cluster with the smallest ordinate y from all the physical neuron clusters with abscissa x=L in the mappable area;

3) If the selected physical neuron cluster ordinate y>L, enter 4), otherwise enter 6);

4) Select the physical neuron cluster with the largest abscissa x from all the physical neuron clusters with the ordinate y=L in the mappable area;

5) If the selected physical neuron cluster abscissa x>L, then let L=L+1, enter 2); otherwise, enter 6);

6) Select the physical neuron cluster for mapping;

According to this method, the output logic neuron cluster is in one corner, making the area coincident with the chip larger (16x16 rectangular area). The final mapping result is shown in Figure 6, which can map the logical neuron cluster of the second layer into a 16x16 rectangular area. The hierarchical spiral mapping method is used to avoid the situation that the mapping fails due to too many adjacent layer nodes in the directed graph of the spiking neural network model.

Claims

A neural model mapping method for a brain-like computer operating system, comprising the following steps:

(1) Obtain the directed graph G of the spiking neural network model, whose nodes are logical neuron clusters v;

(2) Calculate the topological sequence of the directed graph O(G)=v1, v2, v3...vn, where n is the number of logical neuron clusters, and determine V in (v) and V of each logical neuron cluster v out (v), where V in (v) represents the set of logical neuron clusters pointing to v, and V out (v) represents the set of logical neuron clusters pointed to by v;

(3) According to the hardware constraints of the brain-like computer, calculate the mappable region R of the logical neuron cluster v, where R is the set of mappable physical neuron clusters U={u 0,0 ,u 0,1 ,... , u x, y }, where the subscripts x and y represent the coordinates of the physical neuron cluster;

(4) According to the topological sequence O(G), for the logical neuron cluster v in it, select the physical neuron cluster in the mappable region R for mapping;

(5) According to the above mapping scheme, the mapping from the logical neuron cluster to the physical neuron cluster of the brain-like computer is obtained.
The mapping method according to claim 1, wherein, in step (4), for the logical neuron cluster transmitted in the chipset, select the physical neuron cluster to do the mapping according to the following method:

(1) According to the topological sequence O(G), for the logical neuron cluster v1, calculate the communication power consumption of each physical neuron cluster in the corresponding mappable region R, and select the physical neuron cluster with the lowest power consumption for mapping ;

(2) For the logical neuron cluster whose topological sequence is after v1, repeat the above steps, and select a mappable physical neuron cluster for mapping.
The mapping method according to claim 2, wherein, if a logical neuron cluster v in the topological sequence cannot find a corresponding physical neuron cluster for mapping, the mapping fails, and according to the topological sequence O(G) , remapping from v1, the specific method is as follows:

(1) For the mappable region R of the logical neuron cluster v1, find the value with the smallest abscissa in all physical neuron clusters from the mappable region R, and select the vertical axis from the set of physical neuron clusters whose abscissa is equal to the minimum value. The physical neuron cluster with the smallest coordinates is mapped;

(2) For the logical neuron cluster after the topological sequence v1, repeat the above steps to select a mappable physical neuron cluster, until all logical neuron clusters find the corresponding physical neuron cluster for mapping.
The mapping method according to claim 1, wherein, in step (4), for the logical neuron cluster transmitted in the chipset, select the physical neuron cluster to do the mapping according to the following method:

(1) For the mappable region R of the logical neuron cluster v1, find the value with the smallest abscissa in all physical neuron clusters from the mappable region R, and select the vertical axis from the set of physical neuron clusters whose abscissa is equal to the minimum value. The physical neuron cluster with the smallest coordinates is mapped;

(2) For the logical neuron cluster after the topological sequence v1, repeat the above steps to select a mappable physical neuron cluster, until all logical neuron clusters find the corresponding physical neuron cluster for mapping.
The mapping method according to claim 1, wherein, for the logical neuron cluster transmitted between the chipsets, the upper left in the mappable region R is used as the initial point, and the levels are expanded outward in turn, and each layer is arranged according to the order from the upper right. Go to the bottom left to select the mappable physical neuron cluster for the direction.
The mapping method according to claim 1, characterized in that, in step (3), the mappable area is calculated according to the cross-chip set impulse communication constraints of the brain-like computer and the routing relationship between the chip sets.
The mapping method according to claim 6, wherein, according to the synaptic connection constraints of the brain-like computer, traverse the logical neuron clusters in the logical neuron cluster set V in (v); for the logical neuron clusters in V in (v) The connection relationship between logical neuron clusters u, u and v is that u points to v, calculate the minimum area R(u) formed by V out (u) corresponding to u, and combine the mapped area R(v) generated by the cross-chipset pulse communication constraints ), R(u)∩R(v), get the mappable region R of v.
The mapping method according to claim 7, wherein, for the minimum area R(u) smaller than 16×16, it is expanded to obtain a new minimum area R(u), and the expanded new minimum area R(u) Any point can form a 16x16 matrix with the original minimum region R(u).