WO2022082732A1

WO2022082732A1 - A program and read bias and access scheme to improve data throughput for 2 stack 3d pcm memory

Info

Publication number: WO2022082732A1
Application number: PCT/CN2020/123258
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd.
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2022-04-28
Also published as: CN112470225B; CN112470225A

Abstract

A method for accessing memory cells of a three-dimensional memory comprising a plurality of bottom cell blocks, a plurality of top cell blocks, a plurality of bottom cell bit lines coupled to the bottom cell blocks, a plurality of top cell bit lines coupled to the top cell blocks, and a plurality of word lines coupled to each of a bottom cell block positioned below the word lines and a top cell block positioned above the word lines. The method may include accessing memory cells of the bottom cell block and the top cell block at the time by biasing one word line, one bit line of the bottom cell bit lines, and one bit line of the top cell bit lines.

Description

A PROGRAM AND READ BIAS AND ACCESS SCHEME TO IMPROVE DATA THROUGHPUT FOR 2 STACK 3D PCM MEMORY

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to increasing the throughput of memory cell accessing schemes in three-dimensional crosspoint memories.

BACKGROUND

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells, and a biasing scheme for accessing memory cells of the three-dimensional (3D) memory architecture can address throughput limitations of the three-dimensional (3D) memory architecture.

SUMMARY

The presently disclosed three-dimensional memory and biasing schemes solve the problems of current state of the art and provide many more benefits. In accordance with an aspect, disclosed and shown is a distributed array and CMOS (complementary metal-oxide semiconductor) architecture for 3D X-Point memory. Word line (WL) and Bit line (BL) decoders for each memory tile are broken into portions and arranged in a distributed pattern. The middle of WL and BL decoder regions are connected in the middle of word lines and bit lines. TCBL (top cell bit line) blocks are offset one half block to make connections to CMOS TCBL decodes, between BCBL (bottom cell bit line) blocks. BCBL, TCBL blocks and BCWL (bottom cell word line) blocks are offset to maximize area usage. Each of the BCBL and TCBL blocks may be accessed one cell at a time by biasing a selected WL and a selected BL to read or program the cell positioned at an intersection between the selected WL and BL. As a result, the array efficiency is greatly improved compared to current state of the art systems.

In another aspect, provided is a method for accessing memory cells of a three-dimensional memory. The method may include accessing memory cells of a first bottom cell block of a bottom cell array and a first top cell block of a top cell array above the bottom cell array by biasing one word line of a first portion of word lines, one bit line of a first portion of bottom cell bit lines, and one bit line of a first portion of top cell bit lines, and accessing memory cells of a second bottom cell block of the bottom cell array and offset from the first bottom cell block and a second top cell block of the top cell array and offset from the first top cell block by biasing one word line of a second potion of word lines, one bit line of a second portion of bottom cell bit lines, and one bit line of a second portion of top cell bit lines.

In some examples, memory cells of the first bottom cell block and the first top cell block may be accessed simultaneously, and memory cells of the second bottom cell block and the second top cell block may be accessed simultaneously.

In some examples, accessing at least one cell of a cell block may include raising a voltage of a word line coupled to the at least one cell above a first threshold value, and lowering a voltage of a bit line coupled to the at least one cell below a second threshold value.

In some examples, the first threshold value may be between about 5 to 20 V, and the second threshold value may be between about -20 to -5 V.

In some examples, each unbiased word line may have a voltage of about 2 V, and wherein each unbiased bit line may have a voltage of about 2 V.

In some examples, accessing at least one cell of the memory block may include maintaining a voltage of each unbiased word line coupled to the memory block at a first unbiased voltage value, and maintaining a voltage of each unbiased bit line coupled to the memory block at a second unbiased voltage value.

In some examples, the first unbiased voltage value may be about 2 V, and wherein the second unbiased voltage value may be about 2 V.

In some examples, each unbiased word line may have a voltage of about 0 V, and wherein each unbiased bit line may have a voltage of about 0 V.

In some examples, accessing memory cells may iclude at least one of reading data from the memory cells or programming data to the memory cells.

In some examples, the three-dimensional memory may include a plurality of pages, each page may include a plurality of memory blocks, and accessing memory cells of a given page of the three-dimensional memory may include accessing two memory cells of each memory block at one time.

In some examples, each page may include 128 memory blocks, and accessing memory cells of a given page may be performed at a rate of 256 memory cells at a time.

In yet another aspect, the method may include accessing memory cells of a bottom cell block of a bottom cell array one cell at a time by biasing one word line of a plurality of word lines and one bit line of a plurality of bottom cell bit lines, and accessing memory cells of a top cell block of a top cell array offset from the bottom cell block and positioned above the bottom cell array in a depth direction one cell at a time by biasing one word line of the plurality of word lines and one bit line of a plurality of top cell bit lines. A first memory cell of the bottom cell block and a second memory cell of the top cell block positioned above the first memory cell may be accessed at the same time by biasing a word line of the plurality of word lines that is connected to both the first memory cell and the second memory cell.

In some examples, biasing one word line of the plurality of word lines may include raising a voltage of the one word line above a first threshold value.

In some examples, biasing one word line of the plurality of word lines may include maintaining a voltage of the plurality of word lines aside from the one word line at an unbiased word line voltage value.

In some examples, biasing a first bit line of the plurality of bottom cell bit lines and a second bit line of the plurality of top cell bit lines may include lowering a voltage of the first bit line and the second bot line below a second threshold value.

In some examples, biasing a first bit line of the plurality of bottom cell bit lines and a second bit line of the plurality of top cell bit lines may include maintaining a voltage of the plurality of bottom cell bit lines and the plurality of top cell bit lines aside from the first bit line and the second bit line at an unbiased bit line voltage value.

In some examples, accessing memory cells may include at least one of reading data from the memory cells or programming data to the memory cells.

In some examples, the bottom cell block may be positioned below the plurality of word lines in the depth direction and the top cell block may be positioned above the plurality of word lines in the depth direction.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

Fig. 1 is an isometric view of a section of three-dimensional crosspoint memory.

Fig. 2 is a plan view of a section of a prior three-dimensional crosspoint memory.

Figs. 3A and 3B are plan views of a section of prior three-dimensional crosspoint memory.

Fig. 3C is a plan view of another section of prior three-dimensional crosspoint memory.

Fig. 3D is a block diagram representation of a portion of the section of prior three-dimensional crosspoint memory of Fig. 3C.

Fig. 4 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment.

Fig. 5A is another plan view of a section of three-dimensional crosspoint memory according to an embodiment.

Fig. 5B is a side view of the section of three-dimensional crosspoint memory in accordance with the embodiment of Fig. 5A along axis Y-Y.

Fig. 5C is a side view of the section of three-dimensional crosspoint memory in accordance with the embodiment of Fig. 5A along axis X-X.

Fig. 6A is the plan view of the section of three-dimensional crosspoint memory of Fig. 5A showing a biasing scheme according to an embodiment.

Fig. 6B is a side view of the section of three-dimensional crosspoint memory in accordance with the embodiment of Fig. 6A along axis Y-Y.

Fig. 6C is a side view of the section of three-dimensional crosspoint memory in accordance with the embodiment of Fig. 6A along axis X-X.

DETAILED DESCRIPTION

The present technology is applied in the field of three-dimensional memory. A generalized example of a three-dimensional (3D) memory is shown in Fig. 1. In particular, Fig. 1 is an isometric view of a section of three-dimensional crosspoint memory. The memory includes a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer of memory cells 5 and second layer of memory cells is a number of word lines 15 extending in a horizontal or X direction. Above the first layer of memory cells 5 is a number of first bit lines 20 extending along a vertical or Y direction, and below the second layer of memory cells is a number of second bit lines 25 extending along the Y direction.

Further as shown in Fig. 1, the sequential structure of bit line, memory cell, word line, memory cell may be repeated along the Z direction to create a stacked configuration. In the example of FIG. 1, a first layer of the stack may include the first layer of memory cells 5, bit lines 20, and word lines 15, while a second layer of the stack may include the second layer of memory cells 10, the bit lines 25, and word lines 15. Thus, while the first layer of memory cells 5 and the second layer of memory cells 10 each have its respective set of

bit lines

20 and 25, the first layer of memory cells 5 and the second layer of memory cells 10 may share a same set of word lines 15. Although the example of Fig. 1 shows a 4-layer stack configuration, in other examples, the stacked configuration may include any number of memory cell layers and other elements. In any event, an individual memory cell in the structure may be accessed by selectively activating the word line and bit line corresponding to the cell.

In order to selectively activate the word lines and bit lines, the memory includes word line decoders and bit line decoders (not shown) . The word line decoders are coupled to the word lines by word line contacts (not shown) and are used to decode word line addresses such that a particular word line is activated when it is addressed. Similarly, the bit line decoders are coupled to the bit lines by bit line contacts (not shown) and are used to decode bit line addresses such that a particular bit line is activated when it is addressed. Thus, the stack configuration of memory may further include bit line contacts and decoders, and word line contacts and decoders for selectively activating the bit lines and word lines in the stack. For instance, the stack configuration may be arranged as arrays of elements in each stacked layer, where each array includes a set of memory cells, and corresponding sets of bit lines, word lines, bit line and word line contacts, and bit line and word line decoders.

Fig. 2 is a plan view of a section of three-dimensional crosspoint memory of a prior configuration. The figure depicts the section as viewed along the Z (depth) direction. In this example, the stacked configuration is a 2-layer stack. The stacked configuration includes a plurality of arrays of memory cells, including two

top cell arrays

60 and 61 and two

bottom cell array

65 and 66. Although individual memory cells are not shown in FIG. 2, they are illustrated by FIG. 1, for example in the top array the memory cells may be arranged as the first layer of memory cells 5 shown in Fig. 1 and in the bottom array the memory cells may be arranged as the second layer of memory cells 10 shown in Fig. 1.

The section includes word lines and bit lines, word line and bit line contacts, and word line and bit line decoders corresponding to the top cells and bottom cells. As shown, a number of word lines, e.g. word lines 30, extend in the X (horizontal) direction and corresponding to both the top cells and bottom cells. The section further includes a number of top cell bit lines, e.g., bit lines 35, extending along the Y (vertical) direction and corresponding to the top cell array of memory cells 60, and a number of bottom cell bit lines, e.g., bit lines 40, extending along the vertical direction and corresponding to the bottom cell array of memory cells 65. The word lines, top cell bit lines, and bottom cell bit lines are typically formed of a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate. Moreover, the memory may employ complementary metal-oxide semiconductor (CMOS) technology.

The word lines in Fig. 2 are horizontally aligned for a given cell array. For instance as shown, word lines for

cell arrays

60, 61, 65, and 66 are all horizontally aligned with one another and not offset from one another along the X direction. Each of these word lines are shown extending across an entire width of the respective cell arrays. Top cell bit lines for a given top cell array or bottom cell bit lines for a given bottom cell array are vertically aligned with one another and not offset from one another in the vertical or Y direction. For instance, top cell bit lines 35 are vertically aligned along the Y direction, and bottom cell bit lines 40 are vertically aligned along the Y direction. The top cell bit lines of a top cell array and bottom cell bit lines of an overlapping bottom cell array, such as top cell bit lines 35 and bottom cell bit lines 40, are also vertically aligned with one another and not offset from one another in the vertical or Y direction, although they are shown in Fig. 2 as slightly offset in order to clearly show both layers. Each of these bit lines are shown extending across an entire length of the respective cell arrays.

The memory section of Fig. 2 also includes a word line contact area 45, a top cell bit line contact area 50, and a bottom cell bit line contact area 55. The word line contact area 45 is elongated along the vertical direction, while the top cell bit line contact area 50 and bottom cell contact area 55 are elongated along the horizontal direction. The word line contact area 45 includes a plurality of word line contacts, e.g., contact 45a, shown as dots enclosed by the word line contact area 45. The top cell bit line contact area 50 includes a plurality of word line contacts, e.g., contact 50a, shown as dots enclosed by top cell bit line contact area 50. The bottom cell bit line contact area 55 includes a plurality of bottom cell bit line contacts, e.g., contact 55a, shown as dots enclosed by bottom cell bit line contact area 55.

The word line contacts and bit line contacts are connected to the middle of the respective word lines and bit lines. Thus as shown, word line contact area 45 is positioned in the horizontal middle of word lines 40, bottom cell bit line contact area 55 is positioned in the vertical middle of the bottom cell bit lines 40, and top cell bit line contact area 50 is positioned in the vertical middle of the top cell bit lines 35. Since the word lines for a given cell array extend lengthwise horizontally in the X direction and are aligned with one another such that no word line is offset from another, the word line contacts may substantially form a line in the vertical or Y direction such that they are aligned with one another and not offset from one another horizontally. Likewise, since the bit lines for a given cell array extend vertically in the Y direction and are substantially aligned with one another such that no bit line is substantially offset from one another, the bit line contacts substantially form a line in the horizontal or X direction such that they are aligned with one another and not offset from one another vertically.

The word line contact area 45 also includes a plurality of word line decoders (not shown) . The word line decoders generally conform to the word line contact area and generally extend along the vertical direction. The word line decoders couple to the word lines at the word line contacts. The top cell bit line contact area 50 also includes a plurality of top cell bit line decoders (not shown) . The top cell bit line decoders generally conform to the top cell bit line contact area 50 and generally extend along the horizontal direction. The top cell bit line decoders couple to the top cell bit lines at the top cell bit line contacts. The bottom cell bit line contact area 55 also includes a plurality of bottom cell bit line decoders (not shown) . The bottom cell bit line decoders generally conform to the bottom cell bit line contact area 55 and generally extend along the horizontal direction. The bottom cell bit line decoders couple to the bottom cell bit lines at the bottom cell bit line contacts.

The configuration as exemplified in Fig 2 is inefficient in its use of memory area (or “memory real estate” ) . This drawback stems primarily from the arrangement of the word line decoders. As can be seen from Fig. 2, the word line contact area 45, and accordingly the word line contacts and word line decoders, are arranged in the horizontal middle of the memory structure. For instance as shown, the word line contacts 45 and word line decoders are arranged along the horizontal middle of the top and bottom arrays of memory cells 60 and 65 (but at a different depth in the Z direction) . This is also true for other arrays in the memory, such as top cell array 61 and bottom cell array 66, where a word line contact area also occupies the middle of these arrays. The decoders are arranged as such because, as described above, the word lines are horizontally aligned, and the bit lines are vertically aligned.

Fig. 3A is a plan view of a section of a prior three-dimensional crosspoint memory. The figure depicts the section as viewed along the depth or Z direction. This example is a 2-layer stack configuration. The figure shows a plurality of bottom cell arrays including bottom cell array 60 extending from a first edge or top edge 75 to a second edge or bottom edge 80, and a plurality of top cell arrays, including a top cell array 65 extending from a first edge or top edge 76 to a second edge or bottom edge 81. Fig. 3B is the same plan view as Fig. 3A with the exception that the markings denoting the bottom cell array 60 and the top cell array 65 have been removed. For purposes of clarity of presentation Figs. 3A and 3B will be discussed only with respect to the portions pertaining to the bottom cell array 60 and the top cell array 65, with the understanding that such discussion can be readily applied to the other parts of the figures. Also, it should be noted the figures show only the word line decoders, top cell bit line decoders, and bottom cell bit line decoders, and does not show the other parts of the memory.

Referring to Figs. 3A and 3B, it can be seen that the memory section includes a set of word line decoders 70 that is arranged in a contiguous vertical stripe of area from the top edge 75 of the bottom cell array 60 to the bottom edge 80 of the bottom cell array 60. The word line decoders 70 generally extend along the vertical or Y direction, conforming to the word line contact area 45 shown in Fig. 2. The memory section also includes a set of top cell bit line decoders 85 of the top cell array 65 that is split into two

portions

85a and 85b along the horizontal or X direction and which are vertically aligned, and a set of bottom cell bit line decoders 90 of the bottom cell array 60 that are split into two

portions

90a and 90b along the horizontal or X direction which are vertically aligned. The top cell bit line decoders 85 and bottom cell bit line decoders 90 generally extend along the horizontal or X direction, conforming to the top cell bit line contact area 50 and bottom cell bit line contact area 55, respectively, shown in Fig. 2

As shown in Figs. 3A and 3B, the bit line and word line decoders are arranged symmetrically in the memory structure. This is because, as described in relation to Fig. 2, the word lines are horizontally aligned, and the bit lines are vertically aligned. This prior configuration shown in Figs. 3A and 3B thus dedicates a vertical stripe of the memory area to word line contacts and word line decoders, which does not include any bit lines or memory cells for data storage, thereby limiting the efficiency of the memory.

Fig. 3C is a plan view of another section of a prior three-dimensional crosspoint memory. The figure depicts the section as viewed along the depth or Z direction. The figure shows a plurality of pages of the memory. In particular, the plan view in Fig. 3C shows sixteen pages of memory, including a first page 310 at a first end of the shown portion of the memory, and a sixteenth page 320 at an opposing second end of the shown portion of the memory. The pages arranged in strips running parallel to one another.

Fig. 3D shows a block diagram of components included in the first page 310 of the memory of Fig. 3C. Included in page 310 are control circuits 312 for reading and programming memory cells of the page 310, and a plurality of blocks of memory 314. Also shown in the representation of Fig. 3D are bits 316 read from or programmed to the blocks of memory 314. In the example of Fig. 3D, the page 310 is shown as including enough control circuits 312 to access 128 blocks at the same time. At each block 314, only a single memory cell can be accessed at a time. This limits the access size of a single page to 128 bits (or 16 bytes) , whereby 128 bits can be read from or programmed to the page at one time.

Although an access size of 128 bits is suitable for many applications, demand for higher access sizes is growing. For example, an access size of 256 bits (or 32 bytes) is typically preferable in server applications. Therefore, it would be beneficial if more data could be read from or programmed to the memory at one time.

Fig. 4 is a plan view of an example section of three-dimensional crosspoint memory according to an embodiment. The figure depicts the section as viewed along the depth or Z direction. The section in Fig. 4 shows a plurality of columns of cell blocks. In the example of Fig. 4, a portion of first column of cell blocks 410 is shown to include a pair of bottom cell blocks 412, 414 and a pair of

top cell blocks

416, 418. The bottom cell blocks are offset in the vertical or Y direction from the top cell blocks, such that the first bottom cell block 412 is positioned partially underneath the first top cell block 416, and such that the second bottom cell block 414 is positioned partially underneath each of the first top cell block 416 and the second top cell block 418. The overlapping between top cell blocks and bottom cell blocks may be repeated along the vertical or Y direction in order to include additional cell blocks in the column of cell blocks. Additionally, the pattern of the column of cell blocks may be repeated in one or more other columns positioned adjacent the first column of cell blocks. In the example of Fig. 4, a portion of a second column of cell blocks 420 is shown to include a pair of bottom cell blocks 422, 424 and a pair of

top cell blocks

426, 428. As with the first column of cell blocks 410, the top and bottom cell blocks of the second column 420 are offset from one another.

Additionally, a word line decoder and a bit line decoder for each bottom cell block and top cell block of the example configuration is shown as being broken into separate and offset portions. Taking for example top cell block 416 of the first column 410 of Fig. 4, the top cell block 416 includes a word line decoder having a first portion 432 and a second portion 434, and the top cell block 426 includes a word line decoder having a third portion 436 and a fourth portion 438. The first and

second portions

432, 434 may be in horizontal alignment with one another, and the third and

fourth portions

436, 438 may be in horizontal alignment with one another, but offset horizontally apart from the first and

second portions

432, 434 in the X direction.

Offsetting the portions of the word line decoder may allow for each portion to be connected to the middle of a respective plurality of word lines. In the example of Fig. 4, the first portion 432 of the word line decoder is positioned at midpoints of a first plurality of word lines 442, the second portion 434 of the word line decoder is positioned at midpoints of a second plurality of word lines 444, the third portion 436 of the word line decoder is positioned at midpoints of a third plurality of word lines 446, and the fourth portion 438 of the word line decoder is positioned at midpoints of a fourth plurality of word lines 448. The words lines may run in parallel to one another along the horizontal or X direction, and each plurality of word line may be offset from its immediately adjacent plurality of word lines such that the midpoints of each plurality of word lines are aligned with the midpoints of their corresponding word line decoders (which, as explained above, are similarly spaced apart in the horizontal or X direction) .

In the example of Fig. 4, cell blocks may be combined to form a cell array. For instance,

bottom cell blocks

412 and 422 may be considered a bottom cell array 452, whereby the individual blocks of the bottom cell array 452 are offset from one another in the vertical or Y direction. Similarly,

top cell blocks

418 and 428 may be considered a top cell array 458, whereby the individual blocks of the top cell array 458 are offset from one another in the vertical or Y direction.

Fig. 5A is a plan view of section of three-dimensional crosspoint memory according to an embodiment. The figure depicts the section as viewed along the depth or Z direction. The embodiment of Fig. 5A includes features comparable to the feature described in connection with the embodiment of Fig 4. For instance, memory cells, word lines, bit lines, word line and bit line contacts, and word line and bit line decoders in each array in Fig. 5A may be similarly arranged as described in relation to Fig. 4. Fig. 5A is provided to show the word line and bit line contacts with the word lines and bit lines. Thus, a bottom cell array 500 is highlighted, which may be configured similarly as the arrays of Fig. 4, such as the bottom cell array 452 and the top cell array 456 discussed in detail in connection with Fig. 4. As shown, the bottom cell array 500 is divided into two

subsections

500a and 500b. A first portion of bottom cell bit lines 510a extend along the length of subsection 500a, and a second portion of bottom cell bit lines 510b extend along the length of subsection 500b. A first set of bottom cell bit line contacts 520a are provided in the vertical middle of the first portion of bottom cell bit lines 510a, and a second set of bottom cell bit line contacts 520b are provided in the vertical middle of the second portion of bottom cell bit lines 510b.

The two

subsections

500a and 500b are offset from each other, for example along a vertical or Y direction as shown by a predetermined length. Likewise, the first portion of bottom cell bit lines 510a and the second portion of bottom cell bit lines 510b also have a vertical offset between them. Since bit line contacts are positioned in the middle of the bit lines, the first set of bottom cell bit line contacts 520a and the second set of bottom cell bit line contacts 520b also have an offset between them in the vertical or Y direction.

Above the first set of bottom cell bit line contacts 520a, a first portion of word lines 530a extend from a first horizontally adjacent cell through the subsection 500a into the second subsection 500b. A first set of word line contacts 540a are provided along the middle of the first portion of word lines 530a to couple the first portion of word lines 530a to a first set of word line decoders (not shown) . Below the first set of bottom cell bit line contacts 530a, a second portion of word lines 540b also extend from the first horizontally adjacent cell through the subsection 510a into the second subsection 510b. A second set of word line contacts 540b are provided along the middle of the second portion of word lines 530b to couple the second portion of word lines 530b to a second set of word line decoders (not shown) .

Above the second set of bottom cell bit line contacts 520b, a third portion of word lines 530c extend from the subsection 500a through the second subsection 500b into an area of a second horizontally adjacent cell. A third set of word line contacts 540c are provided along the middle of the third portion of word lines 530c to couple the third portion of word lines 530c to a third set of word line decoders (not shown) . Below the second set of bottom cell bit line contacts 520b, a fourth portion of word lines 530d extend from the subsection 500a through the second subsection 500b into an area of the second horizontally adjacent cell. A fourth set of word line contacts 530d are provided along the middle of the fourth portion of word lines 530d to couple the fourth portion of word lines 530d to a fourth set of word line decoders (not shown) . The word line decoders, though not shown, may be positioned generally in the same areas as the word line contacts. Likewise, the bit decoders, though not shown, may be positioned generally in the same areas as the word line contacts.

By introducing offsets between the word lines and the bit lines, offsets are also introduced to the corresponding word line contacts, bit line contacts, word line decoders, and bit line decoders. Because of the distributed positioning of these elements, bit lines can occupy areas overlapping word line contacts. Although Fig. 5A appears to show that bit lines do not overlap areas for word line contacts because large spacing is shown for ease of illustration,

Fig. 5B is a cross-sectional view of a section of three-dimensional crosspoint memory of Fig. 5A along a vertical or Y direction at the Y-Y axis shown in Fig. 5A. The bottom cell array 500 includes a first layer of memory cells 560. Below the first layer of memory cells 560, bit lines and bit line contacts are provided. For instance, two portions of bottom cell bit lines may be provided (only 510a visible from this cross-section) , and two sets of bottom cell bit line contacts (only 520a visible from this cross-section) may be provided. Above the first layer of memory cells 560, word lines and word line contacts are provided. For instance, four portions of word lines may be provided, of which only two

portions

530a and 530b are visible from this view, and four sets of word line contacts may be provided, of which only two

sets

540a and 540b are visible from this view. Thus, bottom cell bit lines and bottom cell memory cells are provided in areas overlapping areas of word line contacts.

Fig. 5B further shows, a top cell array 550 partially overlapping the bottom cell array 510. The top cell array 550 includes a second layer of memory cells 570. Above the second layer of memory cells 570, two portions of top cell bit lines (only 560a visible) may be provided, and two sets of top cell bit line contacts (only 570a visible) may be provided. Below the second layer of memory cells 570, word line and word line contacts are provided, some of which may be shared with the bottom cell array 500. For instance, the top cell array 550 may include four portions of word lines, of which only two

portions

580a and 530a are visible from this view, and four sets of word line contacts, of which only 540a is visible from this view. Thus, top cell bit lines and top cell memory cells are provided in areas overlapping areas of word line contacts. Although the word line decoders and bit line decoders are not shown, they may be positioned generally in the same areas as the corresponding the word line contacts and bit line contacts, respectively.

Fig. 5C is a cross-sectional view of a section of three-dimensional crosspoint memory of Fig. 5A along a horizontal or X direction at the X-X axis shown in Fig. 5A. In this view, the bottom cell array 510, top cell array 550, and many of the same elements shown in Fig. 5B are shown, and are labeled as such. From this view, both portions of bottom

cell bit lines

510a and 510b can be seen, and both portions of top

cell bit lines

560a and 560b can be seen. Further, both sets of bottom cell

bit line contacts

520a and 520b can be seen, while the sets of top cell bit line contacts may be hidden behind the bottom cell

bit line contacts

510a and 520b. Two portions of

word lines

530a and 530c, and the corresponding

word line contacts

540a and 540c are visible from this view. Thus as shown, both bottom and top cell bit lines and memory cells are provided in areas overlapping areas of word line contacts.

Figs. 6A-6D show an example biasing scheme for operating the example three-dimensional crosspoint memory shown in Fig. 5A. In the example biasing scheme, the memory cells of the top and bottom cell arrays may receive a program signal or a read signal at a combination of the word line decoders and the bit line decoders. Each decoder receiving a signal determines a line to activate based on the signal. As shown in the previous figures, the word lines and bit lines are arranged in a grid, whereby memory cells are positioned, and thus data is stored, at the intersections between the word lines and bit lines. Activation of a word line and one or more intersecting bit lines causes data to be programed or read from the memory cells at the intersections.

The example of Fig. 6A shows two cells A and B being programmed or read from based on activation of the word lines and bit lines that intersect at the respective cells. In the example of cell A, word line 600 intersects with bit line 604. Thus, a signal to the word line decoder of word line 600 may indicate to activate word line 600, and to maintain the other word lines of the same word line decoder as inactive. Similarly, a signal to the bit line decoder of bit line 604 may indicate to activate bit line 604, and to maintain the other bit lines of the same bit line decoder as inactive. In the example of cell B, word line 600 intersects with bit line 614. Thus, a signal to the word line decoder of word line 600 may indicate to activate word line 600, and to maintain the other word lines of the same word line decoder as inactive. Similarly, a signal to the bit line decoder of bit line 614 may indicate to activate bit line 614, and to maintain the other bit lines of the same bit line decoder as inactive.

In the example of Fig. 6A, bit line 604 is a bottom cell bit line (BCBL) connected to the bottom cell bit line decoder through a bottom cell bit line contact (BCBL contact) . Cell A is positioned between word line 600 and BCBL 604, making it a memory cell of the bottom array. Conversely, bit line 614 is a top cell bit line (TCBL) connected to the top cell bit line decoder through a top cell bit line contact (TCBL contact) . Cell B is positioned between word line 600 and TCBL 614, making it a memory cell of the top array. Thus, Fig. 6A shows how the word lines, BCBLs, and TCBLs may be arranged in order to activate memory cells of both the bottom cell array and the top cell array of the memory.

Activation of a word line or bit line may involve raising a voltage of the line above a threshold high voltage value (+Vhh) , or lowering a voltage of the line below a threshold low voltage value (-Vll) . Stated more generally, activation of the line may involve raising an absolute value of the voltage of the line above a threshold mark. In some examples, the threshold high voltage value may be between 5 V and 20 V, and preferably between 10 V and 15 V. In some examples, the threshold low voltage value may be between -20 V and -5 V, and preferably between -15 V and -10V. The threshold high and low voltage values differ from a typical voltage of the word and bit lines when they are inactive. The inactive or unbiased voltage values are referred to herein at Vuw for the word lines, and as Vub for the bit lines. The absolute value of Vuw is less than the threshold values +Vhh and -Vll, may preferably be no greater than 2 V, and even more preferably 0 V. Similarly, the absolute value of Vub is less than the threshold values +Vhh and –Vll, may preferably be no greater than 2 V, and even more preferably 0 V.

In the example of Fig. 6A, the biasing scheme for activating cell A includes raising the voltage of word line 600 at or above the threshold high voltage value (+Vhh) , and lowering the voltage of bit line 604 at or below the threshold low voltage value (-Vll) . Similarly, the biasing scheme for activating cell B includes raising the voltage of word line 600 at or above the threshold high voltage value (+Vhh) , and lowering the voltage of bit line 614 at or below the threshold low voltage value (-Vll) . As noted above, activation of a given cell may allow for data to be programmed to the cell, or for data to be read from the cell. In some examples, activation of cell may involve both reading data from the cell and further reprogramming the cell with the data that was read.

In the example of Fig. 6A, when the word line decoder activates word line 600, the remaining, unselected word lines connected to the word line decoder may stay inactive. The inactive word lines may have a voltage of Vuw, which in some examples may be about 0V. Similarly, when the bit line decoder activates bit line 604 or bit line 614, the remaining, unselected TCBL and BCBL bit lines may stay inactive. The inactive bit lines may have a voltage of Vub, which in some examples may be about 0V.

Table 1 summarizes the example biasing scheme of Fig. 6A with respect to each of Cells A and B:

Table 1

	Cell A	Cell B
Selected WL	+Vhh	+Vhh
Selected BL	-Vll	-Vll
Unselected WL (s)	Vuw	Vuw
Unselected BL (s)	Vub	Vub

Table 2 also summarizes the example biasing scheme of Fig. 6A with respect to each of Cells A and B, but for which the unbiased word line voltage Vuw and the unbiased bit line voltage Vub are equal to 0 V.

Table 2

	Cell A	Cell B
Selected WL	+Vhh	+Vhh
Selected BL	-Vll	-Vll
Unselected WL (s)	0	0
Unselected BL (s)	0	0

The biasing scheme of Fig. 6A is shown in greater detail in each of Figs. 6B, 6C and 6D. Fig. 6B is a cross-sectional view of a section of three-dimensional crosspoint memory of Fig. 6A along a vertical or Y direction at the Y-Y axis shown in Fig. 6A. Fig. 6C is a cross-sectional view of a section of three-dimensional crosspoint memory of Fig. 6A along a horizontal or X direction at the X-X axis shown in Fig. 6A.

Each of Figs. 6B and 6C show that cell A is included in a first cell stack (Cell stack 1) of a bottom cell array that is positioned between the word lines (BCWL) , including word line 600, and the BCBLs, including bit line 604, and that cell B is included in a second cell stack (Cell stack 2) of a top cell array that is positioned between the word lines (BCWL) , including word line 600, and the TCBLs, including bit line 614. As can be seen from the figures, the cell stacks occupy nearly all of the space between the top bit lines and the bottom bit lines, requiring only a small space for the word lines and the top cell bit lines to be connected to their respective decoders. This results in increased memory density in the memory device, thus improving storage efficiency.

When one of a high voltage or a low voltage is used for activating a word line of a given cell, the other one of the high voltage or low voltage is used to activate the bit line of that same given cell. For instance, in the particular example of Fig. 6A, all of the word lines are activated by raising their voltage, and all of the bit lines are activated by lowering their voltage. However, in other examples, all of the word lines may be activated by lowering their voltage, and the bit lines may be activated by raising their voltage.

In the above examples, it will be appreciated that any cell of the memory may be accessed (e.g., read, programmed) using the above discussed example biasing schemes. Furthermore, it will also be appreciated that any two cells in vertical alignment with one another may be accessed (e.g., read, programmed) at the same time. This is possible by virtue of the two vertically aligned cells sharing a word line and being connected to separate bit line blocks. For example, in Figs. 6A, 6B and 6C, each of may be accomplished by applying a bias voltage +Vhh to word line 600 and a bias voltage –Vll to each of

bit lines

604 and 614.

The present embodiment makes it possible to access two memory cells from a single block of memory without increasing the number of word line drivers or bit line drivers for the memory. In the case of the word line drivers, it can be seen from Figs. 6A, 6B and 6C that only a single word line driver is need to access both cells A and B. In the case of the bit line drivers, adjacent memory blocks are arranged so that they share a bit line driver, so that the overall number of bit line drivers for the memory does not need to be increased. Thus, two cells of each memory block may be accessed the same time, thus doubling the throughput, without having to provide additional word line or bit line drivers.

In the above examples, for a page of memory including 128 blocks, the access size of the page may be increased from 128 bits (16 bytes) to 256 bits (32 bytes) . Similar improvements may be made to memories having pages of different sizes, whereby the access size of the page would double since two cells of each block could be accessed at the same time. This makes the memory more suitable for applications that require large access sizes, such as a server application for which an access size of 256 bits is preferable.

Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

A method for accessing memory cells of a three-dimensional memory comprising:

accessing memory cells of a first bottom cell block of a bottom cell array and a first top cell block of a top cell array above the bottom cell array by biasing one word line of a first portion of word lines, one bit line of a first portion of bottom cell bit lines, and one bit line of a first portion of top cell bit lines; and

accessing memory cells of a second bottom cell block of the bottom cell array and offset from the first bottom cell block and a second top cell block of the top cell array and offset from the first top cell block by biasing one word line of a second potion of word lines, one bit line of a second portion of bottom cell bit lines, and one bit line of a second portion of top cell bit lines.
The method according to claim 1, wherein the memory cells of the first bottom cell block and the first top cell block are accessed simultaneously, and wherein memory cells of the second bottom cell block and the second top cell block are accessed simultaneously.
The method according to claim 1, wherein accessing at least one cell of a cell block comprises raising a voltage of a word line coupled to the at least one cell above a first threshold value, and lowering a voltage of a bit line coupled to the at least one cell below a second threshold value.
The method according to claim 3, wherein the first threshold value is between about 5 to 20 V, and wherein the second threshold value is between about -20 to -5 V.
The method according to claim 3, wherein each unbiased word line has a voltage of about 2 V, and wherein each unbiased bit line has a voltage of about 2 V.
The method according to claim 3, wherein:

accessing at least one cell of the memory block comprises maintaining a voltage of each unbiased word line coupled to the memory block at a first unbiased voltage value, and maintaining a voltage of each unbiased bit line coupled to the memory block at a second unbiased voltage value.
The method according to claim 6, wherein the first unbiased voltage value is about 2 V, and wherein the second unbiased voltage value is about 2 V.
The method according to claim 6, wherein each unbiased word line has a voltage of about 0 V, and wherein each unbiased bit line has a voltage of about 0 V.
The method according to claim 1, wherein accessing memory cells comprises at least one of reading data from the memory cells or programming data to the memory cells.
The method according to claim 1, wherein the three-dimensional memory comprises a plurality of pages, wherein each page includes a plurality of memory blocks, and wherein accessing memory cells of a given page of the three-dimensional memory comprises accessing two memory cells of each memory block at one time.
The method according to claim 10, wherein each page includes 128 memory blocks, and wherein accessing memory cells of a given page is performed at a rate of 256 memory cells at a time.
A method of accessing memory cells of a three-dimensional memory comprising:

accessing memory cells of a bottom cell block of a bottom cell array one cell at a time by biasing one word line of a plurality of word lines and one bit line of a plurality of bottom cell bit lines; and

accessing memory cells of a top cell block of a top cell array offset from the bottom cell block and positioned above the bottom cell array in a depth direction one cell at a time by biasing one word line of the plurality of word lines and one bit line of a plurality of top cell bit lines,

wherein a first memory cell of the bottom cell block and a second memory cell of the top cell block positioned above the first memory cell are accessed at the same time by biasing a word line of the plurality of word lines that is connected to both the first memory cell and the second memory cell.
The method according to claim 12, wherein biasing one word line of the plurality of word lines comprises raising a voltage of the one word line above a first threshold value.
The method according to claim 13, wherein biasing one word line of the plurality of word lines comprises maintaining a voltage of the plurality of word lines aside from the one word line at an unbiased word line voltage value.
The method according to claim 13, wherein biasing a first bit line of the plurality of bottom cell bit lines and a second bit line of the plurality of top cell bit lines comprises lowering a voltage of the first bit line and the second bot line below a second threshold value.
The method according to claim 15, wherein biasing a first bit line of the plurality of bottom cell bit lines and a second bit line of the plurality of top cell bit lines comprises maintaining a voltage of the plurality of bottom cell bit lines and the plurality of top cell bit lines aside from the first bit line and the second bit line at an unbiased bit line voltage value.
The method according to claim 12, wherein accessing memory cells comprises at least one of reading data from the memory cells or programming data to the memory cells.
The method according to claim 12, wherein the three-dimensional memory comprises a plurality of pages, wherein each page includes a plurality of memory blocks, and wherein accessing memory cells of a given page of the three-dimensional memory comprises accessing two memory cells of each memory block at one time.
The method according to claim 18, wherein each page includes 128 memory blocks, and wherein accessing memory cells of a given page is performed at a rate of 256 memory cells at a time.
The method according to claim 12, wherein the bottom cell block is positioned below the plurality of word lines in the depth direction and the top cell block is positioned above the plurality of word lines in the depth direction.