WO2022057749A1

WO2022057749A1 - Method and apparatus for handling missing memory page abnomality, and device and storage medium

Info

Publication number: WO2022057749A1
Application number: PCT/CN2021/117898
Authority: WO
Inventors: 王义彬; 王龙; 杨栋
Original assignee: 华为技术有限公司
Priority date: 2020-09-21
Filing date: 2021-09-13
Publication date: 2022-03-24
Also published as: CN114253458B; CN114253458A

Abstract

A method and apparatus for handling a missing memory page abnormality, and a device and a storage medium, relating to the technical field of computers. By means of the method and apparatus, the device and the storage medium, pre-fetch information is predicted according to historical memory access information, and data corresponding to the pre-fetch information is read into a memory, instead of blindly pre-fetching consecutive data of a plurality of memory page addresses into the memory. As such, the pre-fetch hit rate is higher, the number of subsequent missing page abnormalities can be effectively reduced, a memory access delay can be effectively reduced, pre-fetched data is more effective, and the loss of memory resources is lower, such that there is less strain on memory resources.

Description

Method, device, device and storage medium for processing memory page fault exception

technical field

The embodiments of the present application relate to the field of computer technologies, and in particular, to a method, apparatus, device, and storage medium for processing a memory page fault exception.

Background technique

The memory includes multiple consecutive memory pages. When the processor needs to access memory data, if the memory data is not in the memory pages included in the memory, a page fault exception will occur.

In the related art, a disk includes a SWAP partition, and the SWAP partition is used to store data on memory pages that are rarely accessed by a processor, that is, data on cold pages. When a page fault exception occurs, the processor reads the corresponding data from the SWAP partition, and loads the read data into the corresponding memory page in the memory. Among them, in order to speed up the processing efficiency of page fault exception and reduce the memory access delay, when a page fault exception occurs, the processor starts from the memory page where the currently accessed memory data is located, and pre-reads multiple consecutive memories from the SWAP partition The data on the page is loaded into the corresponding memory page for subsequent continuous access.

However, when a page fault exception occurs, the data on multiple consecutive memory pages are blindly pre-read into the memory. In the case of non-sequential memory page access, the pre-read data includes a lot of data that is not really to be accessed. In this way, the memory resources will be tight, and the page fault exception will be triggered again in the future, which increases the memory access delay.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a method, apparatus, device, and storage medium for processing abnormal page faults in memory, which can effectively reduce the number of abnormal page faults, reduce memory access latency, and reduce consumption of memory resources. The technical solution is as follows:

In a first aspect, a method for processing a page fault exception in memory is provided, and the method includes:

Determine the information of the target memory page, obtain the first information, and the target memory page is the memory page where the page fault exception occurs this time; It is used to characterize the law of historical access to memory; the data corresponding to multiple prefetch information is read into the corresponding memory page in the memory.

In the embodiment of the present application, since the historical memory access information can represent the law of historical memory access, the prefetch information is predicted according to the historical memory access information, so that the data corresponding to the prefetch information is read into the memory, which is not blind. Prefetching data from multiple consecutive memory page addresses into memory means that this solution has a higher prefetching hit rate, which can effectively reduce the number of subsequent page fault exceptions, effectively reduce memory access latency, and this solution prefetches data. It is more efficient, the consumption of memory resources is lower, and memory resources are not very tight.

In the embodiment of the present application, if the memory data to be read by the computer device is not in the memory pages included in the memory, a page fault exception occurs, and when a page fault exception occurs, the information of the memory page where the page fault exception occurs this time is determined, That is, the information of the target memory page is determined, and the first information is obtained.

It should be noted that, in the embodiment of the present application, the information of the memory page is any information that can identify the memory page, such as the address of the memory page, the number of the memory page, etc., and the information of the memory page is used as the memory in the embodiment of the present application The address of the page is taken as an example to introduce.

Exemplarily, when a page fault exception occurs, the computer device converts the virtual address of the memory data to be read this time into the address of the target memory page to obtain the first address. It should be noted that the first address is the start address of the target memory page.

Optionally, the historical memory access information is determined according to the sequence relationship between memory pages in which a page fault exception occurs during historical memory access.

Optionally, the computer device predicts a plurality of prefetch information corresponding to the first information according to the historical memory access information, including: according to the correlation between the information of the memory page in which the page fault exception occurs in the historical memory access information and the prefetch information. relationship, and obtain multiple pieces of prefetch information corresponding to the first information.

Optionally, the historical access memory information includes the sequence number, the correspondence between page fault information and prefetch information, the page fault information refers to the information of the memory page where the page fault exception occurs, and the serial number is obtained by performing a hash operation on the page fault information. owned.

Based on this, the computer device obtains a plurality of prefetch information corresponding to the first information according to the association relationship between the information of the memory page in which the page fault exception occurs in the historical memory access information and the prefetch information, including: performing the processing on the first information. A hash operation is performed to obtain a first sequence number; according to the first sequence number and the first information, a plurality of corresponding prefetch information is searched from the historical access memory information.

Exemplarily, taking the first information as the first address and the prefetch information as the prefetch address as an example, the page fault address is the memory page address that triggers the page fault exception stored in the historical access memory information, and the historical access memory information can store multiple Each serial number and corresponding records can be stored in the record corresponding to each serial number, and a plurality of prefetch addresses can be stored in the record corresponding to each page fault address.

It should be noted that a row number threshold (ROW) is configured in the computer device, and the row number threshold is used to indicate the maximum value of the hash result of the memory page information, that is, to limit the maximum value of the sequence number.

In the embodiment of the present application, when the computer device acquires a plurality of corresponding prefetch information from the historical access memory information according to the first serial number and the first information, the historical access memory information may store a plurality of corresponding prefetch information from the first information. For the prefetch information, it is also possible that multiple pieces of prefetch information corresponding to the first information are not stored. Next, these two cases will be described separately.

The case where multiple prefetch information corresponding to the first information is stored in the historical access memory information:

According to the first serial number and the first information, the computer device searches for a plurality of corresponding prefetch information from the historical access memory information, including: searching for the record where the first serial number and the first information are located from the historical access memory information; If the first sequence number and the record where the first information is located are found in the memory information, the corresponding pieces of prefetch information are searched from the record where the first sequence number and the first information are located.

Optionally, the computer device searches for a plurality of corresponding prefetch information from the record where the first sequence number and the first information are located, including: searching for the corresponding multiple prefetch information from the record where the first sequence number and the first information are located according to the prefetch depth. prefetch information. That is, after the computer device searches for the corresponding prefetch information from the record in which the first sequence number and the first information are located, the computer device uses a plurality of prefetch information whose total number does not exceed the prefetch depth in the record as the found plurality of prefetch information. get information.

It should be noted that, a prefetch depth (prefetch depth, PD) is also configured in the computer device, and the prefetch depth is used to indicate the maximum number of multiple prefetch information acquired each time.

The case where multiple prefetch information corresponding to the first information is not stored in the historical access memory information:

In the embodiment of the present application, after the computer device searches for the first serial number and the record where the first information is located from the historical access memory information, it further includes: if the first serial number and the record where the first information is located are not found from the historical access memory information record, the historical access memory information is updated according to the first sequence number and the first information.

Optionally, the computer device updates the historical access memory information according to the first serial number and the first information, including: when the historical access memory information does not store the first serial number and the first information, creating the first serial number and the first information in the historical access memory information. The record of the serial number and the first information is to update the historical access memory information; in the case where the historical access memory information is stored with the first serial number, but the first information is not stored, the first information is stored in the record of the first serial number, to Update historical access memory information.

Optionally, the computer equipment stores the first information in the record of the first serial number, including: if the number of page fault information stored in the record of the first serial number does not reach the first quantity threshold, then store in the record of the first serial number. The first information; if the number of page-missing information stored in the record of the first sequence number reaches the first quantity threshold, then delete the page-missing information with the earliest storage time and the corresponding prefetch information in the record of the first sequence number. The first information is stored in the record.

It should be noted that, in this embodiment of the present application, the computer device is further configured with a first quantity threshold (ASSOC), and the first quantity threshold is used to indicate the maximum quantity of page fault information that can be stored in a record of the same serial number. In this way, if the number of page fault information stored in the record of the first serial number reaches ASSOC, that is, the multiple information positions corresponding to the first serial number are full, the computer device deletes the earliest stored page fault in the record of the first serial number information and the corresponding prefetch information, and store the first information in the records corresponding to the first sequence, that is, eliminate the old information, and update the latest information in the historical access memory information.

The above-mentioned method of storing the first information in the record of the first serial number can be understood as a least recently used (LRU) method, in which the earliest stored page fault information is eliminated.

Regardless of whether multiple prefetch information corresponding to the first information is stored in the historical access memory information, after the computer device determines the first information, the historical access memory information can also be updated according to the page fault queue.

That is, after the computer device searches for a plurality of prefetch information corresponding to the first information from the historical access memory information, the method further includes: updating the historical access memory information according to the page fault queue, and the page fault queue is used to store the occurrences in chronological order. Information about memory pages with page fault exceptions. It should be noted that a page-missing queue (miss queue, MQ) is also stored in the computer device.

Optionally, the computer device updates historical access memory information according to the page fault queue, including: storing the first information in the page fault queue; acquiring the memory in the page fault queue that is located before the first information and whose quantity does not exceed a second quantity threshold. Page information, obtain one or more second information; store the first information as prefetch information corresponding to each of the one or more second information in the historical access memory information.

Optionally, the computer device is also configured with a page fault queue length (MQ length, MQ_L), and the page fault queue length is used to indicate the maximum amount of memory page information that can be stored in the page fault queue, so as to ensure that Data timeliness of memory page information.

Optionally, the computer device stores the first information as prefetch information corresponding to each of the one or more second information in the historical memory access information, including: according to the first information and the one or more second information. The positional relationship of each second information in the page fault queue in the second information, and the association relationship between the first information and each second information is stored in the historical memory access information.

Optionally, each of the one or more second information corresponds to one or more related groups, the number of the one or more related groups is the second quantity threshold, and each related group corresponds to one or multiple information locations, each relevant group corresponds to a relevant level, and each relevant group is used to store prefetch information; the computer device is in the missing page according to the first information and each second information in the one or more second information. The positional relationship in the queue, storing the association relationship between the first information and each second information in the historical memory access information, including: selecting one second information from the one or more second information, for the selected second information The information performs the following operations until the following operations are performed on each of the one or more second information: determine the first information according to the position of the first information and the selected second information in the page fault queue The reference level is obtained with the correlation level of the selected second information; the first information is stored in the first information position of the target correlation group, and the target correlation group is that the correlation level corresponding to the selected second information is the reference level related groups.

It should be noted that the closer the positions of the two memory page information stored in the page fault queue are, the higher the correlation degree (correlation degree) of the two memory page information to a certain extent.

Because before storing the first information as the prefetch information in the target related group in the historical access memory information, the prefetch information (that is, the memory page information is stored) may already be stored in the first information position of the target related group, Then, the computer device needs to first move and/or delete the prefetched information stored in the relevant group included in the corresponding second information, and then store the first information in the first information position of the target relevant group.

Optionally, in this embodiment of the present application, the computer device is further configured with a third quantity threshold (SUCC), where the third quantity threshold is used to indicate the maximum quantity of prefetch information that can be stored in each relevant group. The number of the one or more information locations is a third number threshold, and the one or more relevant groups are sequentially arranged in the order of the relevant level; the computer device stores the first information in the first information location of the target relevant group, including :

If the memory page information is not stored in the first information position of the target related group, the computer device stores the first information in the first information position of the target related group;

If memory page information is stored in the first information location, and the number of memory page information stored in the target related group does not reach the third quantity threshold, the computer device moves each memory page information stored in the target related group backward by one After the information location, the first information is stored in the first information location;

If the number of memory page information stored in the target related group reaches the third number threshold, and the target related group is the last related group corresponding to the selected second information, the computer device deletes the last memory page information in the target related group , after moving the remaining memory page information by one information position, the first information is stored in the first information position;

If the number of memory page information stored in the target related group reaches the third number threshold, the target related group is not the last related group corresponding to the selected second information, and the related group corresponding to the selected second information is located in the target related group If there is an idle information position in the subsequent related groups, the computer device moves the target related group and each memory page information before the first free information position in the related group after the target related group by one information position, and then the first information is stored at the first information location;

If the number of memory page information stored in the target related group reaches the third number threshold, the target related group is not the last related group corresponding to the selected second information, and the related group corresponding to the selected second information is located in the target related group There is no free information location in the subsequent related group, then the computer device deletes the last memory page information in the last related group corresponding to the selected second information, and deletes the target related group and the related group located after the target related group. After the rest of the information of the memory pages are moved back by one information position, the first information is stored in the first information position.

It can be seen from the above that the computer equipment stores the first information in the first information position of the target related group in a sequential backward manner. , MRU) method to insert the first information into the target related group corresponding to each second information.

In the above manner, the computer equipment obtains prefetch information from the stored historical memory access information and updates the historical memory access information after each page fault exception occurs. A prefetching algorithm is used to predict the prefetching information, that is, the computer equipment is configured with a prefetching algorithm, the computer equipment continuously updates the historical memory access information by running the prefetching algorithm, and records the historical memory access rules through the historical access memory information.

Optionally, the computer device may store the historical access memory information in any manner of storing data, for example, storing the historical access memory information in a table form. Alternatively, the historical access memory information in tabular form may be referred to as a multi-level correlation table (MLCT).

Through the above process, a plurality of prefetch information corresponding to the memory page of the current page fault exception is obtained, and historical memory access information (such as a multi-level correlation table) is updated. Since the historical memory access information is gradually established according to the sequence relationship between the memory pages of the page fault exception occurred in the historical memory access, the multiple prefetch information obtained from the historical memory access information is very likely to be the first time in the historical access. After the memory data corresponding to a message, the memory page information corresponding to the memory data that needs to be accessed continuously, that is, the data corresponding to the multiple prefetch messages read by this solution is very likely to be the memory to be accessed by the processor next. data, that is, this solution pre-reads memory data more accurately, which can avoid serious waste of memory resources, and can reduce the probability of page fault exceptions again, that is, improve the prefetch hit rate and effectively reduce the memory access delay. .

It should be noted that there are many memory access modes applied in computer equipment, such as sequential memory access mode and non-sequential memory access mode. The non-sequential memory access mode includes strided mode and mixed mode. This solution Learning the rules of historical memory access through the above method establishes historical access memory information, such as MLCT, instead of blindly prefetching data corresponding to consecutive memory page addresses into memory. All have good results.

Optionally, in this embodiment of the present application, the computer device reads the data corresponding to the plurality of prefetch information to the corresponding memory page in the memory, including: reading from the specified storage space according to the plurality of prefetch information. Fetch the corresponding data to the corresponding memory page in the memory.

Optionally, the designated storage space is the storage space of the SWAP partition divided on the disk included in the device, or the storage space of the XL-FLASH memory included in the device, or the storage space of the remote storage.

It should be noted that a designated storage space is set in the computer device for storing the data of the cold page, that is, storing the data not stored in the memory page of the memory. Among them, the read and write speed of XL-FLASH device is faster than that of SWAP partition of disk, and its price is lower than that of memory stick (such as dynamic random access memory (DRAM)), and its capacity is large, which can provide several times more than memory. For computer equipment, the accessible memory space includes DRAM and XL-FLASH devices, that is, by adding XL-FLASH devices, the accessible memory space is increased several times, that is, visible to users The fetch space has increased a lot.

In addition, it should be noted that with regard to the remote storage, for example, a storage device such as a disk and XL-FLASH included in a remote computer device, if the device wants to access the storage space of the remote storage, it can be accessed through the network, such as through high-speed Internet access remote storage.

Optionally, the method further includes: determining the cold page in the memory according to the access time and the access quantity of the memory page in the memory in the first time period; and moving the data on the cold page from the memory to the designated storage space. That is, in addition to prefetching memory data from the specified storage space through the above method, the processor can also combine the method of scanning and eliminating cold pages in the memory to move the data on the cold pages in the memory to the specified storage space, That is, cold pages in memory are eliminated. In this way, more memory space can be freed up for storing hot memory data, thereby improving memory resource utilization.

Optionally, the method further includes: receiving a prefetch algorithm performance query instruction; displaying prefetch algorithm performance information, where the prefetch algorithm performance information includes a prefetch accuracy rate and a prefetch coverage rate; wherein the prefetch accuracy rate is determined by the total prefetch rate. The number and the number of prefetch hits are determined. The prefetch coverage rate is determined by the total number of prefetches and the total number of accesses. The total number of prefetches refers to the total number of all prefetch information acquired in the second time period. The number of prefetch hits refers to The total number of accessed memory pages in the memory pages corresponding to all the prefetch information acquired in the second time period, and the total number of accesses refers to the total number of all memory pages accessed in the second time period.

It should be noted that the prefetch accuracy rate can represent the accuracy of the prefetch algorithm to a certain extent, and the prefetch coverage rate can represent the effectiveness of the prefetch algorithm for applications running on the device to a certain extent.

Optionally, after displaying the prefetch algorithm performance information, the computer device further includes: receiving a prefetch parameter adjustment instruction, where the prefetch parameter adjustment instruction is determined by user feedback on the prefetch algorithm performance information; and according to the prefetch parameter adjustment instruction, update the history. Access memory information. That is to say, the above method of prefetching memory data can be understood as being based on a prefetching algorithm, and the user can configure the prefetching parameters included in the prefetching algorithm, such as the row number threshold, the first number threshold, the second number threshold, the third threshold. The number threshold, prefetch depth, page fault queue length, etc., the user can also adjust the prefetch parameters configured in the computer device. Taking historical access memory information as MLCT as an example, in general, the larger the corresponding multi-level correlation table after the user adjusts the prefetch parameters, the more historical memory access information the multi-level correlation table can record. The performance of the algorithm is better.

In a second aspect, a device for processing a memory page fault exception is provided, and the device for processing a memory page fault exception has the function of implementing the behavior of the method for processing the memory page fault exception in the first aspect. The apparatus for processing a memory page fault exception includes one or more modules, and the one or more modules are used to implement the processing method for a memory page fault exception provided in the first aspect.

That is, a device for processing a memory page fault exception is provided, and the device includes:

The first determining module is used to determine the information of the target memory page, and obtain the first information, and the target memory page is the memory page where the page fault exception occurs this time;

a prediction module, configured to predict a plurality of prefetch information corresponding to the first information according to the historical memory access information, and the historical memory access information is used to characterize the law of historical memory access;

The reading module is used for reading the data corresponding to the plurality of prefetch information to the corresponding memory page in the memory.

Optionally, the historical memory access information is determined according to the sequence relationship between memory pages in which a page fault exception occurs during historical memory access;

The prediction module includes:

an obtaining unit, configured to obtain a plurality of prefetch information corresponding to the first information according to the association relationship between the information of the memory page in which the page fault exception occurs in the historical memory access information and the prefetch information;

Optionally, the historical memory access information includes the sequence number, the correspondence between page fault information and prefetch information, the page fault information refers to the information of the memory page where the page fault exception occurs, and the serial number is obtained by performing a hash operation on the page fault information. owned;

The acquisition unit includes:

a hash subunit, configured to perform a hash operation on the first information to obtain the first serial number;

The search subunit is configured to search for a plurality of corresponding pieces of prefetch information from the historical memory access information according to the first sequence number and the first information.

Optionally, lookup subunits are specifically used to:

Find the first serial number and the record where the first information is located from the historical memory access information;

If the first sequence number and the record where the first information is located are found from the historical memory access information, the corresponding pieces of prefetch information are searched from the record where the first sequence number and the first information are located.

Optionally, lookup subunits are specifically used to:

According to the prefetch depth, the corresponding pieces of prefetch information are searched from the first sequence number and the record where the first information is located.

Optionally, the device also includes:

The first update module is used to update the historical memory access information according to the first sequence number and the first information if multiple prefetch information corresponding to the first information is not obtained, and the first sequence number is to hash the first information obtained by operation.

Optionally, the first update module includes:

The first update unit is used to create the record where the first sequence number and the first information are located in the historical memory access information, to update the historical memory access information;

The second updating unit is configured to store the first information in the record of the first serial number to update the historical memory access information when the first serial number is stored in the historical memory access information but the first information is not stored.

Optionally, the second update unit includes:

The first storage subunit is used to store the first information in the record of the first serial number if the quantity of the page fault information stored in the record of the first serial number does not reach the first quantity threshold;

The second storage subunit is used to delete the page fault information with the earliest storage time and the corresponding prefetch information in the record of the first serial number if the quantity of the page fault information stored in the record of the first serial number reaches the first quantity threshold, The first information is stored in the record of the first serial number.

Optionally, the device also includes:

The second update module is used to update historical memory access information according to the page fault queue, and the page fault queue is used to store the information of the memory pages in which the page fault exception occurs in chronological order.

Optionally, the second update module includes:

a first storage unit for storing the first information in the page fault queue;

an acquisition unit, configured to acquire the memory page information that is located before the first information and whose quantity does not exceed the second quantity threshold in the page fault queue, and obtains one or more second information;

The second storage unit is configured to store the first information as prefetch information corresponding to each of the one or more second information in the historical memory access information.

Optionally, the second storage unit includes:

The third storage subunit is configured to store the first information and each second information in the historical memory access information according to the positional relationship between the first information and each second information in the one or more second information in the page fault queue The relationship between the two information.

Optionally, each of the one or more second information corresponds to one or more related groups, the number of the one or more related groups is the second quantity threshold, and each related group corresponds to one or multiple information locations, each related group corresponds to a related level, and each related group is used to store prefetch information;

The third storage subunit is specifically used for:

Select one second information from the one or more second information, and perform the following operations on the selected second information until the following operations are performed on each of the one or more second information:

According to the positions of the first information and the selected second information in the page fault queue, determine the correlation level of the first information and the selected second information, and obtain the reference level;

The first information is stored in the first information position of the target correlation group, and the target correlation group is a correlation group whose correlation level corresponding to the selected second information is a reference level.

Optionally, the number of the one or more information locations is a third number threshold, and the one or more related groups are arranged in order of related levels;

The third storage subunit is specifically used for:

If memory page information is stored in the first information location, and the number of memory page information stored in the target related group does not reach the third quantity threshold, move each memory page information stored in the target related group by one information location. After that, store the first information in the first information position;

If the number of memory page information stored in the target related group reaches the third number threshold, and the target related group is the last related group corresponding to the selected second information, the last memory page information in the target related group is deleted, and the After the remaining memory page information is moved back by one information position, the first information is stored in the first information position;

If the number of memory page information stored in the target related group reaches the third number threshold, the target related group is not the last related group corresponding to the selected second information, and the related group corresponding to the selected second information is located in the target related group If there is an idle information position in the subsequent related groups, the target related group and each memory page information before the first free information position in the related group after the target related group are moved back by one information position, and the first Information is stored in the first information location;

If the number of memory page information stored in the target related group reaches the third number threshold, the target related group is not the last related group corresponding to the selected second information, and the related group corresponding to the selected second information is located in the target related group If there is no free information location in the subsequent related groups, the last memory page information in the last related group corresponding to the selected second information is deleted, and the target related group and the related group located after the target related group are deleted. After the rest of the memory page information is moved back by one information position, the first information is stored in the first information position.

Optionally, the reading module includes:

The reading unit is configured to read the corresponding data from the specified storage space to the corresponding memory page in the memory according to the plurality of prefetch information.

Optionally, the device also includes:

The second determining module is configured to determine the cold page in the memory according to the access time and the access quantity of the memory page in the memory in the first time period;

The move module is used to move data on cold pages from memory to the specified storage space.

Optionally, the device also includes:

a first receiving module, configured to receive a prefetch algorithm performance query instruction;

The display module is used to display the performance information of the prefetching algorithm, and the performance information of the prefetching algorithm includes the prefetching accuracy rate and the prefetching coverage rate;

Among them, the prefetch accuracy rate is determined by the total number of prefetches and the number of prefetch hits, the prefetch coverage rate is determined by the total number of prefetches and the total number of accesses, and the total number of prefetches refers to all the prefetch information obtained in the second time period. The total number of prefetch hits refers to the total number of memory pages accessed in the memory pages corresponding to all prefetch information obtained in the second time period, and the total number of accesses refers to all the memory accessed in the second time period. The total number of pages.

Optionally, the device also includes:

a second receiving module, configured to receive a prefetch parameter adjustment instruction, where the prefetch parameter adjustment instruction is determined by user feedback on the performance information of the prefetch algorithm;

The third update module is used to adjust the instruction according to the prefetch parameter and update the historical memory access information.

In a third aspect, a computer device is provided, the computer device includes a processor and a memory, the memory is used for storing a program for executing the method for processing a memory page fault exception provided in the first aspect, and a memory for implementing The data involved in the method for processing a memory page fault exception provided by the first aspect. The processor is configured to execute programs stored in the memory. The operating means of the storage device may further include a communication bus for establishing a connection between the processor and the memory.

In a fourth aspect, a computer-readable storage medium is provided, where instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium runs on a computer, the computer executes the processing of the memory page fault exception described in the first aspect. method.

In a fifth aspect, a computer program product containing instructions is provided, which, when running on a computer, enables the computer to execute the method for processing a memory page fault exception described in the first aspect.

The technical effects obtained by the second aspect, the third aspect, the fourth aspect and the fifth aspect are similar to the technical effects obtained by the corresponding technical means in the first aspect, and will not be repeated here.

The technical solutions provided in the embodiments of the present application can at least bring the following beneficial effects:

In the embodiment of the present application, since the historical memory access information can represent the regularity of the historical memory access, the prefetch information is predicted according to the historical memory access information, so that the data corresponding to the prefetch information is read into the memory, which is not blind. Prefetching data of multiple consecutive memory page addresses into memory means that this solution has a higher prefetching hit rate, which can effectively reduce the number of subsequent page fault exceptions, effectively reduce memory access latency, and this solution prefetches data. It is more efficient, the consumption of memory resources is lower, and memory resources are not very tight.

Description of drawings

1 is a schematic structural diagram of a computer device provided by an embodiment of the present application;

FIG. 2 is a flowchart of a method for processing a memory page fault exception provided by an embodiment of the present application;

3 is a schematic diagram of a page fault queue provided by an embodiment of the present application;

4 is a schematic diagram of obtaining a prefetch address from a stored multi-level correlation table according to an embodiment of the present application;

5 is a flowchart of another method for processing a memory page fault exception provided by an embodiment of the present application;

6 is a schematic diagram of a multi-level correlation table provided by an embodiment of the present application;

7 is a flowchart of another method for processing a memory page fault exception provided by an embodiment of the present application;

8 is a schematic diagram of a method for processing a memory page fault exception provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of another method for processing a memory page fault exception provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of an apparatus for processing a memory page fault exception provided by an embodiment of the present application;

FIG. 11 is a schematic structural diagram of another apparatus for processing a memory page fault exception provided by an embodiment of the present application;

FIG. 12 is a schematic structural diagram of another apparatus for processing a memory page fault exception provided by an embodiment of the present application;

FIG. 13 is a schematic structural diagram of another apparatus for processing a memory page fault exception provided by an embodiment of the present application.

detailed description

In order to make the objectives, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

The network architecture and service scenarios described in the embodiments of the present application are for the purpose of illustrating the technical solutions of the embodiments of the present application more clearly, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. The evolution of the architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

Please refer to FIG. 1 , which is a schematic structural diagram of a computer device according to an embodiment of the present application. The computer device includes one or more processors 101 , a communication bus 102 , memory 103 , and one or more communication interfaces 104 .

The processor 101 is a general-purpose central processing unit (CPU), a network processor (NP), a microprocessor, or one or more integrated circuits for implementing the solution of the present application, for example, an application-specific integrated circuit ( application-specific integrated circuit, ASIC), programmable logic device (programmable logic device, PLD) or a combination thereof. Optionally, the above-mentioned PLD is a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any of them. combination. In the embodiment of the present application, the processor 101 has the function of implementing the method for processing a memory page fault exception provided by the embodiment of the present application. For the specific implementation method, refer to the detailed introduction in the embodiments in FIGS. 2 to 9 .

The communication bus 102 is used to transfer information between the aforementioned components. Optionally, the communication bus 102 is divided into an address bus, a data bus, a control bus, and the like. For ease of presentation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

Optionally, the memory 103 is a read-only memory (read-only memory, ROM), a random access memory (random access memory, RAM), an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM) , optical disc (including compact disc read-only memory, CD-ROM, compact disc, laser disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or can be used for portable or any other medium that stores desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto. The memory 103 exists independently and is connected to the processor 101 through the communication bus 102, or the memory 103 is integrated with the processor 101. In this embodiment of the present application, the memory 103 includes a memory and a designated storage space, such as the storage space of an XL-FLASH device.

Communication interface 104 uses any transceiver-like device for communicating with other devices or a communication network. The communication interface 104 includes a wired communication interface, and optionally, a wireless communication interface. The wired communication interface is, for example, an Ethernet interface. Optionally, the Ethernet interface is an optical interface, an electrical interface or a combination thereof. The wireless communication interface is a wireless local area network (wireless local area network, WLAN) interface, a cellular network communication interface, or a combination thereof.

Optionally, in some embodiments, the computer device includes multiple processors, such as processor 101 and processor 105 as shown in FIG. 1 . Each of these processors is a single-core processor, or a multi-core processor. Alternatively, a processor herein refers to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).

In a specific implementation, as an embodiment, the computer device further includes an output device 106 and an input device 107 . The output device 106 communicates with the processor 101 and can display information in a variety of ways. For example, the output device 106 is a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, a projector, or the like. The input device 107 communicates with the processor 101 and can receive user input in a variety of ways. For example, the input device 107 is a mouse, a keyboard, a touch screen device, a sensor device, or the like.

In some embodiments, the memory 103 is further configured to store program codes 110 for executing the solutions of the present application, and the processor 101 can execute the program codes 110 stored in the memory 103 . The program code 110 includes one or more software modules, and the computer device can use the processor 101 and the program code 110 in the memory 103 to implement the processing method for the memory page fault exception provided in the embodiment of FIG. 2 below. Exemplarily, the program code 110 includes the first determination module, the prediction module and the reading module shown in the embodiment of FIG. 10 , and the processor 101 uses the first determination module, the prediction module and the reading module to cause a page fault exception in the memory. When the page fault is predicted, the information of the memory page for page fault prediction is determined, the prefetch information is predicted, and the memory data is pre-read to the memory page.

FIG. 2 is a flowchart of a method for processing a memory page fault exception provided by an embodiment of the present application, and the method is applied to a computer device. Please refer to FIG. 2 , the method includes the following steps.

Step 201: Determine the information of the target memory page, and obtain the first information, and the target memory page is the memory page where the page fault exception occurs this time.

In this embodiment of the present application, when the processor included in the computer device needs to access memory data, if the memory data is not in the memory page included in the memory, a page fault exception will occur.

Exemplarily, when a process running in the operating system of the computer device needs to read the memory data, according to the virtual address of the memory data to be read, from the mapping relationship between the virtual address and the physical address of the stored memory, find the corresponding If there is no corresponding virtual address and physical address in the mapping relationship, it means that the memory data to be read is not in the memory pages included in the memory, and the operating system will trigger a page fault exception.

When a page fault exception occurs, the information of the memory page where the page fault exception occurs this time is determined, that is, the information of the target memory page is determined, and the first information is obtained.

It should be noted that, in the embodiment of the present application, the information of the memory page may be any kind of information that can identify the memory page, such as the address of the memory page, the number of the memory page, etc. In the embodiment of the present application, the information of the memory page is The address of the memory page is introduced as an example. That is, when a page fault exception occurs, the address of the memory page where the page fault exception occurs this time is determined, that is, the address of the target memory page is determined, and the first address is obtained.

In the embodiment of the present application, the computer device converts the virtual address of the memory data to be read this time into the address of the target memory page to obtain the first address, and the first information is the first address. It should be noted that the first address is the starting address of the target memory page, and the starting address is a virtual address.

Exemplarily, assuming that the size of the memory is 100k, the computer device divides the memory into 25 consecutive memory pages according to each consecutive 4k, each memory page corresponds to a memory page address, and each memory page address is the address of the corresponding memory page. The starting address, for example, the address of the first memory page is 0000, the address of the second memory page is 0004, the virtual address of the memory data of this page fault exception is 0011, then the quotient obtained by dividing 0011 by 4 is multiplied by 4 , that is, the starting address of the memory page where this page fault exception is obtained is 0008, that is, the first address is 0008.

Step 202: Predict a plurality of prefetch information corresponding to the first information according to the historical memory access information, and the historical memory access information is used to represent the regularity of the historical memory access.

In the embodiment of the present application, after obtaining the information of the memory page where the page fault exception occurred this time, that is, after obtaining the first information, the computer device predicts a plurality of prefetch information corresponding to the first information according to the historical memory access information . Among them, the historical memory access information is used to represent the law of historical memory access.

Exemplarily, the first information is a first address, the prefetch information is a prefetch address, and the computer device predicts a plurality of prefetch addresses corresponding to the first address according to historical memory access information.

There are various implementation manners for the computer device to predict the plurality of prefetch information corresponding to the first information according to the historical memory access information, one of which is described in detail below.

In this embodiment of the present application, the historical memory access information is determined according to the sequence relationship between memory pages in which a page fault exception occurs during historical memory access. The computer device acquires a plurality of prefetch information corresponding to the first information from the stored historical memory access information.

Optionally, in this implementation manner, the historical memory access information may be referred to as page fault associated information.

In the embodiment of the present application, the computer device acquires a plurality of prefetch information corresponding to the first information according to the association relationship between the information of the memory page in which the page fault exception occurs in the historical memory access information and the prefetch information. That is, the association relationship is stored in the computer device in the embodiment of the present application, and the computer device can predict the prefetch information according to the association relationship.

In the embodiment of the present application, the historical memory access information includes the sequence number, the corresponding relationship between page fault information and prefetch information. obtained by the hash operation.

Based on this, the implementation process for the computer device to obtain a plurality of prefetch information corresponding to the first information from the stored historical memory access information is as follows: the computer device performs a hash operation on the first information to obtain a first serial number, and according to the first serial number and the first information, and look up the corresponding pieces of prefetch information from the historical memory access information.

Exemplarily, taking the first information as the first address and the prefetch information as the prefetch address as an example, the computer device performs a hash operation on the first address to obtain a first serial number, and according to the first serial number and the first address, from the historical Find the corresponding multiple prefetch addresses in the memory access information. The page fault address is the address of the memory page that triggers the page fault exception stored in the historical memory access information. The historical memory access information can store multiple serial numbers and corresponding records, and the records corresponding to each serial number can store multiple page faults. address. Multiple prefetch addresses can be stored in the record corresponding to each page fault address.

Exemplarily, assuming that the memory includes 100 memory pages, that is, there are 100 memory page addresses, and assuming that the parameter of the hash operation is 10, then after hashing the memory page addresses, at most 10 serial numbers can be obtained, each A maximum of 10 memory page addresses are stored in the record corresponding to the serial number, so that the historical memory access information can store 10 records corresponding to the serial number, and the record corresponding to each serial number can store a maximum of 10 page fault addresses. Assuming that the first address is 0024, after the computer device performs a hash operation on the first address, the first sequence number is 4, then the computer device searches the stored historical memory access information for the corresponding address according to the first sequence number 4 and the first address 0024. multiple prefetch addresses.

It should be noted that a row number threshold (ROW) is configured in the computer device, and the row number threshold is used to indicate the maximum value of the hash result of memory page information (such as addresses), that is, to limit the maximum value of the sequence number. For example Typically, if the threshold of the number of rows is 10, then the sequence number can be 0-9 (or 1-10, etc.), that is, the maximum value of the sequence number is 9 (or 10, etc.).

In the embodiment of the present application, when the computer device searches the historical memory access information for a plurality of corresponding prefetch information according to the first sequence number and the first information, the historical memory access information may store a plurality of corresponding prefetch information in the historical memory access information. For the prefetch information, it is also possible that multiple pieces of prefetch information corresponding to the first information are not stored. Next, these two cases will be described separately.

The case where multiple prefetch information corresponding to the first information is stored in the historical memory access information:

The computer device searches the historical memory access information for the record where the first serial number and the first information are located. If the record where the first serial number and the first information are located is found from the historical memory access information, Find the corresponding multiple prefetch information in the records of .

Exemplarily, the computer equipment searches for the record where the first sequence number and the first address are located from the historical memory access information, and if the record where the first sequence number and the first address are located is found from the historical memory access information, then the first sequence number and the record where the first address is located are searched from the historical memory access information. The corresponding multiple prefetch addresses are searched in the record where the first address is located.

In some embodiments, after searching for the corresponding prefetch information in the record where the first sequence number and the first information are located, the computer device uses all the prefetch information in the record as the acquired multiple prefetch information. For example, the prefetch information is a prefetch address, and the computer device uses all the prefetch addresses found as multiple acquired prefetch addresses.

In other embodiments, the computer device searches for a plurality of corresponding pieces of prefetch information from the record where the first sequence number and the first information are located according to the prefetch depth. That is, after the computer device searches for the corresponding prefetch information from the record in which the first sequence number and the first information are located, multiple prefetch information whose total number does not exceed the prefetch depth in the record are used as the obtained multiple prefetch information. get information. For example, the computer device takes multiple prefetch addresses whose total number does not exceed the prefetch depth in the found records as the obtained multiple prefetch addresses.

It should be noted that a prefetch depth (PD) is also configured in the computer device, and the prefetch depth is used to indicate the maximum number of multiple pieces of prefetch information (eg, addresses) acquired each time. If the total quantity of the prefetch information in the record where the first sequence number and the first information are located does not exceed the PD, the computer device regards all the prefetch information in the record as the acquired multiple prefetch information. If the number of prefetch information in the record where the first sequence number and the first information are located exceeds the prefetch depth, the computer device uses PD pieces of prefetch information in the record as the found multiple prefetch information. PD pieces of prefetch information are randomly selected from the record, or the computer device selects PD pieces of prefetch information according to the storage time sequence or location sequence of the prefetch information.

The case where multiple prefetch information corresponding to the first information is not stored in the historical memory access information:

In this embodiment of the present application, if multiple pieces of prefetch information corresponding to the first information are not obtained, the computer device updates the historical memory access information according to the first sequence number and the first information, where the first sequence number is a The information is obtained by hash operation.

Exemplarily, the computer equipment searches for the record where the first sequence number and the first address are located from the historical memory access information, and if the record where the first sequence number and the first address are located is not found from the historical memory access information, then the computer equipment A serial number and a first address to update historical memory access information.

Wherein, when the historical memory access information does not store the first serial number and the first information, the computer device creates a record where the first serial number and the first information are located in the historical memory access information to update the historical memory access information. In the case where the historical memory access information is stored with the first serial number but does not store the first information, the computer device stores the first information in the record of the first serial number to update the historical memory access information.

Exemplarily, taking the information of the memory page as the address of the memory page as an example, when the computer device searches for the prefetch address according to the address of a memory page that triggers a page fault exception for the first time, no information is stored in the historical memory access information. , the computer device stores the first address of the current page fault exception and the first serial number obtained by hashing the first address in the historical memory access information, so as to update the historical memory access information. As the computer device continuously updates the historical memory access information according to the first address and the first serial number of each page fault exception, new serial numbers and corresponding page fault addresses are continuously added to the historical memory access information.

Wherein, an implementation manner for the computer device to store the first information in the record of the first sequence number is: if the number of page fault information stored in the record of the first sequence number does not reach the first quantity threshold, the computer device stores the first sequence number in the first sequence number. Store the first information in the record of the first serial number; if the quantity of the page fault information stored in the record of the first serial number reaches the first quantity threshold, then the computer equipment deletes the page fault information with the earliest storage time and the corresponding prefetching in the record of the first serial number information, the first information is stored in the record of the first serial number.

It should be noted that, in this embodiment of the present application, the computer device is also configured with a first quantity threshold (ASSOC), and the first quantity threshold is used to indicate the page fault information (such as an address) that can be stored in the records of the same serial number. greatest amount. In this way, if the number of page fault information stored in the record of the first serial number reaches ASSOC, the computer device deletes the earliest stored page fault information and the corresponding prefetch information in the record of the first serial number, and stores the first information in the first serial number. In the record of a serial number, the old information is eliminated, and the latest information is updated in the historical memory access information.

Exemplarily, assuming that the memory includes 100 memory pages, that is, there are 100 memory page addresses, and assuming that the row number threshold ROW is 10, after hashing the memory page addresses, at most 10 serial numbers can be obtained, each serial number. A maximum of 10 memory page addresses can be stored in the records of , so that the historical memory access information can store 10 serial numbers and corresponding records, and a maximum of 10 page fault addresses can be stored in the records of each serial number. Assuming that the first number threshold is 4, that is, each serial number stores at most 4 page fault addresses, and the record of the first serial number has already stored 4 page fault addresses, then the computer device stores the earliest of these 4 page fault addresses. The page fault address and the corresponding prefetch address are deleted, and then the first address is stored in the record corresponding to the first serial number.

It should be noted that the value of the first number threshold ASSOC may be smaller than the number of memory page addresses that each sequence number stores at most. For example, in the above example, each sequence number corresponds to storing 10 memory page addresses at most, but the first number The threshold is set to 4, which is less than 10. In this way, the computer device can reduce the amount of stored data by hashing the memory page addresses and setting the first number threshold smaller, and only store relatively new data in historical memory access information. information, while ensuring the accuracy of prefetching, and speeding up the rate of obtaining prefetching information from historical memory access information.

The above-mentioned method of storing the first information in the record of the first serial number can be understood as a LRU method, in which the earliest stored page fault information is eliminated.

Regardless of whether multiple prefetch information corresponding to the first information is stored in the historical memory access information, after the computer device determines the first information, the historical memory access information can also be updated according to the page fault queue.

It should be noted that, in the embodiment of the present application, a page fault queue is also stored in the computer device, and the page fault queue is used to store the information of the memory pages in which the page fault exception occurs in chronological order, that is, to store the historical access memory in chronological order. Information about the memory page that triggers the page fault exception.

In the embodiment of the present application, the implementation manner of the computer device updating historical memory access information according to the page fault queue MQ includes the following steps:

(1) Store the first information in the page fault queue.

In the embodiments of the present application, there are multiple implementations for the computer device to store the first information in the page fault queue, and two implementations are described below.

In Mode 1, the computer device stores the first information (eg, address) at the end of the page fault queue. In this storage method, optionally, the computer device deletes the expired data in the page fault queue every time period, for example, deletes the memory page information whose storage time exceeds the time threshold from the current time, or keeps the page fault queue in the The specified amount of memory page information with a relatively recent storage time is deleted, and other memory page information with an earlier storage time in the page fault queue is deleted, so as to save storage space and ensure the data aging of the memory page information stored in the page fault queue. sex.

In mode 1, the newly stored first information (eg, address) is always located at the end of the page fault queue.

In mode 2, the computer device is further configured with a page fault queue length MQ_L, and the page fault queue length is used to indicate the maximum number of memory page information (eg addresses) that can be stored in the page fault queue. In this storage method, the computer device starts counting from the first time the memory page information is recorded in the MQ, and the value obtained after each count is used as the total number of page faults, that is, the computer device accumulates the number of page faults, and obtains the total number of page faults. quantity. After obtaining the first information this time and counting the total number of page faults obtained, the computer device calculates the total number of page faults divided by the length of the page fault queue to obtain a remainder, and determines the storage location of the first information in the page fault queue according to the remainder. , and store the first information in the storage location.

Exemplarily, it is assumed that the length of the page fault queue is 128, that is, the page fault queue stores information on at most 128 memory pages where page fault exceptions occur, and the storage locations of the page fault queue include 0-127 (or 1-128).

Assuming that the total number of page faults corresponding to the first address of the page fault exception obtained by the computer device is 36, and the page fault queue is not full at this time, the computer device divides 36 by 128 to obtain a remainder of 36, then the computer device according to the remainder It is determined that the storage location of the first information is 35 (or 36), and the first information is stored in the storage location in the page fault queue.

Assuming that the total number of page faults corresponding to the first information of this page fault exception obtained by the computer device is 139, and the page fault queue is full at this time, the computer device divides 139 by 128 to obtain a remainder of 11, then the computer device determines according to the remainder. The storage location of the first information is 10 (or 11), and the first information is stored in the storage location in the page fault queue, that is, the memory page information previously stored in the storage location is overwritten.

In Mode 2, the first information (eg, address) is stored in the page fault queue in a circular storage manner, and the newly stored first information is not necessarily located at the end of the page fault queue.

It can be seen from the above that in the computer device deleting the expired data in the page fault queue, or also configuring the storage mode of the page fault queue length, the data of the memory page information stored in the page fault queue can be guaranteed while saving storage space. Timeliness.

(2) Acquire information of memory pages in the page fault queue that are located before the first information and whose quantity does not exceed a second quantity threshold, and obtain one or more pieces of second information.

It should be noted that, in this embodiment of the present application, a second quantity threshold (LEVEL) is further configured in the computer device, and the second quantity threshold is used to indicate the maximum quantity of the second information obtained from the page fault queue.

It can be seen from the foregoing that there are many ways for the computer device to store the first information in the page fault queue, and correspondingly, there are many ways for the computer device to obtain the second information from the page fault queue. There are two implementation manners corresponding to manner 1 and manner 2 of storing the first information in the page queue respectively.

Assuming that the computer device stores the first information in the page fault queue according to the above method 1, that is, always stores the first information at the end of the page fault queue, then the computer device directly obtains the first information in the page fault queue. The memory page information of the second quantity threshold is obtained, that is, the one or more pieces of second information are obtained.

For example, taking the memory page information as the memory page address as an example, the memory page addresses currently stored in the page fault queue include m1, m2, m3, m4, and m5, the first address is m5, and the second quantity threshold is 3, then the computer equipment Acquire m2, m3, and m4 as the acquired 3 second addresses.

It is assumed that the computer device stores the first information in the page fault queue according to the above method 2, that is, the first information is not necessarily stored at the end of the page fault queue. In this case, if the memory before the first information in the page fault queue is The quantity of page information is not less than the second quantity threshold, and the computer device directly obtains the memory page information whose quantity does not exceed the second quantity threshold before the first information in the page fault queue, that is, obtains the one or more second information. If the number of memory page information before the first information in the page fault queue is less than the second quantity threshold, and the page fault queue is full, the computer device obtains the memory page information before the first information in the page fault queue, and obtains Part of the memory page information from the end of the queue forward, obtains one or more second information whose quantity is the second quantity threshold. That is, when the computer device stores the first information in the page fault queue by means of circular storage, the computer device also acquires the second information by means of forward circular storage.

For example, taking the memory page information as the memory page address as an example, the memory page addresses currently stored in the page fault queue include m1, m2, m3, m4, m5, m6, m7, m8, the first address is m2, and the second quantity threshold is 3, then the computer device acquires m1, m8 and m7 as the acquired 3 second addresses, so that when the page fault queue stores memory page addresses that are not less than the second number threshold in addition to the first address, One or more second addresses are guaranteed to be acquired in a quantity equal to the second quantity threshold.

(3) The first information is stored in the historical memory access information as the prefetch information corresponding to each of the one or more second information.

In the embodiment of the present application, the computer device stores the first information and each second information in the historical memory access information according to the positional relationship between the first information and the one or more second information in the page fault queue. The relationship of the second information.

Optionally, in this embodiment of the present application, each of the one or more second information corresponds to one or more related groups, and the number of the one or more related groups is a second number threshold, Each correlation group corresponds to one or more information locations, each correlation group corresponds to a correlation level, and each correlation group is used to store prefetch information. Based on this, the computer device selects one second information from the one or more second information, and performs the following operations on the selected second information until each of the one or more second information is Perform the following operations until: according to the positions of the first information and the selected second information in the page fault queue, determine the correlation level of the first information and the selected second information, obtain a reference level, and store the first information in the target at the first information position of the related group, wherein the target related group is a related group whose related level corresponding to the selected second information is a reference level.

It should be noted that the closer the locations of the two memory page information (eg addresses) stored in the page fault queue are, the higher the correlation degree (correlation degree) of the two memory page information to a certain extent. Based on this, the computer device determines the correlation level of the first information and the corresponding second information according to the position of the first information and each second information in the page fault queue, obtains the reference level, and stores the first information in the historical memory access information at the first information position in the target related group corresponding to the corresponding second information in .

Exemplarily, taking the memory page information as the memory page address and the information location as the address location as an example, it is assumed that the page fault queue includes m1, m2, m3, m4, m5, m6, m7, and m8, the first address is m4, and the second The number threshold is 3, m1, m2, and m3 are the three acquired second addresses, and each second address corresponds to three related groups. Then the computer device determines the relationship between m4 and m1 according to the positions of m1 and m4 in the page fault queue. The correlation level is 3, and m4 is stored at the first address position in the third correlation group corresponding to m1; according to the positions of m2 and m4 in the page fault queue, the correlation level between m4 and m2 is determined to be 2, and m4 It is stored in the first address position in the second correlation group corresponding to m2; according to the positions of m3 and m4 in the page fault queue, determine that the correlation level between m4 and m3 is 1, and store m4 in the first address corresponding to m1. at the first address position in the associated group.

Optionally, in order to quickly determine the position of the one or more second information in the historical memory access information, the computer device performs a hash operation on each second information, obtains the sequence number corresponding to the corresponding second information, and accesses the information from the historical memory. The corresponding serial number is searched in the information, and the corresponding second information is searched from the page fault information stored in the record of the corresponding serial number.

Because before the first information is stored as the prefetch information in the target related group in the historical memory access information, the prefetch information (that is, the memory page information is stored) may already be stored in the first information position of the target related group, Then, the computer device needs to first move and/or delete the prefetched information stored in the relevant group included in the corresponding second information, and then store the first information in the first information position of the target relevant group.

Optionally, the number of one or more information locations corresponding to each related group is a third number threshold, and the one or more related groups are arranged in order of related levels. That is, in this embodiment of the present application, the computer device is further configured with a third quantity threshold (SUCC), and the third quantity threshold is used to indicate the maximum quantity of prefetch information (such as addresses) that can be stored in each relevant group. . Based on this, the computer device stores the first information in the first information location of the target related group, including various situations:

In case 1, if the memory page information is not stored in the first information position of the target related group, the computer device stores the first information in the first information position of the target related group.

Case 2, if there is memory page information stored in the first information position of the target related group, and the number of memory page information stored in the target related group does not reach the third quantity threshold, the computer device will store each memory page in the target related group. After the memory page information is moved back by one information position, the first information is stored in the first information position of the target related group.

Case 3, if the number of memory page information stored in the target related group reaches the third quantity threshold, and the target related group is the last related group corresponding to the selected second information, then the last memory page information in the target related group is stored. Deleting, after moving the remaining memory page information in the target related group by one information position, the first information is stored in the first information position of the target related group.

Case 4, if the number of memory page information stored in the target related group reaches the third number threshold, the target related group is not the last related group corresponding to the selected second information, and the selected second information corresponds to the related group in the relevant group. If there is an idle information position in the related group after the target related group, move the target related group and each memory page information before the first free information position in the related group after the target related group by one information position. The first information is stored at the first information location of the target related group.

Case 5, if the number of memory page information stored in the target related group reaches the third number threshold, the target related group is not the last related group corresponding to the selected second information, and the selected second information corresponds to the related group in the relevant group. If there is no free information location in the related group after the target related group, the last memory page information in the last related group corresponding to the selected second information is deleted, and the target related group and the related information located after the target related group are deleted. After the rest of the memory page information in the group is moved back by one information position, the first information is stored in the first information position of the target related group.

It can be seen from the above that the computer equipment stores the first information in the first information position of the target related group in a sequential backward manner. This implementation can be understood as inserting the first information into the MRU method. in a target related group corresponding to each second information.

Optionally, a third quantity threshold is configured in the computer device, or a plurality of third quantity thresholds are configured, and each relevant group corresponds to a third quantity threshold. The quantity of prefetch information, for example, the third quantity threshold corresponding to the related group with a high degree of configuration correlation (for example, the correlation level is level 1) is larger, and the related group with a low level of configuration correlation (for example, the correlation level is level 3) corresponds to The threshold of the third quantity is smaller, which can improve the prefetching accuracy to a certain extent.

Through the above methods, the computer device obtains prefetch information from the stored historical memory access information and updates the historical memory access information after each page fault exception occurs. A prefetch algorithm to predict prefetch information (such as addresses), that is, the computer device is configured with a prefetch algorithm, the computer device continuously updates the historical memory access information by running the prefetch algorithm, and records the historical memory access information through the historical memory access information. law.

Optionally, a prefetch algorithm (which can be understood as a software module) is configured in the computer device, and the configured prefetch algorithm includes a prefetch parameter, and the prefetch parameter includes the row number threshold (ROW) and the first number threshold (ASSOC) introduced above. ), the second quantity threshold (LEVEL), the third quantity threshold (SUCC), the prefetch depth (PD) and the page fault queue length (MQ_L), wherein the first quantity threshold, the prefetch depth and the page fault queue length can be selected Configure or not configure. In the case where the first number threshold is not configured, each sequence number can store the most page fault information (such as addresses), and in the case where the prefetch depth is not configured, the first sequence number and all prefetched information in the record of the first information are stored. The information is taken as the acquired prefetch information, and the computer device stores the first information at the end of the page fault queue without configuring the length of the page fault queue.

Regarding the implementation of the computer device predicting the prefetch information from the stored historical memory access information described above, optionally, the computer device can store the historical memory access information in any way of storing data, such as storing the historical memory access information in a table form. Memory access information. Next, we will introduce the storage of historical memory access information in tabular form, and take the memory page information as the memory page address as an example, and explain the above process again. Optionally, the historical memory access information in tabular form can be called a multi-level correlation table. MLCT, the following is an example of MLCT, and the information of the memory page is the address of the memory page.

Assuming that the computer device is configured with a prefetch algorithm, the prefetch algorithm includes a prefetch parameter, and the prefetch parameter includes a row number threshold, a first number threshold, a second number threshold, a third number threshold, a prefetch depth, and a page fault queue length, The computer device updates the stored MLCT according to the page fault queue.

In this embodiment of the present application, a user may configure a prefetch algorithm through a computer device, including configuring a prefetch parameter, wherein:

ROW: R, the maximum value of the hash result of the memory page address, that is, the maximum value used to limit the serial number;

ASSOC: In the tags (T) corresponding to the same hash result, the maximum number of memory page addresses that can be recorded, that is, the maximum number of memory page addresses stored in the record of the same serial number;

LEVEL: LEV, the number of related groups corresponding to the memory page address corresponding to each tag;

SUCC: the maximum number of memory page addresses that can be stored in each relevant group;

PD: the maximum number of multiple prefetch addresses acquired each time;

MQ_L: The page fault queue length.

Exemplarily, the user enters the command line insmod smap_prefetch.ko ROW=4 ASSOC=4 LEVEL=2 SUCC=3 PD=6 MQ_L=128 in the computer device, wherein, insmod represents the loading module, and smap_prefetch.ko is the prefetching algorithm module , the processor in the computer device loads the prefetch algorithm module according to the command line, and transmits the prefetch parameter to the prefetch algorithm module.

Referring to FIG. 3 , the page fault queue (MQ) and the third quantity threshold (SUCC) will be explained. In Figure 3, MQ stores the addresses of the memory pages of each page fault exception in chronological order, including A, B, C, D, E, F, G, H, and I. Assume that the page fault occurs on the first page. One address is E, and the third quantity threshold is 3, then obtain B, C and D in MQ to get 3 second addresses, where the correlation level between E and B is 3, the correlation level between E and C is 2, and the correlation level between E and C is 2. The correlation level with D is 1, which can be understood as E is the third-level successor of B (level 3 successor, L3 SUCCE), E is the second-level successor of C (level 2 successor, L2 SUCCE), E is the first-level successor of D (level 1 successor, L1 SUCCE), then store the first address E in the third-level correlation group of B, store E in the second-level correlation group of C, and store E in the first-level correlation group of D, obtaining A multi-level correlation table storing B, C, and D and the corresponding prefetch addresses.

Referring to Figure 4, the prefetch depth (PD) is explained. The multi-level correlation table shown in Figure 4 stores the first address E and the corresponding prefetch address, and the level 1 group corresponding to E (level 1 group, L1G). ), A and C are stored in ), B and D are stored in the level 2 group (L2G), and H is stored in the third-level correlation group. Assuming that the prefetch depth is 3, then the computer device obtains A, C and B as the prefetch address.

Referring to FIG. 5, the computer device handles the page fault exception according to the following steps.

1. When a page fault exception is triggered, the virtual address va of the missing memory data is determined, and according to the virtual address va, the starting address of the memory page of the current page fault exception is determined, and the first address va _p is obtained.

Exemplarily, assuming that the size of the memory is 100k, the memory is divided into 25 consecutive memory pages according to each consecutive 4k, each memory page corresponds to a memory page address, and each memory page address is the start of the corresponding memory page. For example, if the address of the first memory page is 0000, the address of the second memory page is 0004, and the virtual address of the memory data of this page fault exception is 0011, then the quotient obtained by dividing 0011 by 4 is multiplied by 4, that is, The starting address of the memory page where this page fault exception is obtained is 0008, that is, the first address is 0008.

2. Perform a hash operation on the first address va _p to obtain the first serial number _rp .

Exemplarily, assuming that the row number threshold ROW included in the prefetch parameter is 10, the sequence number starts from 0, the maximum value of the sequence number that can be obtained by the hash operation is 9, and the first address is 0008. According to the hash operation, divide 0008 by 10 to obtain The quotient is 0, and 0 is used as the first sequence number.

3. Find the first sequence number rp from the multi-level correlation table ( _MLCT ). If the first sequence number _rp is found, the first address va _p is searched from the tags corresponding to the first sequence number rp . If the first sequence number _rp is found address va _p , the computer device obtains a plurality of corresponding prefetch addresses according to the prefetch depth PD. The column corresponding to tags is used to store the page fault address.

If the first sequence number rp is not found, the computer device adds the first sequence number rp in the _MLCT , and adds the first address _{va p} _to a tag corresponding to the first sequence number _rp ;

If the first serial number rp is found, but va _p is not found, the computer device stores the first address _va _p in a tag corresponding to the first serial number _rp in an LRU manner.

Wherein, the LRU method is used to store the first address va _p in the first sequence number as follows: if the number of memory page addresses recorded in the tags corresponding to the first sequence number r _p reaches the first number threshold (ASSOC), then the computer equipment After deleting the memory page address with the earliest storage time in the tags, the first address va _p is added to the tags; if the number of memory page addresses recorded in the tags corresponding to the first serial number r _p does not reach the first number threshold, Then the computer device directly adds the first address va _p to tags.

4. If multiple prefetch addresses are obtained, the corresponding data is read into the memory from the specified storage space.

5. Store the first address va _p in the page fault queue MQ as _mp in the MQ (configured with the page fault queue length and stored in a circular manner).

6. According to the second quantity threshold (LEVEL, understood as several levels of successors), obtain the memory page addresses m _i that are not more than LEVEL before the first address va _p in the MQ, assuming levels=3, and there is a storage time in the MQ If there are more than or equal to three memory page addresses before the first address va _p , the three memory page addresses located before the first address va _p in the MQ are acquired, which are m1, m2, and m3 in chronological order.

7. Perform a hash operation on each _mi to obtain the corresponding serial number ri, find the position of _ri corresponding to each _mi from the _MLCT , and according to the position of each _mi and _mp in the MQ, The corresponding correlation group (correlation level) is found, and _{mp (ie, the first address va p} ₎ is stored in the corresponding correlation group (target correlation group) by means of MRU.

Wherein, storing the first address va _page in the relevant group in an MRU manner may be understood as a manner of moving backward in sequence, and the specific implementation method refers to the foregoing embodiments, which will not be repeated here.

FIG. 6 is an exemplary MLCT shown in an embodiment of the present application. In FIG. 6, the column where ROW(R) is located is used to store the serial number, and the column where ASSOC is located is used to store the serial number of each TAG(T). The column is optional, the column where TAG is located stores the page fault address corresponding to each serial number, the column where L1 is located is used to store the prefetch address of the first-level successor corresponding to the page fault address (VA), and the column where L2 is located is used to store The prefetch address (PVA) of the secondary successor corresponding to the page fault address.

Through the above process, multiple prefetch addresses corresponding to the memory page of the current page fault exception are obtained, and the multi-level correlation table is updated. Since the multi-level correlation table is gradually established according to the sequence relationship between the memory pages with page fault exceptions that occur during historical access to memory, the multiple prefetch addresses obtained from the multi-level correlation table are highly likely to be the first in historical access. After the memory data corresponding to an address, the memory page address corresponding to the memory data that needs to be accessed continuously, that is, the data corresponding to the multiple prefetch addresses read by this solution is very likely to be the memory to be accessed by the processor next. data, that is, this solution pre-reads memory data more accurately, which can avoid serious waste of memory resources, and can reduce the probability of page fault exceptions again, that is, improve the prefetch hit rate and effectively reduce the memory access delay. .

It should be noted that there are many memory access modes applied in computer equipment, such as sequential memory access mode and non-sequential memory access mode. The non-sequential memory access mode includes strided mode and mixed mode. This solution The MLCT is established by learning the rules of historical memory access through the prefetch algorithm, instead of blindly prefetching the data corresponding to the consecutive memory page addresses into the memory. This scheme has good effects on sequential memory access mode, skip read mode and mixed mode. .

Optionally, in addition to predicting the prefetch information by storing historical memory access information (such as MLCT) described above, in some other embodiments, the computer device predicts the prefetch information corresponding to the first information based on a Markov model. . For example, a computer device constructs a Markov model based on historical memory access information, which includes historically accessed memory page information (such as addresses) arranged in chronological order, or memory page information of abnormal page faults arranged in chronological order, The computer device calculates the measurement probability of the memory page information and the transition probability between the memory page information according to the Markov model, and then calculates the probability that the first information is transferred to other memory page information according to the measurement probability and the transition probability, and calculates the maximum probability obtained by the calculation. The corresponding memory page information is used as a prefetch information. Optionally, after predicting to obtain a piece of prefetch information, the computer device continues to use the prefetch information as the first information, and continues to predict the next most probable prefetch information by using the Markov model, to obtain the second prefetch information, And so on, until a plurality of prefetch information with the number of the prefetch depth is obtained.

Optionally, in other embodiments, the computer device predicts the prefetch information corresponding to the first information by using a deep learning model, such as predicting the prefetch information by using an artificial intelligence (artificial intelligence, AI) model. Among them, the historical memory access information includes historically accessed memory page information (such as addresses) arranged in chronological order, and the deep learning model is trained according to the historical memory access information. Use the information of multiple memory pages with the number of prefetch depths that continue to be accessed after accessing the memory page as the expected output of the sample, and obtain a training sample. In this way, multiple training samples are obtained. Each training sample includes a sample input and a The sample expected output, the computer equipment inputs the training sample into the initial model, and the deep learning model is obtained by training. After obtaining the memory page information of the page fault exception this time, that is, after obtaining the first information, the computer device inputs the first information into the deep learning model, and outputs a plurality of prefetch information. Optionally, the computer device obtains training samples online, and gradually trains and updates the deep learning model by means of online training, or after the computer device obtains a certain amount of training samples, the deep learning model is obtained by training by means of offline training.

Step 203: Read the data corresponding to the plurality of prefetch information to the corresponding memory page in the memory.

In this embodiment of the present application, after predicting and obtaining multiple pieces of prefetch information (eg, addresses), the computer device reads data corresponding to the multiple pieces of prefetch information to a corresponding memory page in the memory.

It should be noted that, taking the prefetch information as the prefetch address as an example, the prefetch address is a virtual address, and some of the data corresponding to the multiple prefetch addresses may already be on the corresponding memory page in the memory. The mapping relationship between the virtual address and the physical address of the memory is used to determine whether the data corresponding to the multiple prefetch addresses are already on the corresponding memory page, and the data not on the memory page is read to the corresponding memory page.

In the embodiment of the present application, the computer device reads the corresponding data from the designated storage space to the corresponding memory page in the memory according to the plurality of prefetch information.

It should be noted that a designated storage space is set in the computer device for storing the data of the cold page, that is, storing the data not stored in the memory page of the memory. Among them, the read and write speed of XL-FLASH devices is faster than that of SWAP partitions of disks, and the price is lower than that of memory sticks (such as DRAM), and the capacity is large, which can provide several times more capacity than memory. For computer equipment, it can be accessed The memory space includes DRAM and XL-FLASH devices, that is, by adding XL-FLASH devices, the accessible memory space is increased several times, that is, the access memory space visible to the user is increased a lot.

Optionally, the designated memory space includes the storage space of one or more of the SWAP partition, the XL-FLASH device and the remote storage.

Optionally, the computer device determines the cold pages in the memory according to the access time and the number of accesses of the memory pages in the memory in the first time period, and moves the data on the cold pages from the memory to the designated storage space. That is, in addition to prefetching memory data from the specified storage space through the prefetch algorithm, the processor can also combine the method of scanning and eliminating cold pages in the memory to move the data on the cold pages in the memory to the specified storage space. , that is, eliminating cold pages in memory. In this way, more memory space can be freed up for storing hot memory data, thereby improving memory resource utilization.

In the embodiment of the present application, the computer device obtains the access time and the access quantity of the memory pages in the memory in the first time period, and determines the cold page in the memory according to the access time and the access quantity of the memory pages in the memory during the period of time .

Exemplarily, the number of accesses of each memory page in the memory corresponds to the weight w1, and the average of the durations between the respective access times of each memory page in the memory and the current time during this period is the first duration, and the first duration corresponds to the weight w2. , the processor calculates the product of the number of accesses of each memory page in the memory and the weight w1 plus the product of the first duration and the weight w2 to obtain the memory access statistics value corresponding to the corresponding memory page, and the processor calculates the corresponding memory access statistics in the memory A memory page whose value is less than the statistical threshold is determined as a cold page, or the processor sorts the access statistics corresponding to each memory page in the memory from small to large, and determines the memory page corresponding to the specified proportion of access statistics at the lower end of the sorting as a cold page .

Optionally, the computer device periodically scans and eliminates cold pages, the first period of time is a period of time before the current scan, and the duration of the first period of time may be greater than, equal to or less than the scan period.

It should be noted that there are many strategies for scanning to determine cold pages. Each strategy aims to determine the memory pages with fewer accesses and earlier access times as cold pages. The strategy described above is only an example. .

Optionally, when the computer device eliminates cold pages, it compresses the data on the cold pages in the memory and stores it in the specified storage space. When pre-reading the memory data, it decompresses the prefetched memory data from the specified storage space and reads the in memory. In this way, through data compression, the amount of data storage in the specified storage space can be saved, and more cold pages can be eliminated from the memory to the specified storage space. In this way, more hot memory data can be stored in the memory, further improving the Resource utilization of memory.

Referring to FIG. 7, the computer device combines the prefetch algorithm and the memory page scan to prefetch the memory data and eliminate the memory data, wherein the computer device scans the cold pages in the memory through the page scan module, and compresses the data of the cold pages and stores them in the memory. In the designated storage space, the computer equipment prefetches the memory data from the designated storage space through the prefetching algorithm, in which the corresponding data is decompressed from the designated storage space through the kernel compression module and then read into the memory (such as DRAM), which is equivalent to reading heat. page data.

Optionally, the computer device can also receive a prefetch algorithm performance query instruction, and display prefetch algorithm performance information, where the prefetch algorithm performance information includes a prefetch accuracy rate and a prefetch coverage rate. Among them, the prefetch accuracy rate is determined by the total number of prefetches and the number of prefetch hits, the prefetch coverage rate is determined by the total number of prefetches and the total number of accesses, and the total number of prefetches refers to all the prefetch information obtained in the second time period. The total number of prefetch hits refers to the total number of memory pages accessed in the memory pages corresponding to all prefetch information obtained in the second time period, and the total number of accesses refers to all the memory accessed in the second time period. The total number of pages.

Optionally, the second time period refers to a period of time from when the computer device runs the prefetch algorithm to when it receives the prefetch algorithm performance query instruction, or the second time period is before the moment when the prefetch algorithm performance information query is received. A period of time of the specified duration.

Exemplarily, the user obtains the performance information of the prefetch algorithm, including the prefetch accuracy, Prefetch coverage, total number of prefetches, number of prefetch hits, etc. If the prefetching accuracy rate is low, the user can adjust the prefetching parameters by entering a command line in the computer device, such as increasing LEVEL, increasing ASSOC or increasing SUCC, etc. The computer device updates the historical memory according to the adjusted prefetching parameters Access information (such as MLCT) to record the association relationship of more historically accessed memory page information in the historical memory access information.

That is, after displaying the prefetch algorithm performance information, the computer device receives the prefetch parameter adjustment instruction, the prefetch parameter adjustment instruction is determined by user feedback on the prefetch algorithm performance information, the computer device adjusts the instruction according to the prefetch parameter, and updates the history. Memory access information.

In this embodiment of the present application, a user can query prefetch algorithm performance information through a computer device, and the computer device displays the prefetch algorithm performance information after receiving the prefetch algorithm performance query instruction, such as the prefetch accuracy rate and the prefetch coverage rate, Optionally, the total number of prefetches, the number of prefetch hits, etc. can also be displayed, and the user can choose to adjust the prefetch parameters through the computer device according to the prefetch accuracy rate and the prefetch coverage rate. Taking the historical memory access information as MLCT as an example, under normal circumstances, the larger the corresponding multi-level correlation table after the user adjusts the prefetch parameters, the more the correlation relationship of the historically accessed memory page information that the multi-level correlation table can record. To a certain extent, the performance of the prefetching algorithm is better.

Next, the method for processing the memory page fault exception provided by the embodiment of the present application is exemplarily described by using the software and hardware modules in the computer device.

Referring to Figure 8, the computer equipment includes a processor (CPU), a memory and a designated storage space (taking XL-FLASH as an example), and this method is understood to be realized through an abstract three-layer model of SMAP, which includes a perception layer, a decision layer and a physical layer. , SMAP can be understood to include functions corresponding to all the methods provided in the embodiments of the present application. Among them, the computer device counts the hot and cold pages in the memory (main memory) through the processor and, for example, through the application (application, APP), the operating system (operaing system, OS) or the virtual machine (such as Hyper-v) statistics of memory cold and hot pages Pages, that is, memory hot and cold through the perception layer at the software level. A computer device prefetches or eliminates memory pages by running a prefetching algorithm and a memory elimination algorithm, etc. on the processor, that is, prefetching or eliminating memory pages through a decision layer at the software and hardware levels. The computer device performs media compression and decompression through the memory hardware module, that is, the media compression at the physical layer improves the access rate and saves storage space.

Referring to FIG. 9 , taking the user plane and the kernel plane of the operating system in the computer device as examples, the processing method for the memory page fault exception provided by the embodiment of the present application is exemplarily described. In Figure 9, the user configures the prefetch algorithm and other related algorithms (such as the memory elimination algorithm for scanning cold pages) through the command line and other forms. In the kernel space of the operating system, the algorithm is run to realize the data prefetch of the memory page. And the elimination of cold pages in memory.

To sum up, in the embodiment of the present application, since the historical memory access information can represent the law of historical memory access, the prefetch information is predicted according to the historical memory access information, so that the data corresponding to the prefetch information is read into the memory It is not blindly prefetching the data of multiple consecutive memory page addresses into the memory, that is, the prefetching hit rate of this scheme is higher, which can effectively reduce the number of subsequent page fault exceptions, effectively reduce the memory access delay, and this The data prefetched by the scheme is more effective, the consumption of memory resources is lower, and the memory resources are not very tight.

FIG. 10 is a schematic structural diagram of an apparatus 1000 for processing a memory page fault exception provided by an embodiment of the present application. The apparatus 1000 for processing a memory page fault exception may be implemented as part or all of a computer device by software, hardware, or a combination of the two. , the computer device may be the computer device shown in FIG. 1 . Referring to FIG. 10 , the apparatus 1000 includes: a first determination module 1001 , a prediction module 1002 and a reading module 1003 .

The first determination module 1001 is used to determine the information of the target memory page, and obtain the first information, and the target memory page is the memory page where the page fault exception occurs this time; for the specific implementation method, refer to the detailed introduction of step 201 in the foregoing embodiment of FIG. 2 , I won't go into details here.

The prediction module 1002 is used to predict a plurality of prefetch information corresponding to the first information according to the historical memory access information, and the historical memory access information is used to represent the law of historical memory access; for the specific implementation method, refer to step 202 in the aforementioned embodiment of FIG. 2 The detailed introduction will not be repeated here.

The reading module 1003 is configured to read the data corresponding to the plurality of prefetch information to the corresponding memory page in the memory. For a specific implementation manner, refer to the detailed introduction of step 203 in the foregoing embodiment of FIG. 2 , which will not be repeated here.

Prediction module 1002 includes:

The acquisition unit includes:

Optionally, lookup subunits are specifically used to:

Optionally, the device also includes:

Optionally, the first update module includes:

The first update unit is used to create a record where the first serial number and the first information are located in the historical memory access information in the case that the historical memory access information does not store the first serial number and the first information, to update the historical memory access information;

Optionally, the second update unit includes:

Optionally, the device also includes:

Optionally, the second update module includes:

a first storage unit for storing the first information in the page fault queue;

Optionally, the second storage unit includes:

The third storage subunit is specifically used for:

The first information is stored in the first information position of the target related group, and the target related group is a related group whose correlation level corresponding to the selected second information is a reference level.

The third storage subunit is specifically used for:

Optionally, the reading module 1003 includes:

Optionally, referring to FIG. 11 , the apparatus 1000 further includes:

The second determination module 1004 is configured to determine the cold page in the memory according to the access time and the number of accesses of the memory pages in the memory in the first time period; for the specific implementation method, refer to the detailed introduction of step 203 in the foregoing embodiment of FIG. 2 , here No longer.

The moving module 1005 is configured to move the data on the cold page from the memory to the designated storage space.

Optionally, referring to FIG. 12 , the apparatus 1000 further includes:

a first receiving module 1006, configured to receive a prefetch algorithm performance query instruction;

A display module 1007, configured to display prefetch algorithm performance information, where the prefetch algorithm performance information includes a prefetch accuracy rate and a prefetch coverage rate;

Optionally, referring to FIG. 13 , the apparatus 1000 further includes:

The second receiving module 1008 is configured to receive a prefetch parameter adjustment instruction, where the prefetch parameter adjustment instruction is determined by user feedback on the performance information of the prefetch algorithm;

The third update module 1009 is configured to adjust the instruction according to the prefetch parameter and update the historical memory access information.

It should be noted that: when the device for processing a memory page fault exception provided by the above-mentioned embodiment, when processing the memory page fault abnormality, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions may be allocated as required. It is completed by different functional modules, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the apparatus for processing a memory page fault exception provided by the above embodiment and the embodiment of the processing method for a memory page fault exception belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented in software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general purpose computer, special purpose computer, computer network or other programmable device. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server, a data center, etc. that includes one or more available media integrated. The available media may be magnetic media (eg: floppy disk, hard disk, magnetic tape), optical media (eg: digital versatile disc (DVD)) or semiconductor media (eg: solid state disk (SSD)) Wait. It should be noted that the computer-readable storage medium mentioned in the embodiments of the present application may be a non-volatile storage medium, in other words, may be a non-transitory storage medium.

It should be understood that references herein to "at least one" refers to one or more, and "plurality" refers to two or more. In the description of the embodiments of the present application, unless otherwise specified, "/" means or means, for example, A/B can mean A or B; "and/or" in this document is only an association that describes an associated object Relation, it means that there can be three kinds of relations, for example, A and/or B can mean that A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with basically the same function and effect. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like are not necessarily different.

The above-mentioned examples provided for this application are not intended to limit this application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the protection scope of this application. Inside.

Claims

A method for processing a memory page fault exception, characterized in that the method comprises:

Determine the information of the target memory page, and obtain the first information, and the target memory page is the memory page where the page fault exception occurs this time;

predicting a plurality of prefetch information corresponding to the first information according to the historical memory access information, where the historical memory access information is used to represent the law of historical memory access;

The data corresponding to the plurality of prefetch information is read into the corresponding memory page in the memory.
The method according to claim 1, wherein the historical memory access information is determined according to the sequence relationship between memory pages in which a page fault exception occurs during historical memory access.
The method according to claim 1 or 2, wherein the predicting a plurality of prefetch information corresponding to the first information according to historical memory access information comprises:

A plurality of prefetch information corresponding to the first information is acquired according to the association relationship between the information of the memory page where the page fault exception occurs in the historical memory access information and the prefetch information.
The method according to claim 3, wherein the historical memory access information includes a sequence number, a corresponding relationship between page fault information and prefetch information, and the page fault information refers to the memory page in which the page fault exception occurs. information, and the serial number is obtained by performing a hash operation on the page fault information.
The method of claim 4, wherein the method further comprises:

If multiple pieces of prefetch information corresponding to the first information are not obtained, the historical memory access information is updated according to a first sequence number and the first information, where the first sequence number is a reference to the first information obtained by hashing.
The method according to claim 5, wherein the updating the historical memory access information according to the first sequence number and the first information comprises:

In the case where the historical memory access information does not store the first serial number and the first information, a record containing the first serial number and the first information is created in the historical memory access information to update the historical memory access information;

In the case where the first serial number is stored in the historical memory access information, but the first information is not stored, the first information is stored in the record of the first serial number to update the historical memory access information.
The method of claim 6, wherein the storing the first information in the record of the first serial number comprises:

If the quantity of page fault information stored in the record of the first serial number does not reach the first quantity threshold, storing the first information in the record of the first serial number;

If the number of page fault information stored in the record of the first serial number reaches the first quantity threshold, delete the page fault information with the earliest storage time and the corresponding prefetch information in the record of the first serial number, and then delete the page fault information and the corresponding prefetch information in the record of the first serial number. The first information is stored in the record of the first serial number.
The method according to any one of claims 1-7, wherein the method further comprises:

According to the page fault queue, the historical memory access information is updated, and the page fault queue is used to store the information of the memory pages in which the page fault exception occurs in chronological order.
The method of claim 8, wherein the updating the historical memory access information according to the page fault queue comprises:

storing the first information in the page fault queue;

Acquiring memory page information in the page fault queue that is located before the first information and whose quantity does not exceed a second quantity threshold, and obtains one or more second information;

The first information is stored in the historical memory access information as prefetch information corresponding to each of the one or more second information.
The method of claim 9, wherein the first information is stored in the historical memory access as prefetch information corresponding to each second information in the one or more second information information, including:

According to the positional relationship between the first information and each of the one or more second information in the page fault queue, storing the first information and each second information in the historical memory access information The relationship of the second information.
The method according to any one of claims 1-10, wherein the reading data corresponding to the plurality of prefetch information to a corresponding memory page in the memory comprises:

According to the plurality of prefetch information, the corresponding data is read from the specified storage space to the corresponding memory page in the memory.
The method according to claim 11, wherein the designated storage space is the storage space of the SWAP partition divided on the disk included in the device, or the storage space of the XL-FLASH memory included in the device, or the remote storage of storage space.
The method of claim 11 or 12, wherein the method further comprises:

Determine the cold page in the memory according to the access time and the access quantity of the memory page in the memory in the first time period;

moving data on the cold pages from the memory to the designated storage space.
The method according to any one of claims 1-13, wherein the method further comprises:

Receive a prefetch algorithm performance query instruction;

Displaying prefetch algorithm performance information, where the prefetch algorithm performance information includes prefetch accuracy and prefetch coverage;

The prefetch accuracy rate is determined by the total number of prefetches and the number of prefetch hits, the prefetch coverage rate is determined by the total number of prefetches and the total number of accesses, and the total number of prefetches refers to the second time period. The total number of acquired prefetch information, the number of prefetch hits refers to the total number of accessed memory pages in the memory pages corresponding to all prefetch information acquired within the second time period, and the total number of accesses Refers to the total number of all memory pages accessed within the second time period.
The method according to claim 14, wherein after the displaying the performance information of the prefetching algorithm, the method further comprises:

receiving a prefetch parameter adjustment instruction, the prefetch parameter adjustment instruction being determined by user feedback about the performance information of the prefetch algorithm;

The historical memory access information is updated according to the prefetch parameter adjustment instruction.
A device for processing a memory page fault exception, characterized in that the device comprises:

a first determining module, configured to determine the information of the target memory page, and obtain the first information, where the target memory page is the memory page where the page fault exception occurs this time;

a prediction module, configured to predict a plurality of prefetch information corresponding to the first information according to historical memory access information, where the historical memory access information is used to characterize the law of historical memory access;

The reading module is configured to read the data corresponding to the plurality of prefetch information to the corresponding memory page in the memory.
The apparatus of claim 16, wherein the historical memory access information is determined according to the sequence relationship between memory pages in which a page fault exception occurs during historical memory access.
The apparatus of claim 16 or 17, wherein the prediction module comprises:

An obtaining unit, configured to obtain a plurality of prefetch information corresponding to the first information according to the association relationship between the information of the memory page where the page fault exception occurs in the historical memory access information and the prefetch information.
The apparatus according to claim 18, wherein the historical memory access information includes a sequence number, a correspondence between page fault information and prefetch information, and the page fault information refers to the memory page in which the page fault exception occurs. information, and the serial number is obtained by performing a hash operation on the page fault information.
The apparatus of claim 19, wherein the apparatus further comprises:

A first update module, configured to update the historical memory access information according to the first sequence number and the first information if multiple prefetch information corresponding to the first information is not obtained, the first sequence number is obtained by performing a hash operation on the first information.
The apparatus of claim 20, wherein the first update module comprises:

a first update unit, configured to create the first serial number and the first serial number in the historical memory access information when the historical memory access information does not store the first serial number and the first information the record where the information is located to update the historical memory access information;

a second updating unit, configured to store the first information in the record of the first serial number when the historical memory access information stores the first serial number but does not store the first information, to update the historical memory access information.
The apparatus of claim 21, wherein the second update unit comprises:

a first storage subunit, configured to store the first information in the record of the first serial number if the quantity of page fault information stored in the record of the first serial number does not reach the first quantity threshold;

The second storage subunit is configured to delete the page fault information with the earliest storage time in the record of the first serial number if the quantity of the page fault information stored in the record of the first serial number reaches the first quantity threshold and the For the corresponding prefetch information, the first information is stored in the record of the first sequence number.
The device according to any one of claims 16-22, wherein the device further comprises:

The second update module is configured to update the historical memory access information according to the page fault queue, and the page fault queue is used to store the information of the memory pages in which the page fault exception occurs in chronological order.
The apparatus of claim 23, wherein the second update module comprises:

a first storage unit, configured to store the first information in the page fault queue;

an acquisition unit, configured to acquire memory page information that is located before the first information and whose quantity does not exceed a second quantity threshold in the page fault queue, and obtains one or more second information;

A second storage unit, configured to store the first information in the historical memory access information as prefetch information corresponding to each of the one or more second information.
The apparatus of claim 24, wherein the second storage unit comprises:

a third storage subunit, configured to store in the historical memory access information according to the positional relationship between the first information and each of the one or more second information in the page fault queue The association relationship between the first information and each second information.
The device according to any one of claims 16-25, wherein the reading module comprises:

The reading unit is configured to read the corresponding data from the specified storage space to the corresponding memory page in the memory according to the plurality of prefetch information.
The apparatus according to claim 26, wherein the designated storage space is the storage space of the SWAP partition divided on the disk included in the device, or the storage space of the XL-FLASH memory included in the device, or the remote storage of storage space.
The apparatus of claim 26 or 27, wherein the apparatus further comprises:

a second determining module, configured to determine the cold page in the memory according to the access time and the number of accesses of the memory pages in the memory in the first time period;

A moving module, configured to move the data on the cold page from the memory to the designated storage space.
The device according to any one of claims 16-28, wherein the device further comprises:

a first receiving module, configured to receive a prefetch algorithm performance query instruction;

a display module, configured to display prefetch algorithm performance information, where the prefetch algorithm performance information includes a prefetch accuracy rate and a prefetch coverage rate;

The prefetch accuracy rate is determined by the total number of prefetches and the number of prefetch hits, the prefetch coverage rate is determined by the total number of prefetches and the total number of accesses, and the total number of prefetches refers to the second time period. The total number of all acquired prefetch information, the number of prefetch hits refers to the total number of accessed memory pages in the memory pages corresponding to all prefetch information acquired within the second time period, and the total number of accesses Refers to the total number of all memory pages accessed within the second time period.
The apparatus of claim 29, wherein the apparatus further comprises:

a second receiving module, configured to receive a prefetch parameter adjustment instruction, where the prefetch parameter adjustment instruction is determined by user feedback on the performance information of the prefetch algorithm;

A third update module, configured to update the historical memory access information according to the prefetch parameter adjustment instruction.
A computer device, characterized in that the computer device includes a processor and a memory;

The memory is used to store the computer program involved in the method of any one of claims 1-15;

The processor is configured to execute the computer program to implement the method of any one of claims 1-15.
A computer-readable storage medium, characterized in that, a computer program is stored in the storage medium, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1-15 are implemented.