WO2022000371A1 - Interface generation method and device, and computer-readable storage medium - Google Patents

Abstract

An interface generation method and device, and a computer-readable storage medium. The method comprises: acquiring a target assembly instruction (101); determining, according to class indication information of the target assembly instruction, a preconfigured universal instruction interface matching the class indication information, and acquiring a target universal instruction interface, different class indication information corresponding to different preconfigured universal instruction interfaces (102); and generating, according to content of the target assembly instruction and the target universal instruction interface, a dedicated instruction interface for describing the target assembly instruction (103). By means of the method, a user does not need to manually program and define an interface, and a dedicated instruction interface of a target assembly instruction is automatically generated. As a result, costs are reduced, and efficiency is improved.

Description

Interface generation method, apparatus, and computer-readable storage medium technical field

The present invention belongs to the technical field of instructions, and in particular, relates to an interface generation method, an apparatus and a computer-readable storage medium.

Background technique

At present, the application of chips is more and more extensive. When driving a chip, assembly instructions are often used for driving. With the increasing number of assembly instructions supported by the chip, how to improve the efficiency of chip driving based on assembly instructions has become a widely concerned issue.

In the prior art, the interface defining the assembly instruction is usually written manually according to the content of each assembly instruction. In this way, when the assembly instruction is used for driving, the chip can be quickly driven by directly calling the assembly instruction interface. However, this manual writing method has high cost and low efficiency.

SUMMARY OF THE INVENTION

The present invention provides an interface generation method, device and computer-readable storage medium, so as to solve the problems of manual interface writing, high cost and low efficiency.

In order to solve the above-mentioned technical problems, the present invention is achieved in this way:

In a first aspect, an embodiment of the present invention provides an interface generation method, which includes:

Get the target assembly instructions;

According to the category indication information of the target assembly instruction, determine a preset general instruction interface that matches the category indication information, and obtain a target general instruction interface; wherein, different types of instruction information correspond to different preset general instruction interfaces;

According to the content of the target assembly instruction and the target general instruction interface, a dedicated instruction interface for describing the target assembly instruction is generated.

In a second aspect, an embodiment of the present invention provides an interface generation apparatus, the apparatus includes: a memory and a processor,

the memory for storing program codes;

The processor calls the program code, and when the program code is executed, is configured to perform the following operations:

Get the target assembly instructions;

According to the category indication information of the target assembly instruction, determine a preset general instruction interface that matches the category indication information, and obtain a target general instruction interface; wherein, different types of instruction information correspond to different preset general instruction interfaces;

According to the content of the target assembly instruction and the target general instruction interface, a dedicated instruction interface for describing the target assembly instruction is generated.

In a third aspect, an embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the foregoing interface generation method is implemented.

In the embodiment of the present application, a target assembly instruction may be obtained, and according to the category indication information of the target assembly instruction, a preset general instruction interface matching the category indication information may be determined to obtain the target general instruction interface; wherein, different types of indication information correspond to different The preset general instruction interface of the target assembly instruction generates a special instruction interface for describing the target assembly instruction according to the content of the target assembly instruction and the target general instruction interface. In the embodiment of the present application, the user does not need to manually write the definition interface, and the dedicated instruction interface of the target assembly instruction can be automatically generated. Therefore, to a certain extent, the cost can be reduced and the efficiency can be improved.

Description of drawings

1 is a flow chart of steps of a method for generating an interface provided by an embodiment of the present application;

2 is an abstract schematic diagram of a preset general command interface provided by an embodiment of the present application;

3 is a schematic diagram of an interface for generating a general command provided by an embodiment of the present application;

4 is an abstract schematic diagram of a dedicated instruction interface provided by an embodiment of the present application;

5 is a schematic diagram of an interface structure provided by an embodiment of the present application;

6 is a schematic design diagram of a generation tool provided by an embodiment of the present application;

7 is a block diagram of an interface generation apparatus provided by an embodiment of the present application;

FIG. 8 is a block diagram of a computing processing device provided by an embodiment of the present application;

FIG. 9 is a block diagram of a portable or fixed storage unit according to an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

In order to facilitate the understanding of the present application, an application scenario involved in the embodiments of the present application is first described below. In this application scenario, the chip can be a chip accelerator. Specifically, in order to improve the computing processing efficiency of the chip, more and more chip accelerators appear in the chip design. For example, in the fields of machine learning and artificial intelligence, chip accelerators are used to support efficient image processing and data operations. Among them, a chip accelerator is a special chip, which is usually a dedicated hardware circuit that can be used to implement various functions, so as to obtain higher performance or better energy efficiency than general-purpose microprocessors when performing a set of operations Compare.

When the driving chip is working, it can be divided into register driving and instruction driving according to the driving mode. In the register-driven mode, the operation of the accelerator is controlled through the configuration register. In the instruction-driven mode, the drive needs to be implemented through the assembly instructions supported by the accelerator, that is, to implement accelerator scheduling. The accelerator may include an accelerator module, and various types of accelerator modules can be dispatched through assembly instructions supported by the accelerator, so as to control the accelerator to execute operations corresponding to the assembly instructions.

Further, when the accelerator is scheduled through the assembly instruction, the assembly instruction can be embedded in the native code of the accelerator through mixed programming, so that the operation logic indicated by the assembly instruction is associated with the processing logic of the native code, thereby realizing the scheduling of the assembly instruction in the native code. , which drives the accelerator to perform the corresponding operation. Alternatively, the file in the native code of the accelerator is jointly compiled with the assembler file corresponding to the assembly instruction, so as to realize the scheduling of the assembly instruction in the native code, thereby realizing the scheduling of the accelerator. By way of example, assuming that the accelerator is developed in a C programming environment, and it is desired to schedule the character type (char) addition operation of the accelerator, a mixed programming method of C language programming and assembly programming can usually be adopted. For example, in a C language software development system, such as keil C, embedding can be implemented in the following ways:

#pragma ASM

;Assembler code

e#pragma ENDASM

In another C language software development system, such as ARM C, the inline assembly keyword "__asm" can be used to embed assembly in C:

__asm{;Assembler code}

Because the workload of embedding or joint compilation by direct writing is often large, the efficiency is low. Therefore, in order to improve the scheduling efficiency, the interface of the assembly instruction is often defined. When the assembler instruction needs to be used for accelerator scheduling, the interface of the assembler instruction can be directly called, and the assembler instruction can be used for scheduling by running the interface.

In one implementation of generating the interface, the interface that defines the assembly instructions is manually written. However, the number of assembly instructions is often large, which will consume higher labor costs and lower efficiency. In view of this, the embodiments of the present application provide an interface generation method for automatically generating an interface, so as to reduce costs and improve efficiency.

The interface generation method is described in detail below.

FIG. 1 is a flowchart of steps of an interface generation method provided by an embodiment of the present application. As shown in FIG. 1 , the method may include:

Step 101 , obtaining target assembly instructions.

In this embodiment of the present application, the target assembly instruction may be an assembly instruction that needs to generate an interface. There can be one or more target assembly instructions. When acquiring the target assembly instruction, the target assembly instruction may be actively read from a preset position, or the target assembly instruction input by the user may be received, which is not limited in this embodiment of the present application.

Step 102: According to the category indication information of the target assembly instruction, determine a preset general instruction interface that matches the category indication information, and obtain a target general instruction interface; wherein, different types of instruction information correspond to different preset general instruction interfaces .

In this embodiment of the present application, the category indication information may be used to indicate the category to which the assembly instruction belongs. Assembly instructions with the same class designation belong to the same class. Assembly instructions of the same class can have the same content. The preset general instruction interface corresponding to the category indication information of this category can be used to represent the same content that this category of assembly instructions has in common.

Correspondingly, the determined target general instruction interface that matches the category indication information of the target assembly instruction can be used to characterize the same content shared by other similar assembly instructions in the target assembly instruction, that is, at least can be used to characterize the same content of the target assembly instruction. Part of the target assembly instruction.

Step 103: Generate a dedicated instruction interface for describing the target assembly instruction according to the content of the target assembly instruction and the target general instruction interface.

In this embodiment of the present application, the dedicated instruction interface can represent the content of the target assembly instruction and its assembly embedded code, so that the chip can be driven to execute the operation indicated by the target assembly instruction by subsequently calling the dedicated instruction interface. Since the target general instruction interface can be used to represent part of the content in the target assembly instruction, that is, part of the content in the target assembly instruction has been pre-interfaced. Therefore, by combining the content of the target assembly instruction and the target general instruction interface to generate a dedicated instruction interface, the generation efficiency can be improved to a certain extent. And because a general instruction interface can describe the same content that a class of assembly instructions has in common, when a dedicated instruction interface is generated for multiple assembly instructions, the general instruction interface can be reused, thereby improving the generation of dedicated instruction interfaces for multiple assembly instructions. time efficiency.

To sum up, in the interface generation method provided by the embodiments of the present application, the target general instruction interface is obtained by obtaining the target assembly instruction, and according to the category indication information of the target assembly instruction, determining a preset general instruction interface that matches the category indication information; Wherein, different types of indication information correspond to different preset general instruction interfaces, and according to the content of the target assembly instruction and the target general instruction interface, a dedicated instruction interface for describing the target assembly instruction is generated. In the embodiment of the present application, the user does not need to manually write the definition interface, and the dedicated instruction interface of the target assembly instruction can be automatically generated. Therefore, to a certain extent, the cost can be reduced and the efficiency can be improved.

Optionally, in an implementation manner of the embodiment of the present application, the category indication information may include the number of operands included in the target assembly instruction and the chip identifier of the chip to which it belongs. Among them, the operands can be divided into source operands and destination operands. The chip to which it belongs may be a chip that supports the target assembly instruction. The chip identification can be an identification that can uniquely represent the chip. Since the number of operands between assembly instructions and the chip identification of the chip to which they belong is often the same, the number of operands and the chip identification of the chip to which they belong are used as the category instruction information to improve the accuracy of assembly instructions to a certain extent. Classification effect.

The identifiers can be numbers, characters, special symbols, and so on. Correspondingly, the above-mentioned preset general command interface can be implemented through the following sub-steps (1) to (3):

Sub-step (1): configure m ports for the assembly instructions of each preset category supported by the preset chip; the assembly instructions of the same preset category contain the same number of operands, and the m is not less than the preset category The number of operands contained in the assembly instruction.

In this embodiment of the present application, the preset chip may be one or more chips specified in advance. Preset categories may be pre-divided according to operands of assembly instructions. Optionally, in this embodiment of the present application, before this step, the following operations may be used to achieve the division of preset categories: Step A: Divide the assembly instructions that include the same operand in the assembly instructions supported by the preset chip into the same category to get the preset category. Specifically, the number of operands included in each assembly instruction supported by the preset chip may be determined first. Then, the assembly instructions with the same number of operands are divided into one category. For example, assume that the default chip is an accelerator. Then, the instructions in the accelerator instruction pool, that is, the assembly instructions supported by the accelerator, can be classified according to operands. It is assumed that among the supported assembly instructions, there is an assembly instruction including one operand, an assembly instruction including two operands, ..., an assembly instruction including N operands. Then, N preset categories can be obtained by division: single-operand category, double-operand category, ..., N-operand category.

Further, operands can be input or output through ports. Ports can be recorded in registers. As an example, take an assembly instruction: vmadd[0].char,[1].char,[2].char as an example, the assembly instruction is used to implement the accelerator's processing of adding a char type vector. Among them, vmadd represents the mnemonic of the assembly instruction, and [1].char and [2].char represent the source operand of type char, that is, the addend of vector addition. The source operands come from the input ports recorded in internal register 1 and internal register 2 respectively, and the type of vector data is char. [0].char represents the destination operand of type char, that is, the result of vector addition. The destination operand can be output to the output port recorded in internal register 0.

Due to the number of operands included in the assembly instructions in the same preset category, port configuration can be performed in units of categories. Taking the category as a unit, configure the port for each category, and the assembly instructions in one category share the port, which can improve the port utilization to a certain extent, thereby saving port resources.

During configuration, x ports can be configured for the preset category, where x represents the number of operations corresponding to the preset category. In this way, the problem of occupying too many ports and leading to waste of resources can be avoided. For example, a single-operand class can be configured with a single port, a double-operand class can be configured with a dual port, ..., an N-operand class can be configured with N ports. Alternatively, configure the number of ports greater than x, so as to avoid the problem that the ports are occupied and other assembly instructions in the category cannot be executed to a certain extent.

Sub-step (2): configure an assembly instruction conversion interface; the assembly instruction conversion interface is used to generate an assembly embedded code according to the assembly instruction; the assembly embedded code is used to embed the assembly instruction into the native chip of the preset chip. in the code.

In this embodiment of the present application, the assembly instruction conversion interface may be used to provide a method for mapping assembly embedded codes according to assembly instructions. The assembly instruction conversion interface may be implemented by macros, that is, the assembly instruction conversion interface may be a macro-type interface.

When configuring the assembly instruction conversion interface, you can first define internal parameters inside the interface: the general code segment of the assembly embedded code. Wherein, the general code segment may be manually set, or obtained by analyzing the same part in multiple assembler embedded codes. Then define the processing method, input and output of the interface. Wherein, the processing method may be a combination of internal parameters and input, the input may be an assembly instruction, and the output may be an assembly embedded code. It should be noted that, since assembly instructions are often character strings, the input may be a character string representing an assembly instruction.

Optionally, the assembly instruction conversion interface may be an inline assembly interface. Where inline assembly represents a way of inserting assembly language in C language. The inline assembly interface can be used to generate assembly embedded code that can embed assembly instructions into native code developed based on C language in an inline assembly manner.

In an application scenario, the chip is often developed based on the C language. When using inline assembly in the C language, no additional compiler and linker are required, and the variables in the C language can be used. Therefore, this application implements the In the example, by configuring the inline assembly interface, it can be ensured that the generated general instruction interface has the ability to generate the assembly instructions to be embedded in the native code of the chip in the form of inline assembly, thereby improving the convenience of running the code to a certain extent.

Sub-step (3): Generate the preset general instruction interface according to the port information of the m ports, the assembly instruction conversion interface and the chip identifier of the preset chip.

In this embodiment of the present application, the port information of the port may be the port identifier. Further, when generating the preset general instruction interface, the port information, the assembly instruction conversion interface and the chip identification of the chip to which the assembly instruction belongs can be combined and spliced according to the preset interface format according to the preset format, so as to realize the modeling of the general instruction interface. to get the preset general command interface. It should be noted that, the preset general command interface may also be constructed by manual coding according to the logic of generating the preset general command interface shown in the embodiment of the present application, which is not limited in the embodiment of the present application.

As an example, take the preset chip as an accelerator module as an example. Fig. 2 is an abstract schematic diagram of a preset general command interface provided by an embodiment of the present application. Among them, "module" is used to represent the chip identification, the number of v is used to represent the number of operands, and "instr_asm" is used to represent the assembly instruction conversion interface. opnd is used to represent port information. Certainly, other forms may also be used to represent, which is not limited in this embodiment of the present application.

For single-operand instructions in the single-operand category, the generated preset general instruction interface can be expressed as "module_v(instr_asm,opnd)", and for the two-operand instructions in the two-operand category, the preset general instruction interface can be expressed as is "module_vv(instr_asm,opnd1,opnd2)", for N-operand instructions in the N-operand category, the generated preset general instruction interface can be expressed as "module_v...v(instr_asm,opnd1,opnd2,...,opndN)" . The interface format of these general instruction interfaces may be expressed as "module_v..v", and the input parameters may be assembly instructions and corresponding specific vector ports.

Further, FIG. 3 is a schematic diagram of an interface for generating a general command provided by an embodiment of the present application. In the embodiment of the present application, the operation of "instruction operand classification" can be realized through the above-mentioned step A, the operation of "instruction parameter configuration interface support" can be realized through the above-mentioned sub-step (1), and the "instruction-in-instruction" operation can be realized through the above-mentioned sub-step (2). The operation of "connection interface support" is implemented, and the operation of "model splicing" is realized through the above sub-step (3).

In the embodiment of the present application, a general instruction interface is established for each category by classifying the operand instructions. In this way, all the assembly instructions supported by the chip can be described and modeled uniformly through a small number of interfaces, and the convenience of the follow-up is simple and fast. The generation-specific instruction interface. For example, assuming that the chip supports single-operand instructions, two-operand instructions, and three-operand instructions, only three general instruction interfaces need to be provided: "module_v, module_vv, module_vvv".

Optionally, according to the category indication information of the target assembly instruction, determine a preset general instruction interface that matches the category indication information, and obtain the operation of the target general instruction interface, which can be performed through the following sub-steps (4) to (6) accomplish:

Sub-step (4): For any one of the preset general command interfaces, obtain the number of chip identifiers and port information defined in the preset general command interface, as the comparison chip identifiers and the number of comparisons.

In the embodiment of the present application, the preset general command interface can be parsed, and then the chip identification can be extracted therefrom, and the port information can be extracted to determine the quantity of the port information, and then the comparison chip identification and the comparison quantity can be obtained. For example, assuming that the defined chip identifier is "module" and the number is 3, then the comparison chip identifier of the preset general command interface may be "module", and the comparison number may be 3.

Sub-step (5): Compare the comparison quantity and the comparison chip identifier with the number of operands included in the target assembly instruction and the chip identifier of the chip to which the target assembly instruction belongs, respectively.

In this embodiment of the present application, the number of operands included in the target assembly instruction and the chip identifier of the chip to which the target assembly instruction belongs may be determined first. For example, the operands contained in the target assembly instruction can be extracted, and then the number of the extracted operands can be counted. According to the preset correspondence between the chip identifier and the assembly instruction, the chip identifier corresponding to the target assembly instruction is searched for.

Then, the number of comparisons is compared with the number of operands contained in the target assembly instruction to determine whether the two are the same. And, the comparison chip identification is compared with the chip identification of the chip to which the target assembly instruction belongs to determine whether the two are the same.

Sub-step (6): if the comparison quantity is the same as the number of operands included in the target assembly instruction, and the comparison chip identification is the same as the chip identification of the belonging chip, then the preset general instruction interface is used. Identify the generic instruction interface for the target.

In the embodiment of the present application, if the quantity and the chip identifier are the same, it can be considered that the target assembly instruction belongs to the category corresponding to the preset general instruction interface, and then the preset general instruction interface can be determined as the target general instruction interface. In this application, by comparing the number of operands contained in the target assembly instruction and the chip identifier of the chip to which it belongs, respectively with the number of chip identifiers and port information defined in each preset general-purpose instruction interface, the target general-purpose instruction can be more accurately determined. instruction.

Optionally, according to the content of the target assembly instruction and the target general instruction interface, the step of generating a dedicated instruction interface for describing the target assembly instruction can be implemented through the following sub-steps (7) to (8):

Sub-step (7): According to the content of the target assembly instruction and the target general instruction interface, generate an interface name, an interface parameter list and an assembly embedded code of the dedicated instruction interface.

Among them, the interface name can be used to represent a dedicated instruction interface for easy invocation. The interface parameter list can be used to represent the parameters that will be used when the dedicated command interface is processed. The assembly embedded code of the dedicated instruction interface can be used to embed the target assembly instruction into the native code of the corresponding chip.

Optionally, the following sub-steps (7a) to (7b) can be used to generate the interface name, interface parameter list and assembly embedded code of the dedicated instruction interface:

Sub-step (7a): Generate an interface name of the dedicated instruction interface according to the mnemonic, operand type and flag register information in the target assembly instruction.

In this embodiment of the present application, the mnemonic may be an English word or its abbreviation indicating the function of the instruction. The operand type may be the data type of each operand involved in the target assembly instruction. The flag register, also known as the program status word, can be used to store condition flags and control flag registers to reflect the result of instruction execution. The flag register information may be information capable of identifying the flag register, such as the number, symbol, name, and the like of the flag register. It should be noted that, when the flag register information is not included in the assembly instruction, the interface name can be generated only according to the mnemonic, that is, the operand type. Optionally, when generating the interface name of the dedicated instruction interface, the abbreviated characters corresponding to each of the operand types can be obtained; the abbreviated characters can be combined into an abbreviated string; , the abbreviated character string and the flag register information are combined to obtain the interface name. Among them, the abbreviated characters corresponding to each operand type in the target assembly instruction can be searched according to the preset correspondence between the operand types and the abbreviated characters, and then these corresponding abbreviations are sorted according to the order in which the operand types appear in the assembly instruction. The characters are combined into an abbreviated string. For example, in an implementation manner, the corresponding relationship between the preset type and the abbreviated characters may be as follows:

operand type	abbreviated characters
bit	b
char	c
uchar	uc
short	s
ushort	us
int	i
uint	ui
float	f
half float	hf

Suppose the target assembly instruction is "vacmps[0].char,[1].int,[2].int ge", where the operand types are: char, int, int, and the corresponding operand types can be obtained by searching The abbreviated characters are: c, i, i. Combining these abbreviated characters can get the abbreviated string: "cii".

Further, according to the preset separator, when combining the mnemonic, the abbreviated string and the flag register information, the separator can be used to connect the mnemonic, the abbreviated string and the flag register information in sequence, and then the interface is obtained. name. The specific content of the separator may be preset according to actual requirements, and the connection sequence during connection may also be other sequences, which are not limited in this embodiment of the present application.

For example, the delimiter is the underscore "_", the target assembly instruction is "vacmps[0].char,[1].int,[2].int ge", its mnemonic is "vacmps", the operation The abbreviation string corresponding to the number type is "cii", and the flag register information is "ge", then the interface name can be obtained: "vacmps_cii_ge".

Since the mnemonic, operand type and flag register information of different assembly instructions may be different, after these information are combined, an assembly instruction can be specifically characterized to a certain extent. Therefore, according to the combination of these information, the present application can ensure that the interface name can more accurately represent the target assembly instruction by generating the interface name.

Sub-step (7b): calling the target general-purpose instruction interface to generate an interface parameter list of the special-purpose instruction interface according to the operand port information and/or immediate data in the target assembly instruction, and converting the target Assembly instructions are converted into assembly embedded code.

In this embodiment of the present application, an immediate number is equivalent to a constant, which is a number that can directly appear in an assembly instruction without being stored in a register or memory. Specifically, different assembly instructions have different functions. Therefore, some assembly instructions will include one of operands and immediate values, or both. Correspondingly, in the embodiment of the present application, when two kinds of target assembly instructions are included, the interface parameter list may be generated according to both, and if only one is included, the interface parameter list may be generated according to the included one.

When generating an interface parameter list, the included immediate data and operand port information corresponding to each operand can be added to the list. The information of each operand port may be information of a port configured for the operand in advance, and the target general instruction interface may be called to obtain the information of each operand port. For example, also taking the assembly instruction "vacmps[0].char,[1].int,[2].int ge" as an example, its interface parameter list can be expressed as "int dstPort,int src0Port,int src1Port" , int dstPort, int src0Port, int src1Port represent the destination operand, respectively, the corresponding operand port information of source operand 1 and source operand 2. In the embodiment of the present application, the target general instruction interface may be called, the target assembly instruction may be used as the input of the target general instruction interface, and then the output may be used as the assembly embedded code corresponding to the target assembly instruction. Optionally, an inline assembly interface may be defined in the target general instruction interface. Correspondingly, the target assembly instruction can be converted into inline assembly code based on the inline assembly interface defined in the target general instruction interface to obtain the assembly embedded code. For example, the target assembly instruction can be used as the input of the inline assembly interface, and the assembly embedded code can be obtained by combining the general code segment defined in the inline assembly interface with the target assembly instruction. The assembly embedded code generated by the inline assembly interface can embed assembly instructions into the native code developed based on the C language in the form of inline assembly, thereby improving the convenience of code operation to a certain extent.

Optionally, the target general-purpose instruction interface may be invoked in a macro calling manner or an interface function calling manner. Among them, the interface function calling method allocates a temporary memory unit for processing when the code is running. The interface function method can be an intrinsic function. The macro calling method, also known as macro expansion, is performed when the code is compiled, and does not need to allocate memory units. Since the macro call method is expanded in the compilation stage, in the embodiment of the present application, the target general instruction interface is called by the macro call method, which can save the code running time to a certain extent. Further, when the target general instruction interface is called by using the interface function calling method, expansion in the compilation phase can be avoided, thereby ensuring the efficiency of the compilation phase.

Sub-step (8): Generate the dedicated instruction interface according to the interface name, the interface parameter list and the assembler embedded code.

Optionally, in this embodiment of the present application, the interface name, the interface parameter list, and the assembly embedded code may be spliced together to obtain the dedicated instruction interface. For example, internal splicing can be performed in the general command interface. It should be noted that, since the dedicated instruction interface is used to drive the chip to execute the target assembly instruction, the return value of the dedicated instruction interface, that is, the type of the output parameter, can be set to void in advance. FIG. 4 is an abstract schematic diagram of a special-purpose instruction interface provided by an embodiment of the present application, and FIG. 4 is used to represent parts with common characteristics in the special-purpose instruction interfaces belonging to the same category of instructions. where "instruction" is used to represent the instruction name, for example, the instruction's mnemonic. The number of x represents the number of abbreviated strings, and opnd is used to represent port information. For the single-operand instructions in the single-operand category, the dedicated instruction interface can be abstracted as "instruction_x(opnd)", and for the two-operand instructions in the two-operand category, the dedicated instruction interface can be abstracted as "instruction_xx(opnd1, opnd2) ", for N-operand instructions in the N-operand category, the dedicated general-purpose instruction interface can be abstracted as "instruction_x...x(opnd1,opnd2,...,opndN)". The interface format of these general instruction interfaces may be expressed as "module_v..v", and the input parameters may be assembly instructions and corresponding specific vector ports.

Optionally, when the embodiment of the present application acquires the target assembly instruction, a mixed instruction pool may be generated according to the assembly instructions supported by each preset chip; the assembly instruction included in the mixed instruction pool is used as the target assembly instruction, and the The target assembly instruction is obtained from the mixed instruction pool. The preset chip may be one or more chips specified by the user according to actual requirements. The assembly instructions supported by these chips can be stored in the same file, resulting in a mixed instruction pool. Of course, it is also possible to store only the assembly instructions that need to generate an interface among the assembly instructions supported by these chips, so as to avoid performing unnecessary interface generation operations. Next, the mixed instruction pool can be traversed, and one assembly instruction is fetched each time as a target assembly instruction. In the scenario of generating interfaces for assembly instructions supported by multiple chips, by first mixing the assembly instructions supported by multiple chips, and then traversing and acquiring target assembly instructions for processing, to a certain extent, the multiple-to-many assembly instructions can be more evenly obtained. The assembly instruction generation interface supported by each chip avoids generating the interface only for the assembly instruction supported by one of the chips, resulting in that the assembly instructions supported by the other chips cannot be processed in time.

Optionally, after acquiring the target assembly instruction, you can also: acquire preset parallel generation configuration information; if the parallel generation configuration information is a specified value, encapsulate a preset waiting instruction for the dedicated instruction interface; It is assumed that the waiting instruction is used to indicate that when the dedicated instruction interface is called, after the execution of the dedicated instruction interface is completed, other called dedicated instruction interfaces are executed.

In this embodiment of the present application, the parallel generation configuration information may be used to indicate whether a preset waiting command needs to be packaged for the dedicated command interface at present. The configuration information generated in parallel may be set according to actual requirements, and it may be the value of a preset flag bit. Correspondingly, the parallel generation configuration information can be obtained by reading the value of the preset flag bit.

Further, if the configuration information generated in parallel is a specified value, it can be considered that a preset waiting command needs to be packaged for the dedicated command interface at present. Therefore, it is possible to further encapsulate a preset waiting command for the dedicated command interface. Specifically, the preset waiting instruction can be encapsulated inside the interface, and when the dedicated instruction interface is called by encapsulating the preset waiting instruction, it will wait for the completion of the dedicated instruction interface inside the interface, and then execute other commands. The dedicated instruction interface of the call, that is, implements the blocking mode or the serial mode, thereby avoiding the parallel execution of the interface, causing the problem of interface conflict. On the contrary, if the preset waiting instruction is not encapsulated, then when the dedicated instruction interface is called, it will not wait for the dedicated instruction interface to complete within the interface, that is, the non-blocking mode or the parallel mode is implemented. The specified value can be set according to the actual situation, and the specified value can be a number, a character, a character string, and so on. By way of example, the specified value may be "wait". Correspondingly, a second specified value can also be set, and in the case that the configuration information generated in parallel is the second specified value, the operation of encapsulating the preset waiting instruction for the dedicated instruction interface can be not performed, that is, only the generation does not include the preset waiting instruction. Dedicated instruction switching for instructions. For example, the second specified value may be "nowait". Further, a third specified value can also be set, and in the case that the configuration information generated in parallel is the third specified value, according to the dedicated instruction interface, a dedicated instruction interface encapsulated with a preset waiting instruction can be generated at the same time, and a preset waiting instruction is not encapsulated. Dedicated command interface for waiting commands. Illustratively, the third specified value may be "all".

Specifically, the corresponding situations of these several specified value configurations can be as follows:

wait: Generates a dedicated command interface encapsulated with a preset waiting command, and the generated dedicated command interface internally waits for the command to complete. Where interfaces are called consecutively, they execute serially, not in parallel.

nowait: Generates a dedicated command interface that is not encapsulated with preset waiting commands. The generated dedicated command interface does not wait for the command to complete. When the interface is called continuously, they will be executed in parallel.

all: Generates two sets of interfaces of the dedicated command interface encapsulated with the preset waiting command and the dedicated command interface not encapsulated with the preset waiting command. Subsequent use can be freely switched by the user.

After generating the dedicated command interface, you can also generate interface annotations by executing the following steps A to B:

Step A: Acquire designation information according to the dedicated command interface; the designation information at least includes port information in the dedicated command interface and types of output parameters.

In this embodiment of the present application, the specified information may be information set according to actual requirements, and may also include other information in addition to the port information and the type of output parameters, which is not limited in this embodiment of the present application. For example, each port information can be extracted from the dedicated command interface, and the preset output parameter type can be obtained.

Step B: Combine the specified information according to a preset annotation generation tool to obtain an interface annotation of the dedicated command interface.

In this embodiment of the present application, the annotation generating tool may be a pre-selected tool for generating annotations, for example, a doxygen tool, and correspondingly, the specified information may be information that complies with the rule requirements of the doxygen tool. The annotation generation tool can automatically parse the specified types of information, and arrange and combine them according to preset rules. Correspondingly, the specified information can be output to an annotation generation tool, and the specified information can be combined by the annotation generation tool to obtain interface annotations, and these interface annotations form an annotation document. In the present application, the interface annotation of the special instruction interface is automatically generated according to the annotation generation tool, so that the special instruction interface to be called can be conveniently selected according to the interface annotation in the future, thereby improving the efficiency of interface calling.

Taking the target assembly instruction as ""vacmps[0].char,[1].int,[2].intge" as an example, the specific implementation of the built-in dedicated instruction interface can be expressed as:

Lines starting with "///" indicate interface comments, and the content after "#" indicates dedicated instruction interfaces. Among them, VALU_vvv("vacmps[0].char,[1].int,[2].int ge",dstPort,src0Port,src1Port) represents the calling target general instruction interface. "vacmps[0].char,[1].int,[2].int ge" in the target general instruction interface is used to convert the target assembly instruction into assembly embedded code, VALU indicates the chip identification, "dstPort,src0Port, src1Port" indicates port information. The interface prototype of this assembly instruction in the specific model can be expressed as: void vacmps_cii_ge(int dstPort,int src0Port,int src1Port);

In this example, for the target assembly instruction containing three operands, by calling the general instruction interface corresponding to the three operands, the underlying assembly scheduling and configuration can be completed, and the specific interface of the abstract encapsulation target assembly instruction can be realized, that is, Dedicated command interface.

Optionally, after generating the dedicated command interface, the following steps C to D may also be performed:

Step C. For any of the preset chips, define a dedicated command interface corresponding to the preset chip at the designated position of the native code of the preset chip, and obtain an interface model of the preset chip; It is assumed that the dedicated instruction interface corresponding to the chip is generated according to the target assembly instruction belonging to the preset chip.

In this embodiment of the present application, the specified location may be preset. For example, the specified location may be a header file (include.). Specifically, the dedicated command interface corresponding to the preset chip can be written into a specified location, so as to realize the construction of the interface model of the preset chip, and obtain the interface models corresponding to different preset chips. That is, according to the preset chips, the interface model of each preset chip is obtained.

Step D, when receiving an instruction calling request, obtain a dedicated instruction interface matching the instruction calling request from the interface model of the target preset chip; the chip identifier of the target preset chip is in the instruction calling request. The included chip ID matches.

In this embodiment of the present application, the instruction invocation request may be sent when a dedicated instruction interface needs to be invoked. If an instruction call request is received, it can be considered that there is a dedicated instruction interface that needs to be called. The instruction invocation request may contain a chip identifier to indicate which chip the instruction invocation request is used to invoke the dedicated instruction interface of the assembly instruction supported by the chip. Correspondingly, a dedicated instruction interface matching the instruction invocation request can be obtained from the interface model in which the chip identification matches the chip identification contained in the instruction invocation request. The instruction invocation request may also include the name of the dedicated instruction interface, and the dedicated instruction interface with the same name included in the instruction invocation request in the interface model may be determined as the dedicated instruction interface matching the instruction invocation request. In the present application, the interface model of each preset chip is constructed according to the preset chip classification, so that when the dedicated command interface is called later, the corresponding interface model can be conveniently searched and called, and the calling efficiency can be improved to a certain extent.

Optionally, after generating the dedicated instruction interface, you may further: obtain a preset output path; and output the dedicated instruction interface according to the preset output path. In this embodiment of the present application, the preset output path may be preset. When the dedicated command interface is output, the dedicated command interface can be output to the preset position according to the preset output path. In the embodiment of the present application, the preset output path is used to output the dedicated command interface according to the preset output path, so that the dedicated command interface can be directly outputted to the preset position, thereby facilitating storage. By way of example, FIG. 5 is a schematic structural diagram of an interface provided by an embodiment of the present application. The bottom-level assembly instruction may be a target assembly instruction, and the bottom-level assembly configuration may represent a related configuration, for example, configured port information. The general programming model in the first layer may be a target general instruction interface and the specific programming model in the second layer may be a dedicated instruction interface. For example, assuming the underlying assembly instruction is "vmadd[0].char,[1].char,[2].char", the underlying assembly configuration can be expressed as "outVEU_INST0_MAP0,r0", and the general programming model can be expressed as "VEU_vvv( "vmadd[0].char,[1].char,[2].char",dstPort,src0Port,src1Port)", the specific programming model can be expressed as "Vmadd_ccc(dstPort,src0Port,src1Port)".

It should be noted that, in this embodiment of the present application, an automated generation tool may also be constructed according to the above processing logic for generating a dedicated instruction interface. When the automatic generation tool is running, the above steps can be implemented. Among them, the automatic generation tool can support command line parameter control. By way of example, the following is part of the command line:

Through the above command line, it is possible to specify a preset chip from the chips whose chip identifiers are veu, valu, and vfpu, and the control tool filters out other chips, and only processes the assembly instructions supported by the specified preset chip. Set parallel generation configuration information, annotation simplification, switch configuration between interface function call mode and macro call mode, and set intrinsic call implementation of internal interface. Custom output path. When the assembly instructions contained in the instruction pool change, the constructed general instruction interface can still be applied to the instruction pool. Therefore, in the embodiment of the present application, by constructing the general instruction interface, a special instruction interface is generated on the basis of the constructed general instruction interface. , to a certain extent, it can improve the adaptability of the dedicated instruction interface and provide more possibilities for interface generation. At the same time, through the built automatic generation tool, the special instruction interface of the assembly instruction can be quickly and conveniently generated and updated, which can better meet the development needs. By way of example, FIG. 6 is a schematic design diagram of a generation tool provided by an embodiment of the present application. Taking the preset chips as X accelerators as an example, as shown in FIG. 6 , the generation tool can generate a mixed instruction pool according to the instruction pools corresponding to the X accelerators. That is, according to the assembly instructions supported by each preset chip, a mixed instruction pool is generated. Then, the target assembly instruction is obtained from the mixed instruction pool, and a dedicated instruction interface is generated through subsequent operations. Interface annotations and interface models for each accelerator can also be generated later.

FIG. 7 is a block diagram of an interface generation apparatus provided by an embodiment of the present application. As shown in FIG. 7 , the apparatus may include: a memory 201 and a processor 202 .

The memory 201 is used to store program codes. The processor 202 calls the program code, and when the program code is executed, is configured to perform the following operations: obtain a target assembly instruction; The matching preset general-purpose instruction interface obtains the target general-purpose instruction interface; wherein, different types of indication information correspond to different preset general-purpose instruction interfaces; according to the content of the target assembly instruction and the target general-purpose instruction interface, generate a description for A dedicated instruction interface for the target assembly instruction. Optionally, the category indication information includes the number of operands included in the target assembly instruction and the chip identifier of the chip to which it belongs. Optionally, the processor 202 is further configured to: configure m ports for the assembly instructions of each preset category supported by the preset chip; the assembly instructions of the same preset category contain the same number of operands, the m is not less than the number of operands contained in the assembly instructions of the preset category; configure an assembly instruction conversion interface; the assembly instruction conversion interface is used to generate an assembly embedded code according to the assembly instruction; the assembly embedded code is used to convert The assembly instruction is embedded in the native code of the preset chip;

The preset general instruction interface is generated according to the port information of the m ports, the assembly instruction conversion interface, and the chip identifier of the preset chip. Optionally, the assembly instruction conversion interface is an inline assembly interface. Optionally, the processor 202 is further configured to: classify the assembly instructions that include the same operand among the assembly instructions supported by the preset chip into the same category to obtain the preset category. Optionally, the processor 202 is specifically configured to: generate an interface name, an interface parameter list, and an assembly embedded code of the dedicated instruction interface according to the content of the target assembly instruction and the target general instruction interface; The interface name, the interface parameter list and the assembler embedded code are used to generate the dedicated instruction interface. Optionally, the processor 202 is specifically configured to: generate the interface name of the dedicated instruction interface according to the mnemonic, operand type and flag register information in the target assembly instruction; call the target general instruction an interface to generate an interface parameter list of the dedicated instruction interface according to the operand port information and/or immediate data in the target assembly instruction, and convert the target assembly instruction into an assembly embedded code. Optionally, the processor 202 is specifically configured to: obtain the abbreviated characters corresponding to each of the operand types; combine the abbreviated characters into an abbreviated character string; , the abbreviated character string and the flag register information are combined to obtain the interface name. Optionally, the processor 202 is specifically configured to: call the target general instruction interface in a macro calling manner or an interface function calling manner. Optionally, an inline assembly interface is defined in the target general instruction interface; the processor 202 is specifically configured to: convert the target assembly instruction based on the inline assembly interface defined in the target general instruction interface for inline assembly code. Optionally, the processor 202 is specifically configured to: for any of the preset general-purpose command interfaces, obtain the number of chip identifiers and port information defined in the preset general-purpose command interface, as the comparison chip identifiers and comparisons. Quantity; compare the comparison quantity and the comparison chip identifier with the number of operands included in the target assembly instruction and the chip identifier of the chip to which the target assembly instruction contains; if the comparison quantity and the target assembly instruction include The number of operands is the same, and the comparison chip identification is the same as the chip identification of the belonging chip, then the preset general command interface is determined as the target general command interface. Optionally, the processor 202 is specifically configured to: generate a mixed instruction pool according to the assembly instructions supported by each preset chip; The target assembly instruction is obtained from the instruction pool. Optionally, the processor 202 is further configured to: for any of the preset chips, define a dedicated instruction interface corresponding to the preset chip at a designated position of the native code of the preset chip, and obtain the preset chip. The interface model of the preset chip; the dedicated instruction interface corresponding to the preset chip is generated according to the target assembly instruction belonging to the preset chip; when receiving an instruction call request, the interface model of the target preset chip is obtained. A dedicated instruction interface matching the instruction invocation request is obtained; the chip identification of the target preset chip matches the chip identification contained in the instruction invocation request. Optionally, the processor 202 is further configured to: acquire specified information according to the dedicated instruction interface; the specified information at least includes port information and the type of output parameters in the dedicated instruction interface; The annotation generation tool combines the specified information to obtain the interface annotation of the dedicated instruction interface. Optionally, the processor 202 is further configured to: obtain preset parallel generation configuration information; if the parallel generation configuration information is a specified value, encapsulate a preset waiting instruction for the dedicated instruction interface; It is assumed that the waiting instruction is used to indicate that when the dedicated instruction interface is called, after the execution of the dedicated instruction interface is completed, other called dedicated instruction interfaces are executed.

Optionally, the processor 202 is further configured to: acquire a preset output path; and output the dedicated instruction interface according to the preset output path. The operations performed by the above-mentioned apparatus are similar to the corresponding steps in the above-mentioned method, and can achieve the same technical effect. To avoid repetition, details are not repeated here. Further, the embodiments of the present application also provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, each step in the above-mentioned interface generation method is implemented, and can To achieve the same technical effect, in order to avoid repetition, details are not repeated here.

The device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed over multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort. Various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor may be used in practice to implement some or all of the functions of some or all of the components in the computing processing device according to the embodiments of the present application. The present application can also be implemented as an apparatus or apparatus program (eg, computer programs and computer program products) for performing part or all of the methods described herein. Such a program implementing the present application may be stored on a computer-readable medium, or may be in the form of one or more signals. Such signals may be downloaded from Internet sites, or provided on carrier signals, or in any other form. For example, FIG. 8 is a block diagram of a computing processing device provided by an embodiment of the present application. As shown in FIG. 8 , FIG. 8 shows a computing processing device that can implement the method according to the present application. The computing processing device traditionally includes a processor 310 and a computer program product or computer readable medium in the form of a memory 320 . The memory 320 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), EPROM, hard disk, or ROM. The memory 320 has storage space 330 for program code for performing any of the method steps in the above-described methods. For example, the storage space 330 for program codes may include various program codes for implementing various steps in the above methods, respectively. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards or floppy disks. Such computer program products are typically portable or fixed storage units as described with reference to FIG. 9 . The storage unit may have storage segments, storage spaces, etc. arranged similarly to the memory 320 in the computing processing device of FIG. 8 . The program code may, for example, be compressed in a suitable form. Typically, the storage unit includes computer readable code, ie code readable by a processor such as 310 for example, which when executed by a computing processing device, causes the computing processing device to perform each of the methods described above. step.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments may be referred to each other. Reference herein to "one embodiment," "an embodiment," or "one or more embodiments" means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the present application. Also, please note that instances of the phrase "in one embodiment" herein are not necessarily all referring to the same embodiment. In the description provided herein, numerous specific details are set forth. It will be understood, however, that the embodiments of the present application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. do not denote any order. These words can be interpreted as names. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be The technical solutions described in the foregoing embodiments are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions in the embodiments of the present application.

Claims (33)

1. An interface generation method, characterized in that the method comprises:

   Get the target assembly instructions;

   According to the category indication information of the target assembly instruction, determine a preset general instruction interface that matches the category indication information, and obtain a target general instruction interface; wherein, different types of instruction information correspond to different preset general instruction interfaces;

   According to the content of the target assembly instruction and the target general instruction interface, a dedicated instruction interface for describing the target assembly instruction is generated.
2. The method according to claim 1, wherein the category indication information includes the number of operands included in the target assembly instruction and the chip identifier of the chip to which it belongs.
3. The method according to claim 2, wherein the preset general command interface is generated by the following steps:

   Configure m ports for the assembly instructions of each preset category supported by the preset chip; the assembly instructions of the same preset category contain the same number of operands, and the m is not less than the operations contained in the assembly instructions of the preset category number;

   configuring an assembly instruction conversion interface; the assembly instruction conversion interface is used to generate an assembly embedded code according to the assembly instruction; the assembly embedded code is used to embed the assembly instruction into the native code of the preset chip;

   The preset general instruction interface is generated according to the port information of the m ports, the assembly instruction conversion interface, and the chip identifier of the preset chip.
4. The method according to claim 3, wherein the assembly instruction conversion interface is an inline assembly interface.
5. The method according to claim 3, wherein before configuring m ports for the assembly instructions of each preset category supported by the preset chip, the method further comprises:

   Divide the assembly instructions that include the same operand among the assembly instructions supported by the preset chip into the same category to obtain the preset category.
6. The method according to any one of claims 1 to 5, wherein the generating a dedicated instruction interface for describing the target assembly instruction according to the content of the target assembly instruction and the target general instruction interface, comprising:

   According to the content of the target assembly instruction and the target general instruction interface, generate the interface name, the interface parameter list and the assembly embedded code of the special instruction interface;

   The dedicated instruction interface is generated according to the interface name, the interface parameter list and the assembly embedded code.
7. The method according to claim 6, wherein generating the interface name, interface parameter list and assembler embedded code of the dedicated instruction interface according to the content of the target assembly instruction and the target general instruction interface, comprising:

   generating the interface name of the dedicated instruction interface according to the mnemonic, operand type and flag register information in the target assembly instruction;

   Invoke the target general-purpose instruction interface to generate an interface parameter list of the special-purpose instruction interface according to the operand port information and/or immediate data in the target assembly instruction, and convert the target assembly instruction into an assembly embedded code .
8. The method according to claim 6 or 7, wherein generating the interface name of the dedicated instruction interface according to the mnemonic, operand type and flag register information in the target assembly instruction, comprising:

   Obtain the abbreviated characters corresponding to each of the operand types;

   combining the abbreviated characters into an abbreviated string;

   The interface name is obtained by combining the mnemonic, the abbreviated character string and the flag register information according to a preset separator.
9. The method according to claim 7, wherein the invoking the target general instruction interface comprises:

   The target general instruction interface is called through a macro calling method or an interface function calling method.
10. The method according to claim 7, wherein an inline assembly interface is defined in the target general instruction interface;

    The converting the target assembly instruction into the assembly embedded code includes:

    The target assembly instruction is converted into inline assembly code based on the inline assembly interface defined in the target general instruction interface.
11. The method according to any one of claims 2 to 5, wherein, according to the category indication information of the target assembly instruction, determining a preset general instruction interface that matches the category indication information to obtain the target general instruction interface ,include:

    For any one of the preset general-purpose command interfaces, obtain the number of chip identifiers and port information defined in the preset general-purpose command interface, as the comparison chip identifiers and the number of comparisons;

    Comparing the number of comparisons and the identification of the comparison chip with the number of operands included in the target assembly instruction and the identification of the chip of the chip to which it belongs;

    If the number of comparisons is the same as the number of operands included in the target assembly instruction, and the comparison chip identifier is the same as the chip identifier of the chip to which it belongs, the preset general-purpose instruction interface is determined as the target general-purpose instruction interface. Command interface.
12. The method according to claim 1, wherein the obtaining the target assembly instruction comprises:

    Generate a mixed instruction pool according to the assembly instructions supported by each preset chip;

    The assembly instructions contained in the mixed instruction pool are used as target assembly instructions, and the target assembly instructions are acquired from the mixed instruction pool.
13. The method according to claim 12, wherein after generating a dedicated instruction interface for describing the target assembly instruction according to the content of the target assembly instruction and the target general instruction interface, the method further comprises: :

    For any of the preset chips, a dedicated command interface corresponding to the preset chip is defined at the designated position of the native code of the preset chip, and an interface model of the preset chip is obtained; the preset chip corresponds to The dedicated instruction interface is generated according to the target assembly instruction belonging to the preset chip;

    When receiving an instruction invocation request, obtain a dedicated instruction interface matching the instruction invocation request from the interface model of the target preset chip; the chip identifier of the target preset chip and the chip included in the instruction invocation request ID matches.
14. The method according to claim 1, wherein after generating a dedicated instruction interface for describing the target assembly instruction according to the content of the target assembly instruction and the target general instruction interface, the method further comprises: :

    Acquire specified information according to the dedicated command interface; the specified information at least includes port information and the type of output parameters in the dedicated command interface;

    According to a preset annotation generation tool, the specified information is combined to obtain the interface annotation of the dedicated instruction interface.
15. The method according to claim 1, wherein the method further comprises:

    Obtain the preset parallel generation configuration information;

    If the parallel generation configuration information is a specified value, encapsulating a preset waiting command for the dedicated command interface;

    The preset waiting instruction is used to instruct, in the case that the dedicated instruction interface is called, to execute other called dedicated instruction interfaces after the execution of the dedicated instruction interface is completed.
16. The method according to claim 1, wherein after generating a dedicated instruction interface for describing the target assembly instruction according to the content of the target assembly instruction and the target general instruction interface, the method further comprises: :

    Get the default output path;

    According to the preset output path, the dedicated command interface is output.
17. An interface generation device, characterized in that the device comprises: a memory and a processor;

    the memory for storing program codes;

    The processor calls the program code, and when the program code is executed, is configured to perform the following operations:

    Get the target assembly instructions;

    According to the category indication information of the target assembly instruction, determine a preset general instruction interface that matches the category indication information, and obtain a target general instruction interface; wherein, different types of instruction information correspond to different preset general instruction interfaces;

    According to the content of the target assembly instruction and the target general instruction interface, a dedicated instruction interface for describing the target assembly instruction is generated.
18. 18. The apparatus according to claim 17, wherein the category indication information includes the number of operands included in the target assembly instruction and the chip identifier of the chip to which it belongs.
19. The apparatus of claim 18, wherein the processor is further configured to:

    Configure m ports for the assembly instructions of each preset category supported by the preset chip; the assembly instructions of the same preset category contain the same number of operands, and the m is not less than the operations contained in the assembly instructions of the preset category number;

    configuring an assembly instruction conversion interface; the assembly instruction conversion interface is used to generate an assembly embedded code according to the assembly instruction; the assembly embedded code is used to embed the assembly instruction into the native code of the preset chip;

    The preset general instruction interface is generated according to the port information of the m ports, the assembly instruction conversion interface, and the chip identifier of the preset chip.
20. The apparatus according to claim 19, wherein the assembly instruction conversion interface is an inline assembly interface.
21. The apparatus of claim 19, wherein the processor is further configured to:

    Divide the assembly instructions that include the same operand among the assembly instructions supported by the preset chip into the same category to obtain the preset category.
22. The apparatus according to any one of claims 17 to 21, wherein the processor is specifically configured to:

    According to the content of the target assembly instruction and the target general instruction interface, generate the interface name, the interface parameter list and the assembly embedded code of the special instruction interface;

    The dedicated instruction interface is generated according to the interface name, the interface parameter list and the assembly embedded code.
23. The apparatus according to claim 22, wherein the processor is specifically configured to:

    generating the interface name of the dedicated instruction interface according to the mnemonic, operand type and flag register information in the target assembly instruction;

    Invoke the target general-purpose instruction interface to generate an interface parameter list of the special-purpose instruction interface according to the operand port information and/or immediate data in the target assembly instruction, and convert the target assembly instruction into an assembly embedded code .
24. The apparatus according to claim 22 or 23, wherein the processor is specifically configured to:

    Obtain the abbreviated characters corresponding to each of the operand types;

    combining the abbreviated characters into an abbreviated string;

    The interface name is obtained by combining the mnemonic, the abbreviated character string and the flag register information according to a preset separator.
25. The apparatus according to claim 23, wherein the processor is specifically configured to:

    The target general instruction interface is called through a macro calling method or an interface function calling method.
26. The device according to claim 23, wherein an inline assembly interface is defined in the target general instruction interface;

    The processor is specifically used for:

    The target assembly instruction is converted into inline assembly code based on the inline assembly interface defined in the target general instruction interface.
27. The apparatus according to any one of claims 18 to 21, wherein the processor is specifically configured to:

    For any one of the preset general-purpose command interfaces, obtain the number of chip identifiers and port information defined in the preset general-purpose command interface, as the comparison chip identifiers and the number of comparisons;

    Comparing the number of comparisons and the identification of the comparison chip with the number of operands included in the target assembly instruction and the identification of the chip of the chip to which it belongs;

    If the number of comparisons is the same as the number of operands included in the target assembly instruction, and the comparison chip identifier is the same as the chip identifier of the chip to which it belongs, the preset general-purpose instruction interface is determined as the target general-purpose instruction interface. Command interface.
28. The apparatus according to claim 17, wherein the processor is specifically configured to:

    Generate a mixed instruction pool according to the assembly instructions supported by each preset chip;

    The assembly instructions contained in the mixed instruction pool are used as target assembly instructions, and the target assembly instructions are acquired from the mixed instruction pool.
29. The apparatus of claim 28, wherein the processor is further configured to:

    For any of the preset chips, a dedicated command interface corresponding to the preset chip is defined at the designated position of the native code of the preset chip, and an interface model of the preset chip is obtained; the preset chip corresponds to The dedicated instruction interface is generated according to the target assembly instruction belonging to the preset chip;

    When receiving an instruction invocation request, obtain a dedicated instruction interface matching the instruction invocation request from the interface model of the target preset chip; the chip identifier of the target preset chip and the chip included in the instruction invocation request ID matches.
30. The apparatus of claim 17, wherein the processor is further configured to:

    Acquire specified information according to the dedicated command interface; the specified information at least includes port information and the type of output parameters in the dedicated command interface;

    According to a preset annotation generation tool, the specified information is combined to obtain the interface annotation of the dedicated instruction interface.
31. The apparatus of claim 17, wherein the processor is further configured to:

    Obtain the preset parallel generation configuration information;

    If the parallel generation configuration information is a specified value, after acquiring the target assembly instruction, acquire the next target assembly instruction, and execute the special instruction for generating the next target assembly instruction according to the next target assembly instruction operation of the interface.
32. The apparatus of claim 17, wherein the processor is further configured to:

    Get the default output path;

    According to the preset output path, the dedicated command interface is output.
33. A computer-readable storage medium, characterized in that, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the interface generation method according to any one of claims 1-16 is implemented.

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