WO2021258363A1

WO2021258363A1 - Circuit reliability analysis method and apparatus, storage medium, and electronic equipment

Info

Publication number: WO2021258363A1
Application number: PCT/CN2020/098225
Authority: WO
Inventors: 湛灿辉; 杨超; 刘长泽
Original assignee: 华为技术有限公司
Priority date: 2020-06-24
Filing date: 2020-06-24
Publication date: 2021-12-30

Abstract

The embodiments of the present application provide a circuit reliability analysis method and apparatus, a storage medium, a program product, a chip, and electronic equipment. The method comprises: obtaining a circuit diagram to be analyzed; building a topology map of the circuit diagram, wherein nodes in the topology map can used for representing devices in the circuit diagram, and edges in the topology map can be used for representing connecting wires between the devices; and generating a reliability analysis result of the circuit diagram according to the topology map and a preset reliability analysis model. On the one hand, the method can avoid the analysis result being easily affected by human factors (such as incentives being missed by the staff), thereby improving the automation and intelligence of reliability analysis. On the other hand, the method can achieve full coverage of all devices of the circuit diagram and the connection relation between the devices, thereby realizing the integrity and accuracy of reliability analysis, and can improve the efficiency of reliability analysis.

Description

Circuit reliability analysis method, device, storage medium and electronic equipment

Technical field

This application relates to the technical field of circuit analysis, and in particular to a circuit reliability analysis method, device, storage medium, program product, chip, and electronic equipment.

Background technique

The analysis of circuit reliability refers to the analysis of the reliability of the performance of the circuit, such as analyzing the performance parameters of each device in the circuit, and obtaining the degradation rate and/or failure rate of the circuit.

In the prior art, a circuit reliability analysis method includes: receiving input excitation and circuit diagrams, simulating the excitation and circuit diagrams through a simulator, and outputting analysis results of the circuit diagrams, such as outputting circuit reliability results reports.

However, the inventor found that the prior art has at least the following problems: due to the need for manual input excitation, it is easy to cause the analysis result to be affected by human factors, and there are disadvantages of low efficiency and low reliability.

Summary of the invention

In order to solve the foregoing technical problems, embodiments of the present application provide a circuit reliability analysis method, device, storage medium, program product, chip, and electronic equipment.

According to one aspect of the embodiments of the present application, the embodiments of the present application provide a method for analyzing circuit reliability, and the method includes:

Obtain the circuit diagram to be analyzed;

Constructing a topology diagram of the circuit diagram, where nodes in the topology diagram are used for characterization, each device in the circuit diagram, edges in the topology diagram are used for characterization, and connecting lines between the devices;

According to the topology diagram and the preset reliability analysis model, the reliability analysis result of the circuit diagram is generated.

That is to say, the inventive concept of this application is to generate a reliability analysis model based on the sample circuit diagram and the neural network model in advance, and perform reliability analysis on the circuit diagram in combination with the reliability analysis model.

In the embodiments of the present application, on the one hand, because the embodiments of the present application analyze the reliability of the circuit diagram in combination with the topology diagram and the reliability analysis model, there is no need for manual input excitation, therefore, it can avoid the use of the integrated circuit simulator in the related technology ( Simulation Program for Integrated Circuits Emphasis, Spice) is a waste of human resources when performing reliability analysis, and the analysis results are easily affected by human factors (such as incentives being missed by the staff, etc.), which can save costs and improve reliability The analysis is automated and intelligent, and the accuracy of the analysis results is improved; on the other hand, the integrated circuit simulator is based on the number of layers of the circuit diagram, which divides the circuit diagram into multiple modules for simulation. Therefore, it may cause low efficiency and top-level simulation. The simulation cannot be completed and the partial circuit of each module interface is missed. However, by constructing the topological diagram of the circuit diagram, the embodiment of the present application can fully cover the components of the circuit diagram and the connection relationship between the components, thereby realizing reliability analysis The completeness and accuracy of the reliability analysis can improve the efficiency of reliability analysis.

In some embodiments, the generating the reliability analysis result of the circuit diagram according to the topology diagram and the preset reliability analysis model includes:

Generating an adjacency matrix according to the topological graph;

Determine the respective characteristic vector of each of the devices according to the design parameters of each of the devices;

The analysis result is generated according to the adjacency matrix, the feature vector, and the reliability analysis model.

In the embodiment of this application, the adjacency matrix can be used to determine the neighbor relationship between the nodes in the topology, and the feature vector can reflect the design parameters of the device. Therefore, the adjacency matrix and the feature vector are used as the input of the reliability analysis model Features, can get higher accuracy analysis results.

In some embodiments, the generating the analysis result according to the adjacency matrix, the eigenvector, and the reliability analysis model includes:

Performing information fusion processing on each of the nodes according to the adjacency matrix and the feature vector;

According to the information after the fusion processing and the reliability analysis model, the analysis result is generated.

In the embodiment of this application, by performing information fusion processing on each node, while obtaining the information of the neighboring node, the information of the node itself is still maintained. Therefore, two types of information (ie, the information of the neighboring node and the node itself) can be realized. The correlation and independence between the information), and then achieve the technical effect of improving the accuracy and reliability of the analysis results.

In some embodiments, the edges in the topology diagram are directed edges, and the direction of the edges is determined based on the design parameters of the device.

That is to say, in the embodiment of the present application, the direction of the side is introduced, and by introducing the direction of the side, the connection relationship between the devices can be more clearly reflected, and the accuracy of the reliability analysis can be improved.

In some embodiments, the generating an adjacency matrix according to the topological graph includes:

Determining the attribute information of the device in the topology diagram, where the attribute information is used to characterize the number of the device or the type of pin of the device;

The adjacency matrix is constructed based on the attribute information, wherein one device corresponds to one adjacency matrix, or one type of pin corresponds to one adjacency matrix.

In the embodiment of the present application, when performing reliability analysis, the number of devices or the types of pins are considered, and the adjacency matrix is constructed according to the number of devices or the types of pins, which can realize the completeness and integrity of the circuit diagram analysis. Comprehensiveness, so as to achieve the technical effect of improving the accuracy of reliability analysis.

The analysis result is generated according to each adjacency matrix, the feature vector, the reliability analysis model, and the preset weight of each adjacency matrix.

In some embodiments, the method further includes:

Construct the topology diagram of the sample circuit diagram;

Determine the design parameters of each device in the sample circuit diagram;

Collecting simulation parameters of each device in the sample circuit diagram obtained by the simulator;

The reliability analysis model is generated according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the preset neural network model, and the simulation parameters.

In some embodiments, the generating the reliability analysis model based on the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the preset neural network model, and the simulation parameters includes:

Generate test values according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the simulation parameters and the neural network model;

The parameters of the neural network model are iterated according to the test values and the simulation parameters to generate the reliability analysis model.

In the embodiment of the present application, by iterating the parameters of the neural network model, the accuracy of the reliability analysis model can be improved, thereby improving the accuracy of the analysis result.

In some embodiments, the iterating on the parameters of the neural network model according to the test values and the simulation parameters, and generating the reliability analysis model includes:

Determining a loss function according to the test value and the simulation parameter;

Determining the norm of the parameters of the neural network model as a penalty term of the loss function;

The parameters of the neural network model are iterated according to the loss function including the penalty term to generate the reliability analysis model.

In some embodiments, the constructing the topology diagram of the circuit diagram includes:

Generating the circuit netlist of the circuit diagram;

The topology diagram is constructed according to the circuit netlist.

According to another aspect of the embodiments of the present application, the embodiments of the present application also provide a circuit reliability analysis device, the device including:

The acquisition module is used to acquire the circuit diagram to be analyzed;

The first construction module is used to construct the topology diagram of the circuit diagram, wherein the nodes in the topology diagram are used for characterization, each device in the circuit diagram, the edges in the topology diagram are used for characterization, and each Connection lines between devices;

The first generating module is used to generate the reliability analysis result of the circuit diagram according to the topology diagram and the preset reliability analysis model.

In some embodiments, the first generation module is configured to generate an adjacency matrix according to the topology map, determine the respective eigenvectors of each device according to the design parameters of each device, and determine the respective eigenvectors of each device according to the adjacency matrix, the The feature vector and the reliability analysis model generate the analysis result.

In some embodiments, the first generation module is configured to perform information fusion processing on each of the nodes according to the adjacency matrix and the feature vector, and generate information based on the fusion processing information and the reliability analysis model The results of the analysis.

In some embodiments, the first generation module is used to determine the attribute information of the device in the topology diagram, where the attribute information is used to characterize the number of the device or the pin of the device The adjacency matrix is constructed based on the attribute information, wherein one device corresponds to one adjacency matrix, or one type of pin corresponds to one adjacency matrix.

In some embodiments, the first generating module is configured to generate the analysis result according to each of the adjacency matrix, the eigenvector, the reliability analysis model, and preset weights of each of the adjacency matrices .

In some embodiments, the device further includes:

The second building module is used to build the topology diagram of the sample circuit diagram;

The determining module is used to determine the design parameters of each device in the sample circuit diagram;

An acquisition module for acquiring the simulation parameters of each device in the sample circuit diagram obtained by the simulator;

The second generation module is configured to generate the reliability analysis model according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the preset neural network model, and the simulation parameters.

In some embodiments, the second generation module is configured to generate test values according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the simulation parameters and the neural network model, The parameters of the neural network model are iterated according to the test values and the simulation parameters to generate the reliability analysis model.

In some embodiments, the second generation module is configured to determine a loss function according to the test value and the simulation parameters, and determine the norm of the parameters of the neural network model as the penalty term of the loss function , Iterating the parameters of the neural network model according to the loss function including the penalty term to generate the reliability analysis model.

In some embodiments, the first construction module is used to generate a circuit netlist of the circuit diagram, and construct the topology diagram according to the circuit netlist.

According to another aspect of the embodiments of the present application, the embodiments of the present application also provide a computer storage medium having computer instructions stored on the computer storage medium. When the computer instructions are executed by a processor, any one of the foregoing The method described in the embodiment is executed.

According to another aspect of the embodiments of the present application, the embodiments of the present application also provide a computer program product, which when the computer program product runs on a processor, causes the method described in any of the foregoing embodiments to be executed.

According to another aspect of the embodiments of the present application, the embodiments of the present application also provide an electronic device, including:

At least one processor; and

A memory communicatively connected with the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the method described in any of the foregoing embodiments is executed.

According to another aspect of the embodiments of the present application, the embodiments of the present application also provide a chip, including:

Input interface, used to obtain the circuit diagram to be analyzed;

A logic circuit is used to execute the method described in any of the above embodiments to obtain an analysis result of the reliability of the circuit diagram;

The output interface is used to output the reliability analysis result of the circuit diagram.

Description of the drawings

The drawings are used to better understand the embodiments of the present application, and do not constitute a limitation to the present application. in,

FIG. 1 is a schematic flowchart of a circuit reliability analysis method according to an embodiment of the application;

FIG. 2 is a schematic diagram of a circuit diagram of an embodiment of the application;

FIG. 3 is a schematic diagram of a topology diagram of an embodiment of the application;

4 is a schematic flowchart of a circuit reliability analysis method according to another embodiment of the application;

FIG. 5 is a schematic diagram of a circuit netlist generated based on the circuit diagram shown in FIG. 2;

Fig. 6 is a schematic diagram of an adjacency matrix according to an embodiment of the application;

FIG. 7 is a schematic diagram of a feature vector according to an embodiment of the application;

8 is a schematic flowchart of a circuit reliability analysis method according to another embodiment of the application;

FIG. 9 is a schematic diagram of a topological diagram including the direction of edges according to an embodiment of the present application;

10 is a schematic flowchart of a method for generating a reliability analysis model according to an embodiment of the application;

FIG. 11 is a schematic diagram of a circuit reliability analysis device according to an embodiment of the application;

FIG. 12 is a schematic diagram of a circuit reliability analysis device according to another embodiment of the application;

FIG. 13 is a block diagram of an electronic device according to an embodiment of the application;

FIG. 14 is a schematic diagram of a chip according to an embodiment of the application.

detailed description

Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the application as detailed in the appended claims.

The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

According to one aspect of the embodiments of the present application, the embodiments of the present application provide a method for analyzing circuit reliability.

Please refer to FIG. 1. FIG. 1 is a schematic flowchart of a circuit reliability analysis method according to an embodiment of the application.

As shown in Figure 1, the method includes:

S101: Obtain a circuit diagram to be analyzed.

Among them, the execution subject of the embodiments of the present application may be a circuit reliability analysis device (hereinafter referred to as the analysis device), and the analysis device may be a computer, a server, a processor, a chip, a terminal device, and the like.

S102: Construct a topological diagram of a circuit diagram, where nodes in the topological diagram can be used for characterization, each device in the circuit diagram, edges in the topological diagram can be used for characterization, and a connection line between each device.

The construction topology diagram of the embodiment of the present application will now be described in detail with reference to FIG. 2 and FIG. 3, wherein FIG. 2 is a circuit diagram of an embodiment of the application, and FIG. 3 is a topology diagram of an embodiment of the application.

As shown in Figure 2, the circuit diagram includes 4 MOS (metal oxide semiconductor) tubes, which are marked as M1, M2, M3, and M4; each MOS tube is connected by a connecting line Net, and the connecting lines are marked as N1, N2, and N3. , N4 and N5; Vdd can be used for characterization, the power supply is the working voltage provided by the circuit diagram; Vss can be used for characterization, the common ground terminal voltage of the circuit diagram; Is can be used for characterization, the signal source of the circuit diagram.

According to the connection lines between the MOS tube and each MOS tube in FIG. 2, the topology diagram shown in FIG. 3 is constructed.

Specifically, the analysis device can construct nodes based on MOS transistors, and construct connections between nodes and nodes based on the connecting lines between MOS transistors, and then a topology diagram including nodes and edges (that is, connections between nodes and nodes) can be obtained.

For example, based on Figure 2, one pin of M1 is connected to two pins of M3 respectively through N2. Therefore, in Figure 3, there are two connecting lines between node M1 and node M2, and both are marked as N2; In the same way, a pin of M2 is connected to M4 through N3, then in Fig. 3, there is a connection line between node M2 and node M4, which is marked as N3, and so on, and will not be repeated here.

In the embodiment of the present application, by constructing a topological diagram of the circuit diagram, and the topological diagram fully covers the various components of the circuit diagram and the connection relationship between the components, therefore, the completeness and accuracy of the subsequent reliability analysis can be achieved. Effect.

S103: Generate a reliability analysis result of the circuit diagram according to the topology diagram and the preset reliability analysis model.

Among them, the reliability analysis result (hereinafter referred to as the analysis result) can be used to characterize the degradation rate and/or failure rate of the circuit in the circuit diagram.

The reliability analysis model can be used for characterization, and is a network model used to analyze the reliability of the circuit. In some embodiments, the reliability analysis model can be generated based on a sample circuit diagram and a preset neural network model.

Among them, the number of sample circuit diagrams can be selected based on requirements, historical records, experiments, etc., and the embodiment of the present application does not limit the number of sample circuit diagrams.

Taking the number of sample circuit diagrams based on demand as an example, the following explanations are made:

Among them, the demand can be used for characterization. The demand for the reliability of the analysis result is preset in the analysis device, and the analysis device can select a relatively large number of sample circuit diagrams for the relatively high reliability requirements to improve the reliability. The accuracy of the analysis model improves the reliability of the analysis results; conversely, the analysis device can select a relatively small number of sample circuit diagrams for relatively low reliability requirements.

Taking the number of sample circuit diagrams based on historical records as an example, the following explanations are made:

Based on historical records, the analysis device knows that when the number of sample circuit diagrams is within a certain number interval, the accuracy of the reliability analysis model is relatively high and can meet the preset analysis needs, then the analysis device can select the number of sample circuit diagrams based on the number interval .

Taking the number of sample circuit diagrams based on experiments as an example, the following explanations are made:

In the test phase, a number of quantitative intervals are preset in the analysis device. The analysis device selects the sample circuit diagrams of each quantity interval, generates the reliability analysis model of the test stage based on each quantity interval, and selects the number of the sample circuit diagrams based on the accuracy of the reliability analysis model of each test stage.

It is worth noting that the above examples are only used to illustrate possible implementations of selecting the number of sample circuit diagrams, and should not be understood as a limitation of the embodiments of the present application.

Among them, the neural network model can be any one of a convolutional neural network model, a recurrent neural network model, a deep neural network model, and a feedforward neural network model. In the same way, the embodiment of the application does not limit the type of neural network, and the embodiment of the application can also select the neural network model based on needs, experience, and experiment. For the selection principle, please refer to the above example, which will not be repeated here. .

Based on the above analysis, it can be seen that an embodiment of the present application provides a circuit reliability analysis method. The method includes: obtaining a circuit diagram to be analyzed, and constructing a topological diagram of the circuit diagram. The nodes in the topological diagram can be used for characterization. The edges in the topology diagram can be used to characterize each device, the connection line between each device, according to the topology diagram and the preset reliability analysis model, generate the reliability analysis result of the circuit diagram. On the one hand, due to the implementation of this application The example is to analyze the reliability of the circuit diagram by combining the topology diagram and the reliability analysis model without manual input excitation. Therefore, it can avoid the reliability analysis through the integrated circuit simulator (Simulation Program for Integrated Circuits Emphasis, Spice) in the related technology. , Resulting in a waste of human resources, and analysis results are easily affected by human factors (such as incentives missed by staff, etc.), which can save costs, improve the automation and intelligence of reliability analysis, and improve the accuracy of analysis results ; On the other hand, the integrated circuit simulator is based on the number of layers of the circuit diagram and divides the circuit diagram into multiple modules for simulation. Therefore, it may cause problems such as low efficiency, inability to complete the simulation at the top level, and missing parts of the circuit of each module interface. However, by constructing the topology diagram of the circuit diagram in the embodiment of the present application, it is possible to achieve a comprehensive coverage of the various components of the circuit diagram and the connection relationship between the components, thereby achieving the completeness and accuracy of the reliability analysis, and improving the reliability analysis. efficient.

In order to enable the reader to understand more clearly how to generate the analysis result, the circuit reliability analysis method of the embodiment of the present application will now be described in detail with reference to FIG. 4. 4 is a schematic flowchart of a circuit reliability analysis method according to another embodiment of the application.

As shown in Figure 4, the method includes:

S201: Obtain a circuit diagram to be analyzed.

Among them, the description of S201 can refer to S101, which will not be repeated here.

S202: Construct a topological diagram of the circuit diagram, where nodes in the topological diagram are used for characterization, each device in the circuit diagram, edges in the topological diagram are used for characterization, and connecting lines between the devices.

For the description of S202, refer to S102, which will not be repeated here.

In some embodiments, S202 may include:

S2021: Generate the circuit netlist of the circuit diagram.

Among them, the circuit netlist can be used to characterize and describe the text of the connecting lines of each device, and/or the text of the parameters of each device.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a circuit netlist generated based on the circuit diagram shown in FIG. 2.

On the one hand, as shown in Figure 5, the circuit netlist exemplarily shows the connection lines of each device.

For example, taking M3 as an example, in conjunction with Figure 2, it can be seen that the analysis device can determine that the gate and drain of M3 are connected to other devices through N2. For example, the drain of M3 is connected to M1 through N2, and the gate of M3 is connected to N2 through N2. M4 is connected, and the substrate and source of M3 are both connected to Vdd through N4. Therefore, the analysis device can generate the text of (N2N2N4N4) as shown in FIG. 5 with the connection line connected to M3.

On the other hand, as shown in FIG. 5, the circuit netlist generated by the analysis device also exemplarily shows the parameters of each device.

For example, taking M3 as an example, the parameters of M3 may include the model pch_18mac of M3, the length of the channel of M3 l=135n (nm), and the width of the channel of M3 w=98n (nm).

For another example, taking M2 as an example, the parameters of M2 may include the model of M2 nch_18mac, the length of the channel of M2 l=135n (nanometers), and the width of the channel of M2 w=98n (nanometers).

For another example, taking Is as an example, isource means that Is is a current source, and type=dc means that the type of Is is a direct current power supply.

It is worth noting that the above examples are only used to exemplarily illustrate the possible parameters of each device in FIG. 2 and cannot be understood as limiting the types and ranges of parameters of each device.

S2022: Construct a topology diagram according to the circuit netlist.

Based on the above example, it can be seen that the circuit netlist can be used to characterize the text of the connection lines of each device, and/or the text of the parameters of each device. Therefore, when the analysis device generates the circuit netlist, each node can be generated according to each device. , And construct the edge between each node according to the connecting line of each device, thereby generating the topological graph.

S203: Generate an adjacency matrix according to the topological graph.

Among them, the adjacency matrix can be used to characterize the matrix of adjacent relationships between nodes. In other words, through the adjacency matrix, the connection relationship between the nodes can be determined.

Based on the above example, the adjacency matrix shown in FIG. 6 can be generated according to the topology diagram shown in FIG. 3.

In the adjacency matrix shown in FIG. 6, each number is used to represent the number of connecting lines between each device. For example, there is one connection line between M1 and M2, two connection lines between M1 and M3, and so on.

S204: Determine the respective feature vector of each device according to the design parameters of each device.

Among them, the design parameters can be used for characterization, parameters related to the shape of the device and/or parameters related to the performance of the device.

Specifically, the parameters related to the shape of the device may include the shape dimensions of the device, such as length, width, and height, etc.; the parameters related to the performance of the device may include the resistance and power of the device, and so on.

For example, according to the circuit diagram shown in FIG. 2, the characteristic vector of each device in FIG. 2 can be determined according to the design parameters of each device in FIG. 2. For details, please refer to FIG. 7.

In Figure 7, std core can be used to characterize the standard parameters of the device (based on industry standards); IO core can be used to characterize the parameters of the IO interface of the device; Dio can be used to characterize the stroboscopic parameters of the device; R It can be used to characterize the resistance of the device; C can be used to characterize the capacitance of the device; V can be used to characterize the voltage of the device.

For example, the feature vector of M1 is a value formed by combining the standard parameters of M1, the parameters of the IO interface, the de-flickering parameters, the resistance, the capacitance, and the voltage in sequence, and so on, which will not be repeated here.

S205: Generate an analysis result according to the adjacency matrix, eigenvector, and reliability analysis model.

In some embodiments, S205 may include:

S2051: Perform information fusion processing on each node according to the adjacency matrix and the feature vector.

Among them, the information fusion processing can be used for characterization. For each node, the analysis device fuses the information of the nodes adjacent to the node (hereinafter referred to as the adjacent node), and combines the information of the fused adjacent node with the node. The information is fused, that is, the information after fusion processing includes not only the information of the node itself, but also the information of neighboring nodes.

Based on the above example, it can be seen that M2, M3, M4, and Is are all adjacent nodes of M1, and the analysis device uses matrix multiplication to multiply the first row of the adjacency matrix shown in Figure 6 by the eigenvector in Figure 7, then The feature vectors of M1's neighboring nodes M2, M3, M4 and Is are merged into a feature vector, which can be used to characterize the information of M1's neighboring nodes, and then the neighboring node information and M1 information are fused Processing, and so on, will not be repeated here.

In some embodiments, the circuit structure may be a multi-layer circuit structure. When the circuit structure is a multi-layer circuit structure, the analysis device can perform information fusion processing on nodes between different layers through Equation 1, Equation 1:

F ^(l) =σ(CONCAT(AF ^(l-1) ,F ^(l-1) )W ^(l) )

Among them, F ^(l) is the eigenvector of each device output by the lth layer; A is the adjacency matrix of the 1-1 layer; F ^(l-1) is the eigenvector of each device output by the 1-1 layer; W ^(l) is the preset model parameter, W ^(l) can be the sum of squares of the reliability index of each sample circuit diagram generated by the integrated circuit simulator; CONCAT() is the splicing operation, CONCAT(AF ^(l-1) , F ^(l-1) ) can represent the ^{splicing process of AF (l-1)} and F ^(l-1) , that is, take the ^{union of AF (l-1)} and F ^(l-1) ; σ is the activation function , Can mean that (CONCAT(AF ^(l-1) , F ^(l-1) )W ^(l) ) is non-linear processing.

S2052: Generate an analysis result according to the information after the fusion processing and the reliability analysis model.

Based on the above example, the analysis result can be used to characterize the degradation rate and/or failure rate of the circuit. In this step, the analysis device can input the fusion processed information into the reliability analysis model, and based on the reliability analysis model Generate the degradation rate and/or failure rate of the circuit as shown in FIG. 2.

Specifically, based on the foregoing example, it can be known that the reliability analysis model is generated based on the sample circuit diagram and the preset neural network model, that is, the reliability analysis model may be a neural network model for analyzing the reliability of the circuit.

It is worth noting that the reliability analysis model includes multiple neurons. Neurons can store information, can also act as information transmitters, and can also act as information processors. Each neuron includes parameters such as connection weights. In the embodiment of the present application, the analysis device may calculate the fusion processed information based on each neuron, so as to generate the degradation rate and/or failure rate of each device.

For example, each neuron can perform multiplication calculation on parameters such as the fusion processed information and connection weight, and generate the degradation rate and/or failure rate of each device.

In order to further improve the reliability and accuracy of the analysis result, the embodiment of the present application further improves the circuit reliability analysis method on the basis of the above example, which will be described in detail with reference to FIG. 8. Wherein, FIG. 8 is a schematic flowchart of a circuit reliability analysis method according to another embodiment of the application.

As shown in Figure 8, the method includes:

S301: Obtain a circuit diagram to be analyzed.

For the description of S3201, please refer to S101, which is not repeated here.

S302: Construct a topological diagram of the circuit diagram, where nodes in the topological diagram are used for characterization, each device in the circuit diagram, edges in the topological diagram are used for characterization, connecting lines between the devices, and edges in the topological diagram are The pointing side, the direction of the side is determined based on the design parameters of the device.

Among them, for part of the description of S201, refer to S102, which will not be repeated here.

In the embodiments of the present application, the edges in the topology diagram are oriented edges, and the orientation of the edges can be used to reflect the input impedance of each device.

In some embodiments, the direction of the side can be determined based on the direction of current and voltage. Of course, the direction of the side can also be determined based on other design parameters, which will not be listed here.

For example, on the basis of FIG. 2, a schematic diagram of a topological diagram including the direction of edges as shown in FIG. 9 can be obtained. Among them, Fig. 9 exemplarily shows the direction of the edges of the node M4 and the nodes M1 and M3, respectively.

S303: Determine the attribute information of the device in the topology map, where the attribute information can be used to characterize the number of the device or the type of the pin of the device.

Based on the above example, if the device is a MOS tube, the types of pins may include drain, source, and gate.

That is to say, in the embodiments of the present application, the reliability of the circuit diagram can be analyzed based on the number of devices or the types of pins.

S304: Construct an adjacency matrix based on the attribute information, where one device corresponds to one adjacency matrix, or one type of pin corresponds to one adjacency matrix.

Among them, the principle of constructing the adjacency matrix can be referred to the above example, which will not be repeated here.

S305: Generate an analysis result according to each adjacency matrix, eigenvector, reliability analysis model, and preset weights of each adjacency matrix.

In the embodiment of this application, because the analysis device considers the quantity of each device or the type of each pin, there are multiple adjacency matrices obtained. On this basis, the analysis device is configured for each adjacency matrix The weight, and the weight can be set based on requirements, historical records, experiments, etc., and the specific setting method can be referred to the above example, which will not be repeated here.

Similarly, for the specific implementation method of S305, please refer to S2051 and S2052 in the above example. Since there are multiple adjacency matrices in the embodiment of this application, and the weights set for each adjacency matrix are introduced, when the circuit structure is a multilayer When the circuit structure is used, formula 1 can be modified adaptively, for example, formula 1 is modified to formula 2, and information fusion processing is carried out through formula 2, formula 2:

F ^(l) =σ(CONCAT(∑w _i A _i F ^(l-1) ,F ^(l-1) )W ^(l) )

Among them, F ^(l) is the eigenvector of each device output by the lth layer, A _i is the adjacency matrix of the i-th topological graph of the l-1 layer, w _i is the weight of A _i ^{, F (l-1)} Is the feature vector of each device output from the l-1 layer, W ^(l) is the preset model parameter, CONCAT() is the splicing operation, and σ is the activation function.

In order to make the reader understand more clearly how to generate the reliability analysis model, it will be described in detail in conjunction with Figure 10. 10 is a schematic flowchart of a method for generating a reliability analysis model according to an embodiment of the application.

As shown in Figure 10, the method includes:

S1: Construct the topology diagram of the sample circuit diagram.

Among them, the method of constructing the topology diagram of the sample circuit diagram can refer to the above-mentioned example, which will not be repeated here.

S2: Determine the design parameters of each device in the sample circuit diagram.

S3: Collect the simulation parameters of each device in the sample circuit diagram obtained by the simulator.

Among them, simulation parameters can be used for characterization, degradation rate and/or failure rate.

Wherein, the simulator may be the integrated circuit simulator in the above example.

S4: Generate a reliability analysis model based on the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the neural network model and the simulation parameters.

In some embodiments, S4 may include:

S41: Generate test values according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the simulation parameters and the neural network model.

S42: Iterate the parameters of the neural network model according to the test values and simulation parameters to generate a reliability analysis model.

In some embodiments, S42 may include:

S421: Determine the loss function according to the test value and the simulation parameter.

S422: Determine the norm of the parameters of the neural network model as the penalty term of the loss function.

S423: Iterate the parameters of the neural network model according to the loss function including the penalty term to generate a reliability analysis model.

According to another aspect of the embodiments of the present application, the embodiments of the present application also provide a circuit reliability analysis device, which is used to perform the method described in any of the above embodiments, for example, it is used to perform Figure 1, Figure 4, The method shown in any one of the embodiments in FIG. 8 and FIG. 10.

Please refer to FIG. 11. FIG. 11 is a schematic diagram of a circuit reliability analysis device according to an embodiment of the application.

As shown in Figure 11, the device includes:

The obtaining module 11 is used to obtain the circuit diagram to be analyzed;

The first construction module 12 is used to construct the topological diagram of the circuit diagram, where nodes in the topological diagram are used for characterization, each device in the circuit diagram, edges in the topological diagram are used for characterization, and each The connecting wires between the devices;

The first generating module 13 is configured to generate the reliability analysis result of the circuit diagram according to the topology diagram and the preset reliability analysis model, wherein the reliability analysis model is based on the sample circuit diagram and the preset nerve analysis model. Generated by the network model.

In some embodiments, the first generating module 13 is configured to generate an adjacency matrix according to the topology map, determine the respective eigenvectors of each device according to the design parameters of each device, and determine the respective eigenvectors of each device according to the adjacency matrix and the The feature vector and the reliability analysis model are used to generate the analysis result.

In some embodiments, the first generating module 13 is configured to perform information fusion processing on each of the nodes according to the adjacency matrix and the feature vector, and according to the information after the fusion processing and the reliability analysis model, Generate the analysis results.

In some embodiments, the first generating module 13 is used to determine the attribute information of the device in the topology map, where the attribute information is used to characterize the quantity of the device or the management of the device. The type of pins is used to construct the adjacency matrix based on the attribute information, wherein one device corresponds to one adjacency matrix, or one type of pin corresponds to one adjacency matrix.

In some embodiments, the first generating module 13 is configured to generate the analysis according to the adjacency matrix, the eigenvector, the reliability analysis model, and the preset weight of each adjacency matrix. result.

With reference to FIG. 12, it can be seen that in some embodiments, the device further includes:

The second construction module 14 is used to construct the topology diagram of the sample circuit diagram;

The determining module 15 is used to determine the design parameters of each device in the sample circuit diagram;

The collection module 16 is used to collect the simulation parameters of each device in the sample circuit diagram obtained by the simulator;

The second generation module 17 is configured to generate the reliability analysis model according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the neural network model, and the simulation parameters.

In some embodiments, the second generating module 17 is configured to generate test values according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the simulation parameters and the neural network model, and The test value and the simulation parameter iterate the parameters of the neural network model to generate the reliability analysis model.

In some embodiments, the second generation module 17 is configured to determine a loss function according to the test value and the simulation parameters, and determine the norm of the parameters of the neural network model as the penalty term of the loss function, The parameters of the neural network model are iterated according to the loss function including the penalty term to generate the reliability analysis model.

In some embodiments, the first construction module 14 is configured to generate a circuit netlist of the circuit diagram, and construct the topology diagram according to the circuit netlist.

According to another aspect of the embodiments of the present application, the embodiments of the present application also provide a computer storage medium having computer instructions stored on the computer storage medium. When the computer instructions are executed by a processor, any one of the foregoing The method described in the embodiment is executed, and the method shown in any one of the embodiments in FIG. 1, FIG. 4, FIG. 8 and FIG. 10 is executed.

According to another aspect of the embodiments of the present application, the embodiments of the present application also provide a computer program product. When the computer program product runs on a processor, the method described in any of the above embodiments is executed, such as The method shown in any one of the embodiments in FIG. 1, FIG. 4, FIG. 8, and FIG. 10 is executed.

At least one processor; and

A memory communicatively connected with the at least one processor; wherein,

The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor, so that the method described in any of the foregoing embodiments is executed, as shown in FIG. 1, FIG. 4, and FIG. The method shown in any one of the embodiments in FIG. 8 and FIG. 10 is executed.

Please refer to FIG. 13, which is a block diagram of an electronic device according to an embodiment of the application.

Among them, the electronic device is intended to mean various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the application described and/or required herein.

As shown in FIG. 13, the electronic device includes: one or more processors 101, a memory 102, and interfaces for connecting various components, including a high-speed interface and a low-speed interface. The various components are connected to each other using different buses, and can be installed on a common motherboard or installed in other ways as needed. The processor may process instructions executed in the electronic device, including instructions stored in or on the memory to display graphical information of the GUI on an external input/output device (such as a display device coupled to an interface). In other embodiments, if necessary, multiple processors and/or multiple buses can be used with multiple memories and multiple memories. Similarly, multiple electronic devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). In FIG. 13, a processor 101 is taken as an example.

The memory 102 is a non-transitory computer-readable storage medium provided by this application. Wherein, the memory stores instructions executable by at least one processor, so that the at least one processor executes the circuit reliability analysis method provided by this application. The non-transitory computer-readable storage medium of the present application stores computer instructions, and the computer instructions are used to make a computer execute the circuit reliability analysis method provided by the present application.

As a non-transitory computer-readable storage medium, the memory 102 can be used to store non-transitory software programs, non-transitory computer executable programs, and modules. The processor 101 executes various functional applications and data processing of the server by running non-transitory software programs, instructions, and modules stored in the memory 102, that is, realizing the circuit reliability analysis method in the foregoing method embodiment.

The memory 102 may include a storage program area and a storage data area. The storage program area may store an operating system and an application program required by at least one function; the storage data area may store data created according to the use of the electronic device, and the like. In addition, the memory 102 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory 102 may optionally include memories remotely provided with respect to the processor 101, and these remote memories may be connected to the electronic device via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

The electronic device may further include: an input device 103 and an output device 104. The processor 101, the memory 102, the input device 103, and the output device 104 may be connected by a bus or in other ways. In FIG. 13, the connection by a bus is taken as an example.

The input device 103 can receive input digital or character information, and generate key signal input related to the user settings and function control of the electronic device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, a pointing stick, one or more Input devices such as mouse buttons, trackballs, joysticks, etc. The output device 104 may include a display device, an auxiliary lighting device (for example, LED), a tactile feedback device (for example, a vibration motor), and the like. The display device may include, but is not limited to, a liquid crystal display (LCD), a light emitting diode (LED) display, and a plasma display. In some embodiments, the display device may be a touch screen. For example, the input device 103 may be used to input circuit diagrams, and the output device 104 may be used to output analysis results.

Various implementations of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, application specific ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: being implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, the programmable processor It can be a dedicated or general-purpose programmable processor that can receive data and instructions from the storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device. An output device.

These computing programs (also referred to as programs, software, software applications, or codes) include machine instructions for programmable processors, and can be implemented using high-level procedures and/or object-oriented programming languages, and/or assembly/machine language Calculation program. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and/or device used to provide machine instructions and/or data to a programmable processor ( For example, magnetic disks, optical disks, memory, programmable logic devices (PLD)), including machine-readable media that receive machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor.

In order to provide interaction with the user, the systems and techniques described here can be implemented on a computer that has: a display device for displaying information to the user (for example, a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) ); and a keyboard and a pointing device (for example, a mouse or a trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (for example, visual feedback, auditory feedback, or tactile feedback); and can be in any form (including Acoustic input, voice input, or tactile input) to receive input from the user.

The systems and technologies described herein can be implemented in a computing system that includes back-end components (for example, as a data server), or a computing system that includes middleware components (for example, an application server), or a computing system that includes front-end components (for example, A user computer with a graphical user interface or a web browser through which the user can interact with the implementation of the system and technology described herein), or includes such back-end components, middleware components, Or any combination of front-end components in a computing system. The components of the system can be connected to each other through any form or medium of digital data communication (for example, a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

The computer system can include clients and servers. The client and server are generally far away from each other and usually interact through a communication network. The relationship between the client and the server is generated through computer programs that run on the corresponding computers and have a client-server relationship with each other.

According to another aspect of the embodiment of the present application, the embodiment of the present application also provides a chip.

Please refer to FIG. 14, which is a schematic diagram of a chip according to an embodiment of the application.

As shown in Figure 14, the chip includes:

The input interface 21 is used to obtain the circuit diagram to be analyzed.

The logic circuit 22 is used to execute the method described in any of the above embodiments, such as executing the method shown in any of the embodiments in FIG. 1, FIG. 4, FIG. 8, and FIG. 10, to obtain an analysis of the reliability of the circuit diagram result.

The output interface 23 is used to output the analysis result of the reliability of the circuit diagram.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present application can be executed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution of the present application can be achieved, this is not limited herein.

The foregoing specific implementations do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement made within the spirit and principle of this application shall be included in the protection scope of this application.

Claims

A method for analyzing circuit reliability, characterized in that the method includes:

Obtain the circuit diagram to be analyzed;

Constructing a topology diagram of the circuit diagram, where nodes in the topology diagram are used for characterization, each device in the circuit diagram, edges in the topology diagram are used for characterization, and connecting lines between the devices;

According to the topology diagram and the preset reliability analysis model, the reliability analysis result of the circuit diagram is generated.
The method according to claim 1, wherein the generating an analysis result of the reliability of the circuit diagram according to the topology diagram and a preset reliability analysis model comprises:

Generating an adjacency matrix according to the topological graph;

Determine the respective characteristic vector of each of the devices according to the design parameters of each of the devices;

The analysis result is generated according to the adjacency matrix, the feature vector, and the reliability analysis model.
The method according to claim 2, wherein said generating said analysis result according to said adjacency matrix, said eigenvector and said reliability analysis model comprises:

Performing information fusion processing on each of the nodes according to the adjacency matrix and the feature vector;

According to the information after the fusion processing and the reliability analysis model, the analysis result is generated.
The method according to claim 2 or 3, wherein the edges in the topology diagram are oriented edges, and the orientation of the edges is determined based on the design parameters of the device.
The method according to claim 4, wherein the generating an adjacency matrix according to the topological graph comprises:

Determining the attribute information of the device in the topology diagram, where the attribute information is used to characterize the number of the device or the type of pin of the device;

The adjacency matrix is constructed based on the attribute information, wherein one device corresponds to one adjacency matrix, or one type of pin corresponds to one adjacency matrix.
The method according to claim 5, wherein said generating said analysis result according to said adjacency matrix, said eigenvector and said reliability analysis model comprises:

The analysis result is generated according to each adjacency matrix, the feature vector, the reliability analysis model, and the preset weight of each adjacency matrix.
The method according to any one of claims 1 to 6, wherein the method further comprises:

Construct the topology diagram of the sample circuit diagram;

Determine the design parameters of each device in the sample circuit diagram;

Collecting simulation parameters of each device in the sample circuit diagram obtained by the simulator;

The reliability analysis model is generated according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the preset neural network model, and the simulation parameters.
8. The method according to claim 7, wherein said generating said circuit diagram according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the preset neural network model and the simulation parameters Reliability analysis models include:

Generate test values according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the simulation parameters and the neural network model;

The parameters of the neural network model are iterated according to the test values and the simulation parameters to generate the reliability analysis model.
The method according to claim 8, wherein the iterating the parameters of the neural network model according to the test values and the simulation parameters to generate the reliability analysis model comprises:

Determining a loss function according to the test value and the simulation parameter;

Determining the norm of the parameters of the neural network model as the penalty term of the loss function;

The parameters of the neural network model are iterated according to the loss function including the penalty term to generate the reliability analysis model.
The method according to any one of claims 1 to 9, wherein the constructing the topology diagram of the circuit diagram comprises:

Generating the circuit netlist of the circuit diagram;

The topology diagram is constructed according to the circuit netlist.
A circuit reliability analysis device, characterized in that the device includes:

The acquisition module is used to acquire the circuit diagram to be analyzed;

The first building module is used to construct a topology diagram of the circuit diagram, where nodes in the topology diagram are used for characterization, each device in the circuit diagram, edges in the topology diagram are used for characterization, and each Connection lines between devices;

The first generating module is configured to generate the reliability analysis result of the circuit diagram according to the topology diagram and the preset reliability analysis model.
The device according to claim 11, wherein the first generating module is configured to generate an adjacency matrix according to the topology map, determine the respective eigenvectors of each of the devices according to the design parameters of each of the devices, and The adjacency matrix, the feature vector, and the reliability analysis model generate the analysis result.
The device according to claim 12, wherein the first generating module is configured to perform information fusion processing on each of the nodes according to the adjacency matrix and the feature vector, and perform information fusion processing on each of the nodes according to the fusion processing information and all the information. The reliability analysis model is used to generate the analysis result.
The device according to claim 12 or 13, wherein the edges in the topology diagram are oriented edges, and the orientation of the edges is determined based on the design parameters of the device.
The apparatus according to claim 14, wherein the first generating module is configured to determine the attribute information of the device in the topology map, wherein the attribute information is used to characterize the number of the device Or the types of pins of the devices, based on the attribute information, construct the adjacency matrix, wherein one device corresponds to one adjacency matrix, or one type of pins corresponds to one adjacency matrix.
The device according to claim 15, wherein the first generating module is configured to: according to the adjacency matrix, the eigenvector, the reliability analysis model, and the preset adjacency matrix Weight, which generates the analysis result.
The device according to any one of claims 11 to 16, wherein the device further comprises:

The second building module is used to build the topology diagram of the sample circuit diagram;

The determining module is used to determine the design parameters of each device in the sample circuit diagram;

An acquisition module for acquiring the simulation parameters of each device in the sample circuit diagram obtained by the simulator;

The second generation module is configured to generate the reliability analysis model according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the preset neural network model, and the simulation parameters.
The device according to claim 17, wherein the second generation module is configured to, according to the topology diagram of the sample circuit diagram, the design parameters of each device in the sample circuit diagram, the simulation parameters and the nerve A network model generates a test value, and the parameters of the neural network model are iterated according to the test value and the simulation parameter to generate the reliability analysis model.
The device according to claim 18, wherein the second generation module is configured to determine a loss function according to the test value and the simulation parameter, and determine the norm of the parameters of the neural network model as The penalty term of the loss function is to iterate the parameters of the neural network model according to the loss function including the penalty term to generate the reliability analysis model.
The device according to any one of claims 11 to 19, wherein the first construction module is configured to generate a circuit netlist of the circuit diagram, and construct the topology diagram according to the circuit netlist.
A computer storage medium, characterized in that computer instructions are stored on the computer storage medium, and when the computer instructions are executed by a processor, the method according to any one of claims 1 to 10 is executed.
A computer program product, characterized in that, when the computer program product runs on a processor, the method according to any one of claims 1 to 10 is executed.
An electronic device, characterized in that it comprises:

At least one processor; and

A memory communicatively connected with the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the method according to any one of claims 1 to 10 is executed.
A chip, characterized in that it comprises:

Input interface, used to obtain the circuit diagram to be analyzed;

A logic circuit for executing the method according to any one of claims 1 to 10 to obtain the analysis result of the reliability of the circuit diagram;

The output interface is used to output the reliability analysis result of the circuit diagram.