WO2021233363A1

WO2021233363A1 - Computing device and bios update method therefor, and medium

Info

Publication number: WO2021233363A1
Application number: PCT/CN2021/094778
Authority: WO
Inventors: 杨林; 马秋涛; 董德远
Original assignee: 华为技术有限公司
Priority date: 2020-05-21
Filing date: 2021-05-20
Publication date: 2021-11-25
Also published as: CN113703799A

Abstract

A computing device and a BIOS system update method therefor, and a medium, relating to the field of computers. The BIOS system update method comprises: an operating system of a computing device enters a dormant state; after the operating system enters the dormant state, restart a basic input/output system; the basic input/output system obtains an update file of the basic input/output system, and executes update of the basic input/output system on the basis of the obtained update file; after the basic input/output system is updated, the operating system wakes up from the dormant state. The update of the BIOS system can be completed after the operating system of the computing device enters the dormant state, without restarting the computing device, and the working state of the operating system can be kept before and after the update of the BIOS system.

Description

Computing device and its BIOS update method and medium

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on May 21, 2020, the application number is 202010436449.8, and the application name is "computing equipment and its BIOS update method and medium", the entire content of which is incorporated herein by reference Applying.

Technical field

This application relates to the computer field, and more specifically, discloses a computing device and its BIOS update method and medium.

Background technique

Basic Input Output System (BIOS) is usually a set of programs stored in the non-volatile memory on the computer motherboard, including the most important basic input and output programs of the terminal, self-checking programs after booting, and system startup Programs, etc., are one of the foundations of the terminal system. With the rapid development of computers, BIOS, the most important underlying firmware update for PCs, is becoming more and more frequent. BIOS iterations and updates can better solve product problems, such as CPU (Central Processing Unit, central processing unit) and other hardware security vulnerabilities and product design issues, thereby improving user experience.

However, because the BIOS update requires the system to restart, the current operation of the system cannot be saved, so users are not willing to update. In addition, the BIOS cannot be forced to push the update at present.

Summary of the invention

The purpose of this application is to provide a computing device and its BIOS update method and medium, so as to update the BIOS without restarting the operating system, so as to save the current operation of the operating system.

In the first aspect, an embodiment of the present application provides a method for updating a basic input output system of a computing device, including: the operating system of the computing device enters a sleep state; after the operating system enters the sleep state, restarting the basic Input output system; the basic input output system obtains the update file of the basic input output system, and performs the update of the basic input output system based on the obtained update file; after the basic input output system is updated, the operating system Waking up from the dormant state.

That is, in this method, the operating system OS is first made to enter the sleep state, and the basic input output system BIOS is closed. Then restart the BIOS to start the BIOS update, and wake up the OS after the BIOS update is complete. In this way, the current operation of the OS is saved while the BIOS update is completed.

In an implementation of the foregoing first aspect, entering the operating system of the computing device into the sleep state includes: the update program of the basic input output system sends a sleep instruction to the operating system, and the operating system enters the sleep state. Specifically, the BIOS update program may send a sleep instruction to the CPU of the computing device through the BIOS, the CPU turns off the power supply, and the OS enters the sleep state.

In an implementation of the foregoing first aspect, after the operating system enters the sleep state, restarting the basic input output system includes: after the operating system enters the sleep state, resetting the embedded controller of the computing device The central processing unit of the computing device restarts the basic input output system.

After the operating system OS enters the sleep state, the embedded controller EC decoupled from the OS is still in a working state, so the EC decoupled from the OS can be used to reset the CPU, thereby restarting the BIOS for updating.

In an implementation of the foregoing first aspect, the foregoing method further includes: before the operating system enters the sleep state, the basic input output system sets a wake-up flag bit for the embedded controller, wherein the embedded controller After acquiring the wake-up flag bit, the controller resets the central processing unit.

In an implementation of the foregoing first aspect, the foregoing method further includes: after the embedded controller resets the central processing unit, deleting the wake-up flag bit.

In an implementation of the above-mentioned first aspect, the basic input output system performs the update of the basic input output system in the following manner: the basic input output system writes the update file into the basic input of the computing device The output system chip; the basic input output system resets the central processing unit of the computing device to load the update file in the basic input output system chip into the memory of the computing device.

That is, after the BIOS of the basic input output system writes the BIOS update file into the BIOS chip, it needs to reset the CPU to load the BIOS update file into the memory to complete the BIOS update.

In an implementation of the above-mentioned first aspect, after the basic input output system is updated, waking up the operating system from the sleep state includes: reading the operating system from the hard disk of the computing device and enters sleep Related data before the state; based on the obtained related data, the operating system returns to the working state before entering the sleep state.

In a second aspect, an embodiment of the present application discloses a method for updating a basic input output system of a computing device, including: the basic input output system sends a sleep instruction obtained from the basic input output system update program to the The operating system of the computing device, the hibernation instruction is used to instruct the operating system to enter the hibernation state; the basic input output system is restarted; the basic input output system obtains an update file of the basic input output system; the basic input output system Perform the update of the basic input output system based on the obtained update file.

In an implementation of the above second aspect, the basic input output system that completes the basic input output system update based on the acquired update file includes: the basic input output system writes the update file into the basic of the computing device In the input output system chip; the basic input output system restarts the central processing unit of the computing device to load the update file in the basic input output system chip into the memory of the computing device.

In a third aspect, an embodiment of the present application discloses a method for updating a basic input output system of a computing device, including: the embedded controller of the computing device detects that the power state of the central processing unit of the computing device is dormant State; the embedded controller resets the central processing unit to restart the basic input output system of the computing device to update the basic input output system.

In an implementation of the foregoing third aspect, resetting the central processing unit by the embedded controller includes:

The embedded controller resets the central processing unit when the wake-up flag bit is acquired.

In an implementation of the foregoing third aspect, the foregoing method further includes:

The embedded controller detects that the basic input output system writes the update file of the basic input output system into the basic input output system chip of the computing device; the embedded controller resets the computing device To write the update file into the memory of the computing device.

In a fourth aspect, an embodiment of the present application discloses a readable medium of a computing device, and an instruction is stored on the readable medium. When the instruction is executed on the computing device, the computing device executes the first or second The method described in the aspect.

In a fifth aspect, an embodiment of the present application discloses a computing device, which includes: a memory and a controller;

Wherein, the memory is used to store instructions executed by one or more controllers of the computing device;

The controller includes a central processing unit and an embedded controller, and is used to execute the method described in the first or second aspect.

Description of the drawings

Fig. 1 is a schematic structural diagram of a computer 100 according to an embodiment of the present application.

FIG. 2 is a BIOS update control system 200 according to an embodiment of the present application.

Fig. 3 is a flowchart of a BIOS update method according to an embodiment of the present application.

Fig. 4(a) is a diagram of the operating system display interface before BIOS update according to an embodiment of the present application.

Fig. 4(b) is an operating system display interface diagram after BIOS update according to an embodiment of the present application.

Fig. 5 is a schematic diagram of an example computing device according to an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions, and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

The terms commonly used by those skilled in the art will be used to describe various aspects of the illustrative embodiments to convey the essence of their work to others skilled in the art. However, it is obvious to those skilled in the art to implement some alternative embodiments using the features described in part. For the purpose of explanation, specific numbers and configurations are set forth for a more thorough understanding of the illustrative embodiments. However, it is obvious to those skilled in the art that alternative embodiments can be implemented without specific details. In some other cases, some well-known features are omitted or simplified herein to avoid obscuring the illustrative embodiments of the present application. It should be noted that in this specification, similar reference numerals and letters indicate similar items in the following drawings.

In various electronic devices such as computers, BIOS is a very important underlying firmware. BIOS iterations and updates can better solve product problems, such as CPU and other hardware security vulnerabilities and product design issues, thereby enhancing user experience. However, the BIOS update usually requires the system to restart, causing the current operation of the system to be unable to be saved. Based on this situation, the embodiment of the present application provides a solution that can save the current operation while updating the BIOS.

Illustrative embodiments of this application include but are not limited to BIOS update methods, devices, media, devices, and systems.

The embodiments of the present application can be applied to various electronic devices with embedded controllers (Embedded Controller, EC), for example, personal computers, notebook computers, desktop computers, handheld or laptop computers, tablet computers, portable games Machine, server, etc.

Hereinafter, taking the computer 100 as an example, a schematic diagram of the structure of an electronic device according to an embodiment of the present application is introduced in conjunction with FIG. 1.

As shown in FIG. 1, the computer 100 may include a main processor 110, a memory 120, an input device 130, an embedded controller 140, a graphics card 150, a display screen 151, a power supply 160, a sensor 170, an audio module 180, and the like.

It can be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the computer 100. In other embodiments of the present application, the computer 100 may include more or fewer components than shown, or combine certain components, or split certain components, or different component arrangements and/or different architectures. The illustrated components can be implemented in hardware, software, or a combination of software and hardware.

The main processor 110 is the control center of the computer 100. It uses various interfaces and lines to connect various parts of the entire computer 100, and executes various functions and functions of the computer 100 by running or executing software programs and/or data stored in the memory 120. Data processing, so as to control the computer 100 as a whole. For example, the main processor 110 may perform related operations performed by the CPU 222 described later in conjunction with FIG. 2 and FIG. 3 to implement the functions provided by the embodiments of the present application.

The main processor 110 may include one or more processing units, where different processing units may be independent devices, or may be integrated in one or more processors. A memory may also be provided in the main processor 110 to store instructions and data. In some embodiments, the memory in the main processor 110 is a cache memory. The memory can store instructions or data that have just been used or recycled by the main processor 110. If the main processor 110 needs to use the instruction or data again, it can be directly called from the memory. Repeated accesses are avoided, the waiting time of the main processor 110 is reduced, and the efficiency of the system is improved.

The memory 120 may include any suitable non-volatile memory and/or any suitable non-volatile storage device, such as flash memory, hard disk drive (HDD), solid-state drive (SSD) , Compact disk (CD) drive, and/or digital versatile disk (DVD) drive, etc. The memory 120 may be used to store computer executable program code, where the executable program code includes instructions. According to some embodiments of the present application, the memory 120 may include a storage program area and a storage data area. The storage program area can store an operating system, an application program required for at least one function (for example, a function for controlling the computer 100 to enter a sleep state, a function for waking up the computer 100, etc.). The data storage area can store data (such as audio data, image data, etc.) created during the use of the computer 100. The main processor 110 executes various functional applications and data processing of the computer 100 by running instructions stored in the memory 120 and/or instructions stored in a memory provided in the processor.

The input device 130 may be used to receive inputted digital information, character information, or contact touch operations/non-contact gestures, and generate signal inputs related to user settings and function control of the computer 100.

Specifically, according to some embodiments of the present application, the input device 130 may include a touch panel 131, a keyboard 132, and a mouse 133. The touch panel 131 can be used to collect the user's touch operations on or near it (for example, the user's operation on the touch panel 131 with fingers, stylus, or any other suitable object or accessory), and according to a preset program Drive the corresponding connection device. Characters, numbers, punctuation marks, etc. can be input into the computer 100 through the keyboard 132, and commands can also be issued to the computer 100 through function keys on the keyboard 132. The mouse 133 can position the cursor on the current display screen 151, and operate the screen element at the position where the cursor passes through the button and scroll wheel device, triggering the computer 100 to execute the corresponding command.

According to some embodiments of the present application, the computer 100 may also include other input devices, and other input devices may include, but are not limited to, any one of function keys (such as volume control buttons, switch buttons, etc.), trackball, light pen, joystick, etc. Kind or more.

Embedded Controller (EC) 140 is a control system used to perform designated independent control functions and has a complex data processing capability. When the system is turned on, EC 140 controls the timing of most important signals. For example, in the following embodiments of this application, the EC 140 activates the CPU 222 to wake up the BIOS to perform BIOS update.

The display screen 151 may be used to display information input by the user or information provided to the user, for example, various menu interfaces of the computer 100 and the like. The display screen 151 includes a display panel. The display panel can use liquid crystal display (LCD), organic light-emitting diode (OLED), active matrix organic light-emitting diode or active-matrix organic light-emitting diode (active-matrix organic light-emitting diode). AMOLED, flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, quantum dot light-emitting diode (QLED), etc. Optionally, the display screen 151 may be configured in the form of a liquid crystal display (LCD) or an organic light-emitting diode (OLED). In some embodiments, a part of the touch panel 131 may be integrated with the display screen 151 to form a touch display screen.

The graphics card 150 may include a graphics processing unit (GPU) or a video processing unit (Video Processing Unit, VPU), which is used to convert the digital signal input into the computer 100 into an analog signal, and make the display screen 151 convert When the analog signal is displayed, the graphics card 150 also has image processing capabilities, and the processed image is displayed on the display screen 151. The graphics card 150 may be integrated on the motherboard of the computer 100, or may be independent of the motherboard of the computer 100.

The power supply 160 is used to supply power to other modules, and the power supply 160 may include a charging management module and a power management module. The charging management module is used to receive charging input from the charger. Among them, the charger can be a wireless charger or a wired charger. While the charging management module charges the battery, it can also supply power to the electronic device through the power management module. The power management module is used to receive input from the battery and/or the charge management module, and supply power to each module in the computer 100. The power management module can also be used to monitor battery capacity, battery cycle times, battery health status (leakage, impedance) and other parameters.

The computer 100 may include one or more sensors 170 for sensing various information and transforming the sensed information into electrical signals or other required forms of information output according to a certain rule. In the embodiment of the present application, the sensor 170 may include various types of sensors, such as an image sensor, a brightness sensor, a light sensor, a GPS sensor, an infrared sensor, and so on.

The computer 100 can implement audio functions through the audio module 180, the speaker 181, the microphone 182, the earphone interface 183, and the main processor 110. For example, music playback, recording, etc.

The audio module 180 is used to convert digital audio information into an analog audio signal for output, and is also used to convert an analog audio input into a digital audio signal. The audio module 180 can also be used to encode and decode audio signals. In some embodiments, the audio module 180 may be disposed in the main processor 110, or part of the functional modules of the audio module 180 may be disposed in the main processor 110.

The speaker 181 is used to convert audio electrical signals into sound signals. The computer 100 can output sound through the speaker 181.

The microphone 182 is used to pick up sound signals and convert the sound signals into electrical signals. The computer 100 may be provided with at least one microphone 182. In some other embodiments, the computer 100 can be provided with two microphones 182, which can implement noise reduction functions in addition to collecting sound signals. In other embodiments, the computer 100 may also be provided with three, four or more microphones 182 to collect sound signals, reduce noise, identify sound sources, and realize directional recording functions.

The earphone interface 183 is used to connect wired earphones. The earphone interface 183 may be a USB interface, a 3.5mm open mobile terminal platform (OMTP) standard interface, a cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface, and so on.

In addition, the computer 100 may also include a radio frequency (RF) circuit 191 for network communication with wireless network devices, and may also include a WIFI module 192 for WIFI communication with other devices, and to obtain data transmitted by other devices, etc. .

The following describes the BIOS update control system 200 according to an embodiment of the present application in conjunction with FIG. 2. The update control system 200 can be implemented in the computer 100 as shown in FIG. 1.

The update control system 200 may include a software (SW) part 210 and a hardware (HW) part 220. The software 210 part includes a basic input output system (Basic Input Output System, BIOS) 211 and an operating system (Operating System, OS). 212. The hardware 220 part may include a hard disk 221, a central processing unit (CPU) 222, a BIOS chip 223, and an embedded controller (EC) 224.

OS 212 is a computer program that manages hardware and software resources in a computer. It is mainly used to handle basic tasks such as managing and configuring memory, determining the priority of system resource supply and demand, controlling input devices and output devices, operating networks, and managing file systems. The OS 212 can schedule various resources of the computer system, including software and hardware equipment, data, information, etc., and also provide an interface for the user to interact with the computer 100. Common operating systems include but are not limited to: Windows, Android, IOS, etc. It can be understood that, in the embodiment of the present application, the OS 212 is decoupled from the EC 224. After the OS 212 sleeps, the EC 224 continues to work and performs functions such as waking up the CPU 222.

BIOS 211 is a set of programs solidified in the BIOS chip 223 on the computer motherboard, including the most important basic input and output programs of the computer, the power-on self-check program, and the system self-starting program. It is used to directly control the input and output devices in the computer system. Perform hardware-level control to provide a basis for establishing connections between other software programs and hardware devices. BIOS 211 is the first program to be executed after the computer is powered on. It completes functions such as initial setting and testing of various hardware devices of the system to ensure that the system can work normally. After the BIOS 211 initializes the hardware resources, the OS 212 will run to perform various services through the initialized hardware resources.

Specifically, from the power-on of the host computer of the computer 100 to the loading of the bootloader (bootloader), that is, the BIOS 211 completes the startup task and enters the idle state. The BIOS 211 mainly goes through three stages: Pown On (the power phase is not activated), and POST (Power on). self tes t, power-on self-test) and load the bootloader. in:

1) The main task of the Pown On stage is to verify whether the content in CMOS (Complementary Metal Oxide Semiconductor) is correct, and to check the status of some hardware on the host to determine the next self-check.

2) The POST (power on self test) phase checks whether some key devices such as memory and graphics card can work normally, and provides a simple memory test. As long as the test is no problem, the basic information of the hardware is displayed on the screen. Generally, the basic process of BIOS 211 in the POST phase is as follows: BIOS 211 searches for the BIOS code of the graphics card, and then calls its initialization code. The graphics card’s BIOS completes the initialization of the graphics card, and then the screen can display information; then, BIOS 211 calls other found The BIOS code of the device to complete the initialization of the corresponding device, and so on. After checking other devices, the BIOS 211 will display its own startup screen, and then check the type and operating frequency of the CPU 222, the memory capacity of the computer, etc.; then the BIOS 211 starts to test and configure some standard hardware devices installed in the system, such as hard drives, Optical drive, interface, etc., and then BIOS 211 checks and configures the plug-and-play devices in the computer system. Generally speaking, all the devices that need to be used are activated during the POST phase during and after the startup.

3) In the stage of loading bootloader, the way for BIOS to retreat behind the scenes is to transfer the master control of loading the OS to the MBR (Master Boot Record) of the hard disk, that is, the physical sector of the hard disk 0 cylinder 0 surface 1 sector The above content allows the bootloader hidden here to bring the pointer to the core of the system.

In addition, it can be understood that, in some embodiments of the present application, the BIOS 211 exits after the OS 212 enters the sleep state, and can be restarted after the CPU 222 is reset. The details will be introduced below.

The hard disk 221 is one of the most important memories in a computer. Most of the application programs and data required for the computer to run normally are stored on the hard disk 221. The hard disk 221 may include, but is not limited to: a solid state drive (Solid State Drive, SSD for short) and a mechanical hard disk drive (Hard Disk Drive, HDD), etc. When updating the BIOS 211, the BIOS update tool can initially store the binary (bin) file of the BIOS in the hard disk 221. It should be understood that in the embodiments of the present application, the storage location of the BIOS bin file is not limited to the hard disk 221. In some embodiments, the BIOS bin file (ie, BIOS update file) can be stored in various internal memories or In an accessible external storage device, for example, it can be stored in a mobile storage device such as a U disk.

The CPU 222 is a core hardware unit that controls and allocates all hardware resources of the computer 100 and executes general operations. As the computing and control core of the computer 100, the CPU 222 is the final execution unit for information processing and program operation. The operations of all software layers 210 in the computer system will eventually be mapped to the operations of the CPU 222 through the instruction set. In some embodiments of the present application, the BIOS update program sends a sleep instruction to the CPU 222 through the BIOS 211, and yes, the OS 212 enters the sleep state.

The BIOS chip 223 is a non-volatile memory provided on the computer motherboard and used to store the aforementioned BIOS 211, which can keep data without loss without power supply. The BIOS chip 223 may be a read-only memory (Read-Only Memory, ROM) chip or a flash memory (Flash) chip. The BIOS chip is generally a FlashROM (flash-erase read-only programmer) chip. At present, the capacity of FlashROM chips is generally 1M or 2M up to 8M, and is roughly divided into 28 and 29 series. The FlashROM chip of the 28 series is designed with dual voltage, it can be read under the condition of 5V voltage, and the voltage of 12V must be provided for writing. The motherboard of this chip needs to open the case and change the jumper setting when upgrading. The 29 series of FlashROM chips are relatively simple. Because of their single-voltage design, both read and write use 5V voltage, so the firmware read and write operations can be completed with only software.

Embedded Controller (EC) 224 is a control system used to perform designated independent control functions and have complex data processing capabilities. As a single processor, EC 224 can be implemented by a single-chip microcomputer, which plays a global management role for the entire system before and during the boot process. The EC 224 uses the logic program (ie EC code) stored in the flash to perform the control function. In some embodiments, the EC 224 itself can integrate a certain capacity of Flash, etc. to store the EC code. In some embodiments, the EC 224 It is also possible not to integrate Flash, but to store the EC code in the BIOS chip 223.

When the system is turned on, EC 224 controls the timing of most important signals. In a computer, as long as it is powered on, the EC 224 will always be turned on, regardless of whether the computer is on or off, unless the battery and adapter are completely removed. In the shutdown state, the EC 224 keeps running and waits for the user's startup information. After booting, EC 224 will perform keyboard, fan, charging and discharging, indicator lights and other functions to control or support work, and is responsible for the tasks of keyboard, mouse, battery power supply, and temperature control detection. In some embodiments, EC 224 is also used to control the standby, hibernation and other states of the system.

The following describes the process of using the BIOS update control system 200 shown in FIG. 2 to perform a BIOS update with reference to FIG. 3.

First, S301: When the OS 212 is running, use the BIOS update tool to store the new BIOS bin file to the specified location of the computer's hard disk. The specified location is determined by the storage path of the BIOS bin file, and the file storage path can be updated by the BIOS The default settings of the tool can also be customized by the user. For example, the new BIOS bin file may be stored in the EFI system partition (ESP) of the hard disk 221, so that the BIOS 211 can be directly accessed without a driver. It can be understood that the new BIOS bin file may also be stored in other partitions of the hard disk 221 or other storage devices of the computer 100.

S302: Set the update flag bit (update flag) through the BIOS 211 update tool. The update flag can be used in the POST process of the BIOS 211 to make the BIOS 211 self-check whether it needs to be updated.

S303-S304: Use the BIOS 211 update tool to notify the BIOS to send a hibernation instruction to the CPU 222, so that the computer enters the hibernation state. Among them, when the OS 212 enters the sleep state, the BIOS 211 also exits.

For example, as shown in Figure 4a, when the computer system enters the dormant state, the display interface of the computer 100 can be used to remind the user that the computer is about to update the BIOS and the computer system is about to enter the dormant state. After the user clicks to confirm, the computer system enters Sleep state. If the user chooses to update later, the user can be reminded to update after a predetermined time. Or you can also set the options for the user to update the time, such as choosing to update after 4 hours, choosing to update at night, and so on.

According to some embodiments of the present application, the hibernation instruction sent by the BIOS 211 to the CPU 222 may be an S4 hibernation instruction to control the computer system to enter the S4 state, which is also called the Suspend to Disk (STD) state. In the S4 state, the power of the CPU 222 is turned off, and the main power of the system is turned off, but the hard disk is still powered and can be awakened, the relevant data in operation is saved to the hard disk, and then all components stop working. In the STD state, the user's current operation will not be lost. After that, the system can be re-awakened by pressing the power button and other operations. After the system wakes up, the relevant data can be read from the hard disk and restored to the working state before the STD.

According to other embodiments of the present application, the hibernation instruction sent by the BIOS 211 to the CPU 222 may also be an S3 hibernation instruction to control the computer system to enter the S3 state, which is also called the Suspend to RAM (STR) state. In the STR state, the power of the CPU 222 is also turned off, and the working state data before the system enters the STR is stored in the memory. In the STR state, the power supply continues to supply power to the most necessary components such as memory to ensure that data is not lost, while other components are turned off. Similarly, afterwards, the system can be re-woken up by pressing the power button and other operations. After the system is woken up, data can be read from the memory immediately and restored to the previous working state of STR. Due to the extremely fast read and write speed of the memory, the time to enter and leave the STR state is shorter than the time to enter and leave the STD state. The system entering S3 or S4 sleep can be realized through Advanced Configuration and Power Interface (ACPI).

In addition, it can be understood that in other embodiments, the BIOS 211 may also send a hibernation instruction to the CPU 222 through other systems coexisting on the computer 100. For example, the BIOS 211 may send a hibernation instruction to the CPU through the OS 212.

S305: BIOS 211 configures the wake-up flag (that is, wake-up flag bit) for EC 224. According to some embodiments of this application, the operation of BIOS 211 to configure the wake-up flag can be performed at the same time when BIOS 211 sends a sleep command to CPU 222, or in BIOS 211 is performed before or after the operation of sending the sleep instruction to the CPU 222, but it must be ensured that the operation of the BIOS 211 to configure the wake-up flag for the EC 224 is completed when the BIOS 211 has the operating authority, that is, before the CPU 222 sleeps. Setting the wake-up flag before the CPU 222 sleeps can ensure that after the computer system enters sleep, the EC 224 can start the CPU 222 according to the obtained wake-up flag, thereby waking up the BIOS 211 for BIOS update.

Under normal circumstances, after the BIOS 211 sends a sleep instruction to the CPU 222, the OS 212 and the BIOS 211 will enter the sleep state together. In order to enable the BIOS to be awakened and updated, the embodiment of the present application sends the sleep instruction to the CPU 222 at the same time. Configure the wake-up flag for EC 224. The wake-up flag is set at a location accessible to the EC 224, so that the EC 224 can wake up the BIOS 211 after reading the wake-up flag.

S306: Use EC 224 to wake up BIOS 211 and clear the wake-up flag.

Since the EC 224 is always on when the power is on, even if the computer enters the dormant state, the EC 224 keeps running and can access the previously set wake-up flag. In the embodiment of the present application, the EC 224 is configured to perform the operation of resetting the CPU 222 after reading the wake-up flag. After the CPU 222 is reset, the BIOS 211 is turned on, and the wake-up flag is cleared after the BIOS 211 is turned on. The clearing operation can be executed by the EC after accessing the wake-up flag; it can also be executed by the BIOS 211. For example, the BIOS 211 sets the wake-up flag to be cleared when the wake-up flag is configured when the wake-up flag is configured.

S307-S308: After the BIOS 211 is turned on, the startup task is executed, and the BIOS update operation is executed when the update flag is detected during the POST phase (for example, the update flag is detected as 1). As mentioned above, the BIOS 211 will enter the POST phase when it executes the startup task. When the BIOS 211 detects that the update flag is 1 in the POST phase, it will execute the BIOS update operation and store the BIOS bin originally stored in the hard disk 221. The file is written into the BIOS chip 223, and the update flag is cleared.

Specifically, after the BIOS 211 detects that the update flag is 1 in the POST phase, the BIOS 211 can read the new BIOS file from the specified location of the hard disk 221, for example, read the new BIOS file from the ESP mentioned above, and then update the new BIOS file. BIOS file verification and authentication (such as verifying whether the new BIOS file carries viruses, checking the integrity of the new BIOS file, etc.), confirming that the new BIOS file that needs to be upgraded is stored in the ESP, and checking whether the current upgrade is available condition. According to some embodiments of the present application, the upgrade conditions may include whether the current power of the computer equipment meets the upgrade requirements, etc. The upgrade conditions can be customized and set in this application, which is not limited here.

It is confirmed in the BIOS 211 that the new BIOS file that needs to be upgraded is stored in the ESP, and after the current computer equipment meets the upgrade conditions, the preparation for the BIOS update is started, and the new BIOS file is written into the BIOS chip 223. After completing the writing of the new BIOS file, a read and write check may be performed. A successful check indicates that the BIOS flashing is successful, and if the check fails, it can be rewritten.

After the BIOS 211 writes the new BIOS file into the BIOS chip 223, the BIOS 211 sends a message to the EC 224 that the update file is successfully written to the BIOS chip 223, and the BIOS 211 causes the CPU 222 to restart, and the CPU 222 resets the BIOS chip 223 after restarting. The BIOS file is loaded into the memory of the computer 100. So far, the BIOS 211 is updated.

In addition, it can be understood that in other embodiments, the EC 224 may also instruct the CPU to restart, that is, after the BIOS 211 writes the new BIOS file to the BIOS chip 223, the BIOS 211 sends the update file to the EC 224 to successfully write the BIOS. The message of the chip 223, the EC 224 causes the CPU 222 to restart. After the CPU 222 restarts, the new BIOS file in the BIOS chip 223 is loaded into the memory of the computer 100. At this point, the BIOS 211 is updated.

S309: After the BIOS211 update is completed and successfully started, OS 212 wakes up from the sleep state, enters the S0 state, reads operating data from the memory or hard disk and returns to the working state before sleep, and the system related operations before the BIOS update are saved. For example, as shown in Figure 4b, after the BIOS 211 update is completed, the OS 212 enters the S0 state and saves related operations before the update. Among them, the S0 state of the OS 212 is the normal working state of the OS 212. At this time, the hardware devices of the computer 100 are basically in the on state.

The embodiment of the present application realizes the update of the BIOS 211 through the interactive design of the OS 212, the BIOS 211, and the EC 224. During the BIOS update process, the BIOS 211 is decoupled from the OS 212, so that the OS 212 remains in a dormant state, and the BIOS 211 initiates the update. During the BIOS 211 update process, the OS 212 is in the S3 or S4 dormant state, so that the current operating state and files of the OS system can be saved, so that the current system operations are not lost while the BIOS is updated to meet the idle time of the BIOS 211 Automatic update and mandatory update requirements.

An example computing device 500 according to some embodiments of the present application will be described below in conjunction with FIG. 5. In the embodiment of the present application, the computing device 500 may be or may include the update control system 200 shown in FIG. 2, and, in various embodiments, the computing device 500 may have more or fewer components and/or Different architectures.

In one embodiment, the computing device 500 may include one or more processors 504, a system control logic 508 connected to at least one of the processors 504, a system memory 512 connected to the system control logic 508, and a system control logic 508 The memory 516 (for example, a non-volatile memory (NVM)) is connected, and the network interface 520 is connected to the system control logic 508.

The processor 504 may include one or more single-core or multi-core processors. The processor 504 may include any combination of a general-purpose processor and a special-purpose processor (for example, a graphics processor, an application processor, a baseband processor, etc.). In some cases, the processor 504 may be configured to perform various operations performed by the CPU 222 or the EC 224 described above with reference to FIGS. 2 to 3.

The system control logic 508 for a certain embodiment may include any suitable interface controller to provide any suitable interface to at least one of the processors 504 and/or any suitable device or component in communication with the system control logic 508 . The system control logic 508 for a certain embodiment may include one or more memory controllers to provide an interface to the system memory 512. The system memory 512 may be used to load and store data and/or instructions. For example, for the computing device 500, the system memory 512 used in a certain embodiment may include any suitable volatile memory, such as a suitable random access memory ( random-access memory (RAM) or dynamic random access memory (dynamic random access memory, DRAM).

The memory 516 may include one or more tangible, non-transitory computer-readable media for storing data and/or instructions. For example, the memory 516 may include any suitable non-volatile memory and/or any suitable non-volatile storage device, such as flash memory, hard disk drive (HDD), and solid-state drive (SSD). ), compact disk (CD) drives, and/or digital versatile disk (DVD) drives, etc.

The memory 516 may include a part of storage resources on the device on which the computing device 500 is installed, or it may be accessed by the device, but not necessarily a part of the device. For example, the storage 516 can be accessed through the network via the network interface 520.

In particular, the system memory 512 and the memory 516 may include: temporary and permanent copies of the instructions 524, respectively. The instructions 524 may include instructions that, when executed by at least one of the processors 504, cause the computing device 500 to implement the method described above. In various embodiments, instructions 524 or hardware, firmware, and/or software components thereof may additionally/alternatively be placed in system control logic 508, network interface 520, and/or processor 504.

The network interface 520 may include a transceiver, which is used to provide a radio interface for the computing device 500 to communicate with any other suitable devices (such as a front-end module, an antenna, etc.) through one or more networks. In various embodiments, the network interface 520 may be integrated with other components of the computing device 500. For example, the network interface may include the processor of the processor 504, the memory of the system memory 512, the memory of the memory 516, and/or a firmware device (not shown) with instructions, the instructions being generated by at least one of the processors 504 When executed, instructions that cause the computing device 500 to implement the method described in FIG. 3.

The network interface 520 may further include any suitable hardware and/or firmware to provide a multiple input multiple output radio interface. For example, the network interface 520 used in a certain embodiment may be a network adapter, a wireless network adapter, a telephone modem, and/or a wireless modem.

For an embodiment, at least one of the processors 504 may be packaged with the logic of one or more controllers for the system control logic 508. For one embodiment, at least one of the processors 504 may be packaged with the logic of one or more controllers for the system control logic 508 to form a system in package (SiP). For one embodiment, at least one of the processors 504 may be integrated with the logic of one or more controllers for the system control logic 508. For one embodiment, at least one of the processors 504 may be integrated with the logic of one or more controllers for the system control logic 508 to form a system on chip (SoC).

The computing device 500 may further include: an input/output (I/O) device 532. The I/O device 532 may include a user interface designed to enable a user to interact with the computing device 500; a peripheral component interface designed to enable peripheral components to also interact with the computing device 500; and/or a user interface designed to enable A sensor that determines environmental conditions and/or location information related to the computing device 500, etc.

The various embodiments disclosed in this application may be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system. The programmable system can include at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements). ), at least one input device and at least one output device.

Program codes can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner.

The program code in this application can be implemented in a high-level programming language or an object-oriented programming language to communicate with the processing system. When needed, assembly language or machine language can also be used to implement the program code. In fact, the mechanism described in this application is not limited to the scope of any particular programming language. In either case, the language can be a compiled language or an interpreted language.

In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented in the form of instructions or programs carried or stored on one or more transient or non-transitory machine-readable (for example, computer-readable) storage media, which may be implemented by one or more The processor, etc. read and execute. When the instructions or programs are executed by the machine, the machine can execute the aforementioned various methods. For example, the instructions can be distributed via a network or other computer-readable media. Therefore, a machine-readable medium may include, but is not limited to, any mechanism for storing or transmitting information in a form readable by a machine (for example, a computer), such as floppy disks, optical disks, compact disk read-only memories (CD-ROMs), and magnetic disks. Optical disc, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), magnetic or optical card, or for Flash memory or tangible machine-readable memory that transmits network information through electricity, light, sound, or other forms of signals (for example, carrier waves, infrared signals, digital signals, etc.). Therefore, the machine-readable medium includes any form of machine-readable medium suitable for storing or transmitting electronic instructions or machine (for example, computer) readable information.

Therefore, the embodiments of the present application also include non-transitory tangible machine-readable media containing instructions or design data, such as hardware description language (HDL), which defines the structures, circuits, devices, and processes described herein. And/or system characteristics. These embodiments are also called program products.

It should be understood that although the terms "first", "second", etc. may be used herein to describe various features, these features should not be limited by these terms. These terms are used only for distinction, and cannot be understood as indicating or implying relative importance. For example, without departing from the scope of the exemplary embodiment, the first feature may be referred to as the second feature, and similarly the second feature may be referred to as the first feature.

In addition, various operations will be described as multiple operations separated from each other in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be construed to imply that these operations must rely on the order of description, many of which Operations can be performed in parallel, concurrently, or simultaneously. In addition, the order of operations can also be rearranged. When the described operations are completed, the processing may be terminated, but there may also be additional operations not included in the drawings. The processing may correspond to methods, functions, procedures, subroutines, subroutines, and so on.

References in the specification to "one embodiment", "an embodiment", "an illustrative embodiment", etc. indicate that the described embodiment may include specific features, structures, or properties, but each embodiment may or may not necessarily include specific The characteristics, structure or properties of. Moreover, these phrases are not necessarily referring to the same embodiment. In addition, when specific features are described in conjunction with specific embodiments, the knowledge of those skilled in the art can influence the combination of these features with other embodiments, regardless of whether these embodiments are explicitly described.

Unless the context dictates otherwise, the terms "comprising", "having" and "including" are synonymous. The phrase "A/B" means "A or B". The phrase "A and/or B" means "(A), (B) or (A and B)".

As used herein, the term "module" can refer to, as a part of it, or include: memory (shared, dedicated or group) for running one or more software or firmware programs, application specific integrated circuit (ASIC), Electronic circuits and/or processors (shared, dedicated or group), combinational logic circuits, and/or other suitable components that provide the described functions.

In the drawings, some structural or method features may be shown in a specific arrangement and/or order. However, it should be understood that such a specific arrangement and/or ordering is not necessary. Rather, in some embodiments, these features may be described in a different manner and/or order than shown in the illustrative drawings. In addition, the structural or method features included in a particular drawing do not mean that all embodiments need to include such features. In some embodiments, these features may not be included, or these features may be combined with other features.

The embodiments of this application are described in detail above in conjunction with the drawings, but the use of the technical solutions of this application is not limited to the various applications mentioned in the embodiments of this patent. Various structures and modifications can be easily referred to the technical solutions of this application. To achieve the various beneficial effects mentioned in this article. Within the scope of knowledge possessed by those of ordinary skill in the art, various changes made without departing from the purpose of this application shall all belong to the scope of the patent coverage of this application.

Claims

A method for updating a basic input output system of a computing device, which is characterized in that it comprises:

The operating system of the computing device enters a sleep state;

After the operating system enters the sleep state, restart the basic input output system;

The basic input output system obtains the update file of the basic input output system, and performs the update of the basic input output system based on the obtained update file;

After the basic input output system is updated, the operating system wakes up from the sleep state.
The update method according to claim 1, wherein the operating system of the computing device enters a dormant state comprises:

The update program of the basic input output system sends a sleep instruction to the operating system, and the operating system enters a sleep state.
The update method according to claim 2, wherein after the operating system enters a sleep state, restarting the basic input output system comprises:

After the operating system enters the sleep state, the embedded controller of the computing device resets the central processing unit of the computing device to restart the basic input output system.
The update method according to claim 3, further comprising:

Before the operating system enters the sleep state, the basic input output system sets a wake-up flag bit for the embedded controller, wherein the embedded controller resets the wake-up flag bit after acquiring the wake-up flag bit. CPU.
The update method according to claim 1, further comprising:

The embedded controller deletes the wake-up flag bit after resetting the central processing unit.
The update method according to claim 1, wherein the basic input output system performs the update of the basic input output system in the following manner:

The basic input output system writes the update file into the basic input output system chip of the computing device;

The basic input output system resets the central processing unit of the computing device to load the update file in the basic input output system chip into the memory of the computing device.
The update method according to claim 1, wherein after the basic input output system is updated, the operating system waking up from the sleep state comprises:

Reading the relevant data before the operating system enters the hibernation state from the hard disk of the computing device;

Based on the acquired relevant data, the operating system is returned to the working state before entering the sleep state.
A method for updating a basic input output system of a computing device, which is characterized in that it comprises:

The basic input output system sends the hibernation instruction obtained from the update program of the basic input output system to the operating system of the computing device, where the hibernation instruction is used to instruct the operating system to enter a hibernation state;

The basic input output system restarts;

The basic input output system obtains an update file of the basic input output system;

The basic input output system performs the update of the basic input output system based on the obtained update file.
The update method according to claim 8, wherein the completion of the update of the basic input output system by the basic input output system based on the obtained update file comprises:

The basic input output system writes the update file into the basic input output system chip of the computing device;

The basic input output system restarts the central processing unit of the computing device to load the update file in the basic input output system chip into the memory of the computing device.
A method for updating a basic input output system of a computing device, which is characterized in that it comprises:

The embedded controller of the computing device detects that the power state of the central processing unit of the computing device is a sleep state;

The embedded controller resets the central processing unit to restart the basic input output system of the computing device to update the basic input output system.
The method of claim 10, wherein the embedded controller resetting the central processing unit comprises:

The embedded controller resets the central processing unit when the wake-up flag bit is acquired.
The method according to claim 10 or 11, further comprising:

The embedded controller detects that the basic input output system writes the update file of the basic input output system into the basic input output system chip of the computing device;

The embedded controller resets the central processing unit of the computing device to write the update file into the memory of the computing device.
A readable medium for a computing device, characterized in that an instruction is stored on the readable medium, and when the instruction is executed on a computing device, the computing device executes the method according to any one of claims 1 to 12 .
A computing device, characterized by comprising: a memory and a controller;

Wherein, the memory is used to store instructions executed by one or more controllers of the computing device;

The controller includes a central processing unit and an embedded controller, and is configured to execute the method according to any one of claims 1-12.