WO2021217529A1

WO2021217529A1 - Method and system for inter-process communication

Info

Publication number: WO2021217529A1
Application number: PCT/CN2020/087917
Authority: WO
Inventors: 张建永
Original assignee: 华为技术有限公司
Priority date: 2020-04-29
Filing date: 2020-04-29
Publication date: 2021-11-04
Also published as: CN113939805A

Abstract

A method and a system for inter-process communication (IPC). Said system comprises: a processor core, IPC engine hardware and a memory. The processor core is used to configure, when the IPC engine hardware is initialized, a part of memory space of the memory to be a shared memory space, so as to save data to be transmitted required for IPC, and establish a page table. The processor core runs a client caller, and sends a calling instruction to the IPC engine hardware, the calling instruction comprising the identifier of a server callee and a virtual address of said data, and a physical address of said data being located in the shared memory space. The IPC engine hardware is used to instruct the processor core to run the server callee. The processor core runs the server callee, and the server callee queries the page table according to the virtual address of said data to obtain said data to execute a service, and sends a return instruction to the IPC engine hardware. The IPC engine hardware is used to instruct the processor core to restore and run the client caller. Thus, the IPC delay can be reduced, improving the data transmission efficiency and improving the performance.

Description

Method and system for inter-process communication

Technical field

This application relates to the field of computer technology, and in particular to a method, related equipment and system for inter-process communication.

Background technique

Software systems, such as Linux, allocate and manage resources in units of processes. In user space, a process cannot directly access the resources of another process. However, in practical applications, multiple processes are usually used to jointly complete a task, which requires a communication mechanism between processes, that is, inter-process communication (IPC). IPC is a technology for transferring data or signals between at least two processes. A process is a unit by which a computing device allocates resources, and a process can run on the same computing device or different computing devices connected to the network. Each process corresponds to a part of independent system resources, isolated from each other, and through the IPC mechanism, different processes can access resources and coordinate work with each other.

Traditionally, Linux-based IPC mechanisms include, for example, pipe communication, signal communication, message queues, and sockets. Android (android) Linux-based kernel provides a further optimized IPC mechanism: IPC binder. Binder is a communication mechanism based on the client-server (Client-server, CS) mode. All clients obtain server-side services through a centralized binder driver.

The performance of IPC is a key factor that affects the overall performance of computing devices. For example, for Android, user space processes need to interact frequently with a large number of user space services, and the delay performance of IPC also directly affects user experience.

For example, referring to Figure 1, the core of the existing Binder mechanism is to run the Binder driver at the kernel layer. Because the kernel space in the system can share resources, the Binder driver has powerful cross-process access capabilities, and the Binder driver assumes the client The media role of IPC communication between the process (caller) of the (client) and the process (callee) of the server (server). The user mode caller process requests the kernel (kernel) service through the system call function "call()", and the caller process falls into the kernel mode to complete the context switch, that is, it needs to switch from the user mode to the kernel mode. Next, complete the copy of the IPC message data, copy the message data from the user space of the client to the kernel space, and the server as the data receiver shares data with the kernel, so there is no need to copy the data. Therefore, the entire IPC process only needs one memory copy to transfer the message data to the callee. Then, the kernel switches to the user-mode callee context to complete the service response, and finally returns by calling the function "reply()", and the kernel restores the state of the caller process.

In the above-mentioned Binder mechanism, on the one hand, the kernel needs to allocate execution time to complete the process of switching between the kernel state and user state of the process and the process context save/restore process, so that the CPU cycle occupied by the IPC process can be as long as 00 cycles, and the delay overhead is large. . On the other hand, a copy process is inevitably required in message data transmission, which affects the efficiency of data transmission. When some existing solutions try to overcome the above-mentioned shortcomings, it is often necessary to change the address access process of the memory management unit (MMU) in the existing standard, which is difficult to promote and apply in products that comply with the existing standard.

Summary of the invention

The present application provides a method, related equipment, and system for inter-process communication, which can reduce IPC delay, improve data transmission efficiency, and improve performance.

In the first aspect, this application provides a hardware system for inter-process communication IPC. The system includes a processor core, IPC engine hardware, and a memory. The processor core is used to initialize the IPC engine hardware. , Configure a part of the memory space in the memory as the shared memory space of the process, the shared memory space is used to store the to-be-transferred data required for inter-process communication; create a page according to the starting address and length of the shared memory space Table, the page table contains the virtual address to the physical address mapping relationship of the shared memory space; the processor core is also used to run a client process (such as caller), the client process needs to call the server process ( For example, when calling a service, send a first processor instruction (for example, ipccall described in the specification) to the IPC engine hardware. The first processor instruction is the call instruction of the client process to the service, so The call instruction includes the identifier of the server process and the virtual address of the data to be transferred; the physical address of the data to be transferred is located in the shared memory space; the IPC engine hardware is used to instruct the processor core according to the identifier Run the server process, and send the virtual address of the data to be transferred to the server process; the processor core is also used to run the server process, the server process according to the The virtual address of the transfer data queries the page table to obtain the data to be transferred to execute the service; and sends a second processor instruction (for example, ipcret described in the specification) to the IPC engine hardware, and the second processor The instruction is a return instruction of the server process; the IPC engine hardware is also used to, according to the second processor instruction, instruct the processor core to resume running the client process.

Among them, the attributes of the client process and the server process can be processes or threads.

It can be seen that the embodiment of the present application can transfer the context information storage, context switching and restoration, data transfer, etc. in the user state from time and space to a new physical entity (ie, IPC engine). As the medium of IPC, the IPC engine provides corresponding user mode commands ipccall and ipcret, so that the caller and callee can complete the context switch in the user mode without switching to the kernel mode, thereby satisfying the caller's service call and callee's callback. In order to interact with the process at the user mode level, the IPC engine can work in parallel with the kernel software, which greatly reduces the overall delay of the IPC process. In addition, in the embodiments of the present application, the IPC engine can be used to transfer data access rights, and only the virtual address of the data needs to be transferred to the callee, instead of the data itself, thereby avoiding copying of the data, and further Reduce the time delay of data copy, and improve the efficiency of data transmission.

In addition, during system initialization (IPC engine initialization), the operating system running on the processor core reserves (or configures) a part of the physical memory as a shared memory for caller and callee. That is to say, in the embodiment of the present application, the shared memory is fixedly reserved and allocated when the IPC engine is initialized, and this part of the shared memory is not in the page management page table of the kernel (for example, the kernel). This part of shared memory can be directly accessed by the IPC engine. The shared memory can be used to store data that needs to be transferred between processes during IPC communication. By reserving the shared memory, a dedicated page table (the page table containing the mapping relationship between virtual addresses and physical addresses) can be established to ensure that the data to be transferred always has corresponding physical pages, thereby avoiding page faults and improving system performance.

After the shared memory is allocated, when the callee is registered with the IPC engine, the callee can create the page table of the process and add it to the MMU according to the starting address and length (size) of the shared memory. The page table defines the segment globally The mapping relationship between the virtual address (VA) and the physical address (PA) of the shared memory, the implementation of the solution of the embodiment of this application can also realize that after the IPC engine is initialized, the operating system allocates the shared memory, and the callee initiates registration After that, the page table of this process is established and managed by MMU, so that the purpose of sharing memory between caller and callee is achieved, and changes to the existing MMU workflow are avoided, page faults are avoided, and the stability of IPC communication is ensured. Sex and safety.

Based on the first aspect, in a possible embodiment, the processor core is further configured to allocate a part of the shared memory space to the client when the client process needs to call the service of the server process Process to save the to-be-transferred data.

To implement the embodiment of this application, when the caller needs to call the callee service, the operating system allocates memory to the caller based on the shared memory, that is, allocates a part of the memory space in the shared memory to the caller to save the data to be transferred (msg), that is, the operating system In the shared memory, the caller is allocated a memory segment that stores the generation transfer data (msg). The mapping relationship between the virtual address of msg and the physical address in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU, so, In the subsequent IPC communication, after the msg VA is passed from the caller to the callee through the IPC engine, the callee can access the page table to obtain the data according to the VA, thereby achieving the purpose of sharing memory between the caller and the callee, and avoiding the need for existing The change of the MMU workflow to avoid the occurrence of page faults, and to ensure the stability and security of IPC communication.

Based on the first aspect, in a possible embodiment, before running the client process, the processor core is further configured to send registration information of the server process to the IPC engine hardware, where the registration information includes The identifier; the IPC engine hardware is also used to: receive the registration information; in response to the registration information, save the identifier and the server process entry address in the IPC engine hardware; the IPC engine The hardware is specifically used to: find the entry address according to the identifier; set the entry address to the program counter (PC) in the processor core; the processor core is also used to, according to the setting in the The entry address in the PC runs the server process.

Among them, the IPC engine hardware may include a callee register set, and the callee register set includes a set of registers for recording indication information of the context information of the callee. The callee register set is specifically used to record the entry addresses (callee entry addresses) of multiple callees, and each callee entry address corresponds to the context information of a callee. In an embodiment, the callee entry address includes an address pointer of a callee service function, and the service function may be a callback function (Callback function). The IPC engine can set the Program Counter (PC) in the CPU to the callee entry address, so that the CPU starts to execute the callee process context and run the callee to execute the corresponding service.

Further, the callee register set further includes a first address register and a counting register. The first address register is used to store the first address of the callee list. Specifically, it may be the first callee entry address in the callee list. The counting register is used to record the number of callee entry addresses (entry list size). Specifically, each time a list entry (ie, a callee entry address) is added to the callee list, the number of the count register records is increased by 1. In this way, through the callee register set, the entry address (callee entry address) of multiple callees can be recorded to the callee list according to the registration status of multiple callees. In a specific implementation, each list entry in the callee list can be configured to correspond to an index identification (ID). The index ID may be the process ID of the callee (ie callee ID), or the index ID may be one-to-one mapped with the process ID, and the index ID may be determined after the callee is registered with the IPC engine. In this way, it is convenient for the client process (caller) to perform IPC with one or more callees.

It can be seen that the IPC engine in the embodiments of this application can realize the preservation of context information, context switching, or data transmission in the user mode. These process cores are not aware (that is, the IPC process may not require the core to participate), which avoids the current situation. There is the disadvantage of frequent switching between user mode and kernel mode in the IPC mechanism (such as the binder mechanism), which separates the IPC process of the process from the kernel, thereby freeing up a large amount of CPU software execution time, thereby greatly reducing the overall delay of the IPC process.

Based on the first aspect, in a possible embodiment, the IPC engine hardware is further configured to, after receiving the call instruction, query the status register in the processor core to obtain the call of the client process Stack address, and save the call stack address of the client process in the IPC engine hardware; the IPC engine hardware is specifically used to call out the call stack address according to the second processor instruction and instruct The processor core resumes running the client process according to the call stack address.

Specifically, the IPC engine hardware may include a link register, and the link register is used to store the entry address of the current caller, and the entry address of the caller corresponds to the context information of the caller. Specifically, the link register may save the call stack address of the current caller to record the call behavior of the current trigger, and the call stack address is associated with the context information of the caller. After the caller initiates the call instruction (ipccall), the IPC logic circuit of the IPC engine queries the status register in the CPU. By querying the latest saved caller status in the status register, you can know which caller initiated the call, so that the call stack address of the caller can be saved To the link register. When the callee completes the execution of the service, the link register can pop up the current caller's record to realize process switching (that is, the CPU switches from the context of the callee to the context of the caller) to restore the process of the caller. The callee register set and link register provided in the embodiments of the present application can implement the context switching process of the process in hardware, thereby freeing up the software execution time of the CPU and reducing the delay of the IPC process.

Based on the first aspect, in a possible embodiment, the IPC engine hardware is specifically used to check whether the client process and the server meet the requirements of inter-process communication. When the terminal meets the requirements of inter-process communication, instruct the processor core to run the server process according to the identifier. Executing this embodiment makes the IPC engine hardware provided by this application more secure and reliable.

For example, the IPC engine can check at least one of the following conditions through the IPC logic circuit:

1) Check whether caller and callee are at different execution levels.

2) Check whether the caller and callee are in the same processor core. The IPC logic circuit can determine whether the process context information needs to be migrated according to whether the process is in the same core.

3) Check the security authority of the caller to determine whether the caller has the authority to call the service of the callee.

4) Check whether the relevant parameters carried by the call instruction meet the length requirement.

Based on the first aspect, in a possible embodiment, the call instruction and the return instruction are both user mode instructions. This satisfies the service call of the caller and the callback of the callee, realizes the interaction of the process at the user mode level, avoids the disadvantages of frequent switching between the user mode and the kernel mode in the existing IPC mechanism (such as the binder mechanism), and realizes that the software does not switch to the kernel. Mode, the IPC engine and CPU work in parallel on the hardware.

Based on the first aspect, in a possible embodiment, when the caller needs to initiate an ipccall to the IPC engine, the operating system allocates memory to the caller based on the shared memory, that is, allocates a part of the memory space in the shared memory to the caller to save the data to be transferred (msg), and indicate the virtual address (VA) of the data to the caller, and set the access permission to be readable and writable by the caller, and the other processes/threads are not readable and writable. When the ipccall instruction is executed, after the permission check is passed, the IPC engine sets this part of the shared memory to callee readable according to the callee entry information, and other processes/threads cannot read or write.

In the second aspect, an embodiment of the present application provides a method for inter-process communication IPC. The method in this embodiment is a method executed in the system described in the first aspect. The method includes: when the IPC engine hardware is initialized by the processor core, a part of the memory space in the memory is configured as the shared memory space of the process, and the shared memory space is used to store the data to be transferred required for inter-process communication; The start address and length of the shared memory space establish a page table, the page table contains the virtual address to the physical address mapping relationship of the shared memory space; the processor core runs a client process, and the client process needs When the service of the server process is called, a first processor instruction is sent to the IPC engine hardware. The first processor instruction is a call instruction of the client process to the service, and the call instruction includes the server process The identifier of the data to be transferred and the virtual address of the data to be transferred; the physical address of the data to be transferred is located in the shared memory space; the IPC engine hardware instructs the processor core to run the server process according to the identifier and transfers the The virtual address of the data to be transferred is sent to the server process; the processor core runs the server process, and the server process queries the page table according to the virtual address of the data to be transferred to obtain the Data to be transferred to execute the service; the processor core sends a second processor instruction to the IPC engine hardware, the second processor instruction is a return instruction of the server process; the IPC engine hardware is based on The second processor instruction instructs the processor core to resume running the client process.

Based on the second aspect, in a possible embodiment, the processor core allocates a part of the shared memory space to the client process when the client process needs to call the service of the server process, To save the data to be transferred.

Based on the second aspect, in a possible embodiment, before the processor core runs the client process, the method further includes: the processor core sends the server process information to the IPC engine hardware Registration information, where the registration information includes the identifier; the IPC engine hardware receives the registration information; in response to the registration information, stores the identifier and the entry address of the server process in the IPC engine hardware; Correspondingly, the IPC engine hardware instructs the processor core to run the server process according to the identifier, including: the IPC engine finds the entrance address according to the identifier; and sets the entrance address to all The program counter (PC) in the processor core; the processor core runs the server process according to the entry address set in the PC.

Based on the second aspect, in a possible embodiment, after the processor core sends the first processor instruction to the IPC engine hardware, the method further includes: the IPC engine hardware queries the status register in the processor core To obtain the call stack address of the client process, and save the call stack address of the client process in the IPC engine hardware; correspondingly, the IPC engine hardware according to the second processor instruction, Instructing the processor core to resume running the client process includes: the IPC engine hardware calls out the call stack address according to the second processor instruction, and instructs the processor core according to the call stack address Resume the client process.

Based on the second aspect, in a possible embodiment, before the IPC engine hardware instructs the processor core to run the server process according to the identifier, the method further includes: the IPC engine hardware checks the client Whether the client process and the server meet the requirements of inter-process communication; correspondingly, the IPC engine hardware instructs the processor core to run the server process according to the identifier specifically includes: the client process and the server process When the server meets the requirements of inter-process communication, the IPC engine hardware instructs the processor core to run the server process according to the identifier.

Based on the second aspect, in a possible embodiment, the call instruction and the return instruction are both user mode instructions.

In the third aspect, the present application provides a method for inter-process communication IPC, which is applied to an IPC engine in the form of a physical entity (ie, IPC engine hardware); when the IPC engine hardware is initialized, the processor core will A part of the memory space in the memory is configured as the shared memory space of the process, the shared memory space is used to store the data to be transferred required for inter-process communication; the page table is established according to the starting address and length of the shared memory space, the The page table contains the mapping relationship between the virtual address and the physical address of the shared memory space;

The method includes: the IPC engine receives a call instruction from the client process; the call instruction is used to request the service of the server process, and the call instruction includes the identifier of the server process and the virtual address of the data to be transferred; The IPC engine activates the server process according to the identifier of the server process, so that the server process queries the page table according to the virtual address of the data to be transferred to obtain the data to be transferred to execute the process. The service; the physical address of the data to be transferred is located in the shared memory space, the IPC engine receives a return instruction from the server process, the return instruction includes an execution result; wherein, the call instruction and the return The instructions are all processor instructions in the user mode; the IPC engine restores the client process according to the return instruction.

Based on the third aspect, in a possible embodiment, when the client process needs to call the service of the server process, the processor core allocates a part of the memory space in the shared memory space to the client process, To save the data to be transferred.

Based on the third aspect, in a possible embodiment, the length of the data to be transferred is greater than a preset threshold.

Based on the third aspect, in a possible embodiment, before the IPC engine receives the call instruction from the client process, the method further includes: the IPC engine accepts the registration of the server process; the IPC engine according to The registration of the server process records the identifier of the server process and the entry address of the server process.

The IPC engine activating the server process according to the identifier of the server process includes: the IPC engine finds the entry address of the server process according to the identifier of the server process; the IPC engine according to the identifier of the server process; The entry address of the server process runs the server process.

Based on the third aspect, in a possible embodiment, after the IPC engine receives the call instruction from the client process, it further includes: the IPC engine records the entry address of the client process; correspondingly, the IPC engine Restoring the client process according to the return instruction includes: the IPC engine switches the operation of the server process to the operation of the client process according to the entry address of the client process.

Based on the third aspect, in a possible embodiment, before the IPC engine runs the server process according to the server process identifier, the method further includes: the IPC engine checks the client process and the server process Whether it meets the requirements of inter-process communication; correspondingly, the IPC engine activates the server process according to the identifier of the server process, including: meeting the requirements of inter-process communication between the client process and the server In this case, the IPC engine activates the server process according to the identifier of the server process.

In the fourth aspect, the embodiments of the present application also provide IPC engine hardware, which is used to execute the method described in the third aspect, or can realize the function of the IPC engine hardware in the method described in the second aspect. The IPC engine hardware includes an IPC logic circuit (or called IPC logic), callee register set, link register (or link reg), message register set, the IPC engine can be deployed on the CPU core or independently. The IPC engine hardware may be a coprocessor or an independent processing chip. In some embodiments, the IPC engine hardware may be integrated in the processor, and the IPC engine hardware and the CPU core run in parallel. In still other embodiments, the IPC engine hardware may be independent of the processor and communicate through a communication line/interface.

In a fifth aspect, this application provides a computer storage medium for storing a computer program, and when the computer program is executed by one or more processors, any one of the second aspect or the third aspect is provided. Methods.

In a sixth aspect, the present application provides a computer program product, the computer program product is used to store a computer program, and when the computer program is executed by one or more processors, any one of the second aspect or the third aspect is provided. Methods.

Description of the drawings

Figure 1 is a schematic diagram of a scene of the existing Binder mechanism;

FIG. 2 is a schematic diagram of a possible application scenario of communication between a client process and a server process based on a CS mode provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of another possible application scenario of communication between a client process and a server process based on the CS mode provided by an embodiment of the present application;

4A is a block diagram of a possible system structure of a computing device in an embodiment of the present application;

4B is an example diagram of a physical hardware system provided by an embodiment of the present application;

4C is a schematic structural diagram of a computing device provided by an embodiment of the present application;

FIG. 5A is a possible hardware architecture of an IPC engine provided by an embodiment of the present application;

FIG. 5B is an example diagram of some application scenarios of the IPC engine provided by an embodiment of the present application;

FIG. 5C is an example diagram of another application scenario of the IPC engine provided by an embodiment of the present application;

FIG. 6 is a schematic flowchart of an inter-process communication method provided by an embodiment of the present application;

FIG. 7 is a schematic flowchart of another method for inter-process communication provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of a scenario of a shared memory solution provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of an IPC communication scenario using the solution of the present application provided by an embodiment of the present application.

Detailed ways

The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and/or" as used herein refers to and includes any or all possible combinations of one or more associated listed items. The terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusion, for example, including a series of steps or units. The method, system, product, or device need not be limited to those clearly listed steps or units, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or devices.

It should be understood that in this application, "at least one" refers to one or more, and "multiple" refers to two or more. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. "The following at least one item (a)" or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a). For example, at least one of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c" ", where a, b, and c can be single or multiple.

This application provides a new IPC mechanism through which the delay of the IPC process can be significantly reduced and the efficiency of data transmission can be improved. In order to better understand the solution of the present application, the client-server (CS) mode involved in the embodiments of the present application is first described below. In this article, the requestor of the service can be called the client, the implementer of the service can be called the server, the process of the client can be referred to as the client process for short, and the client process is the process that accesses the service. , This article can also be referred to as the sender (caller). The server process can be referred to as the server process for short. The server process is a process that provides services, and can also be referred to as a receiving process (callee) in this article.

Referring to Figures 2 and 3, Figures 2 and 3 exemplarily describe possible application scenarios for communication between a client process and a server process based on the CS mode provided in an embodiment of the present application. In some possible embodiments, the two processes (client process and server process) may be located in the same computing device, that is, IPC reflects the communication between two processes in the same computing device, here The computing device can be a terminal or a server. In an example, as shown in FIG. 2, the two processes may run on the same processor core of the computing device, such as the CPU core. In another example, when the computing device has multiple CPU cores, the two processes can run on different CPU cores of the computing device (such as CPU core1 and CPU core2 in the figure). In other possible embodiments, the two processes may also be located on different computing devices, that is, IPC reflects the communication between two different computing devices (computing device 1 and computing device 2), where, The computing device 1 and the computing device 2 may both be terminals, or both may be servers, or one device may be a terminal and the other device may be a server.

Taking two processes located on the same computing device as an example, the operating system type of the computing may be the Android system (Android system). In the description of the following related embodiments, the inter-process communication method of the present application is applied to the Android system. Examples are explained.

In the embodiments of the present application, the system architecture of the computing device may be designed using a layered architecture, an event-driven architecture, a microkernel architecture, a microservice architecture, or a cloud architecture. In the following, an Android system with a layered architecture is taken as an example to illustrate a system architecture of a computing device by way of example. Refer to FIG. 4A, which is a block diagram of a possible system structure of a computing device in an embodiment of the present application. The system architecture includes the physical hardware at the bottom layer and the software architecture running on the physical hardware. The physical hardware layer provides various computing resources (such as CPU), storage resources (such as memory, disk, etc.), communication resources ( For example, transceiver) and so on. The software architecture divides the software into several layers, and each layer has a clear role and division of labor. Communication between layers through software interface.

In a possible implementation, the software architecture of the Android system is divided from bottom to top: the kernel layer (kerne), the hardware abstraction layer (HAL), the system service layer, the application framework layer, and the application layer. Among them: the kernel layer is used to provide drivers for the Linux kernel and various hardware devices. The hardware abstraction layer is used to encapsulate the kernel layer hardware driver and provide a unified hardware interface that can be called by the system service layer. The system service layer is used to provide system services (service) and provide an interface that can be called by the application framework layer. The application framework layer can be understood as Android SDK, which is used to provide the four major components, drawing and other basic components used in usual development. Developers can call the interface of the application framework layer. The application layer is used to provide user-oriented applications (APP).

It should be noted that the kernel layer adopted by the computing device in the embodiment of the present application may be a macro kernel (Monolithic kernel) or a micro kernel (Micro kernel). Among them, the macro kernel, such as the linux kernel, not only provides the most basic process, thread management, and memory management, but also provides file systems, drivers, network protocols, and so on. For the micro-kernel (such as SEL4, QNX, Fuchsia, LK etc.) architecture, the kernel provides the most basic scheduling and memory management. Drivers, file systems, etc. are all implemented by user-mode daemons, which bring better scalability, security and fault tolerance, and are applied to more and more products (such as mobile terminals, cars, aircrafts, etc.). Equipment, etc.).

In the embodiments of this application, the processing logic of IPC is set to the physical hardware layer instead of the kernel layer, and a dedicated hardware form IPC engine (IPC Engine) is designed. In this article, the IPC engine may also be referred to as IPC engine hardware. As the core of process interaction, it can be processed in parallel with the kernel. The kernel can initialize, configure, control, service process registration, and handle abnormal interrupts for the IPC engine. The service call (function call), context switch, data exchange (transfer of data access rights) involved in the IPC process are completed by the IPC engine in hardware, and the transfer of data or data addresses is carried out within the IPC engine, thus avoiding software. Kernel mode and user process stack context switching and data copy, etc., thereby freeing up a large amount of CPU software execution time and reducing overall delay.

The IPC engine can run in parallel without the software execution cycle of the CPU. In the implementation of an IPC engine, the hardware-specific logic of the IPC Engine can be added to the chip where the CPU Core is located as a coprocessor, that is, the CPU Core and IPC Engine are integrated in the same chip; in another IPC engine implementation, IPC The engine can be a processing chip independent of the CPU Core.

In addition, in order to realize the interaction between the IPC engine and the process, the process is provided with processor instructions to use the IPC engine, such as "ipccall instruction" and "ipcret instruction". The client process (caller) in the user space can call the service of the server process (callee) through the ipccall instruction, and the server process can return through the ipcret instruction to restore the client process. The premise for the execution of the above two instructions is that the IPC engine is initialized (for example, including the initial configuration of the IPC engine, memory allocation, etc.), and the initialization process can be completed by the kernel mode driver.

Through the design of this application, the application framework layer in Android is open to developers in the form of SDK. The core services in the system service layer run when the system starts, and the application framework layer provides real-time applications through the manager (Manager) provided by the application framework layer. The program provides service calls. Each service in the system service layer runs in its own independent process space, and applications can call services in the system service layer through the IPC engine. Therefore, processes such as context switching and data exchange can be realized by hardware, and the CPU uses the IPC software communication mode to realize the cooperative work of software and hardware through the IPC engine, freeing up the software execution time of the CPU. In this way, at the level of user processes, caller and callee realize direct IPC communication in user mode, thereby avoiding the delay caused by switching between kernel mode and user mode in the existing scheme, and data between processes The interaction can only transfer the data address (data access right), thereby reducing or even eliminating the occurrence of data copying, greatly improving the efficiency of data transmission, and further reducing the delay of the IPC process.

An embodiment of the present application also provides a physical hardware system, including: a central processing unit (CPU) and IPC engine hardware. In this article, the IPC engine hardware may be referred to as IPC engine for short. In specific implementation, the IPC engine hardware may be a logic circuit. Or an independent logic computing chip. Wherein: the CPU includes a CPU core. In some embodiments, the IPC engine may be integrated in the CPU, and the IPC engine and the CPU core run in parallel. In still other embodiments, the IPC engine may be independent of the processor core.

Referring to FIG. 4B, FIG. 4B is an example diagram of a physical hardware system further provided by an embodiment of the present application. The physical hardware system includes a CPU core 11, an IPC engine 12, and a DDR memory 13. Among them, part or all of the CPU core 11, the IPC engine 12, and the DDR memory 13 may be integrated, or connected through a general communication interface, or connected through a bus. Among them: CPU core11 can be used to run processes (client process caller or server process callee), IPC engine 12 can be used to implement inter-process communication, and DDR memory 13 can be used to provide data and context information necessary for process operation. Specifically, the CPU core may register the server process with the IPC engine in advance, and the IPC engine saves the identifier of the server process and the entry address of the server process according to the registration. The CPU core may be used to send a first processor instruction to the IPC engine when the client process needs to call the service of the server process, where the first processor instruction includes the call instruction of the client process to the service (Such as the ipccall described in any embodiment of this application), the call instruction includes the identifier of the server process and the virtual address of the data to be transferred; the virtual address of the data to be transferred may be the value of the data to be transferred in the DDR memory The virtual address corresponding to the location.

The IPC engine can be used to save the entry address of the client process; and find the entry address of the server process according to the identifier (ID) of the server process, and then instruct the CPU core to run the server process, thereby realizing the process Context switch. In addition, the IPC engine can also establish a mapping between the address of the data to be transferred and the address of the server process in the memory space, and transfer the mapping to the server process, thus realizing the transfer of data access rights (not the data itself).

The CPU core is also used to run the server process to execute the service according to the data to be transferred; the CPU core is also used to send a second processor instruction to the IPC engine, and the second processor instruction includes the server The return instruction of the process (such as ipcret described in any embodiment of this application). Wherein, the first processor instruction and the second processor instruction are both user-mode processor instructions. The IPC engine is also used to find the entry address of the client process and instruct the processor core to run the client process, thereby realizing the recovery of the client process.

It can be seen that in the implementation of the embodiments of this application, processes such as context preservation, context switching, and data exchange can be implemented on the IPC engine hardware. After the caller actually initiates the IPC, the IPC process does not need to be involved in the kernel, and the software does not switch. In the kernel mode, the IPC engine and the CPU core work in parallel on the hardware. The CPU uses the IPC software communication method to realize the cooperative work of software and hardware through the IPC engine, thereby releasing the software execution time of the CPU core. In order to match the hardware form of the IPC engine and the process It also provides user-mode processor instructions (first processor instructions and second processor instructions), which satisfies the caller’s service call and callee’s callback, realizes the process’ interaction at the user-mode level, and guarantees IPC The realizability of the process. In this way, at the level of the user process, the caller and callee realize the direct IPC communication in the user mode, thereby avoiding the frequent switching between the user mode and the kernel mode in the existing IPC mechanism (such as the binder mechanism). The time delay caused by the data interaction between processes can only transfer the mapping of the data address (data access rights), thereby reducing or even eliminating the occurrence of data copying, greatly improving the data transmission efficiency, and further reducing the delay of the IPC process.

Further, referring to FIG. 4C, FIG. 4C exemplarily shows a schematic structural diagram of a computing device 30. The computing device 30 may be a terminal or a server. It should be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the computing device 30. As shown in FIG. 4C, the computing device 30 may include: a chip 310, a memory 315, and a user interface 314. These components can communicate on one or more communication buses.

The chip 310 may integrate: one or more processors 311, an IPC engine hardware 312, and a power management module 313. The processor 311 can perform operations, generate operation control signals, complete control of fetching and executing instructions, running processes (such as client process caller or server process collee), and so on. The power management module 313 integrated in the chip 310 is mainly used to provide a stable and high-precision voltage for the chip 310 and other components of the computing device 30. The IPC engine hardware 312 integrated in the chip 310 may be the IPC engine described in any embodiment of the present application, which implements processes such as context preservation, context switching, and data exchange in the IPC communication.

The IPC engine hardware 312 may be a coprocessor or an independent processing chip. In some embodiments, the IPC engine hardware 312 may be integrated in the processor 311, and the IPC engine hardware 312 and the CPU core run in parallel. In still other embodiments, the IPC engine hardware 312 may be independent of the processor 311 and communicate through a communication line/interface. For the specific function implementation of the IPC engine hardware 312, reference may be made to the description of the IPC engine in any embodiment of the present application.

The processor 311 may specifically include one or more processing units with different capabilities. For example, the processor 311 may include the central processing unit (CPU, central processing unit) and application processor (AP) described in the previous embodiment. Modulation and demodulation processor, graphics processing unit (GPU), image signal processor (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband Processor, and/or neural-network processing unit (NPU), etc. Among them, the different processing units may be independent devices or integrated in one or more processors. Each processing unit may include one or more cores.

In some embodiments, the processor 311 may include one or more interfaces. The interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (PCM) interface, and a universal asynchronous transceiver (universal asynchronous transceiver) interface. asynchronous receiver/transmitter, UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, And/or Universal Serial Bus (USB) interface, etc.

The memory 315 may be connected with the processor 311 through a bus, or may be coupled with the processor 311, and used to store various data, software programs, and/or multiple sets of instructions. In a specific implementation, the memory 315 may include a DDR memory for storing data and context information necessary for the operation of the process. The memory 315 may also include a high-speed random access memory (for example, a cache memory), and the memory 315 may also include a non-volatile memory, such as one or more magnetic disk storage devices, flash memory devices, or other non-volatile solid-state storage devices.

The user interface 314 can be used to connect peripheral devices in the computing device 30, such as various input/output devices (I/O devices, sensors, display screens, etc.), which is not limited in the embodiment of the present application.

The following describes a possible hardware architecture of the IPC engine in the embodiment of the present application. Referring to Figure 5A, the hardware architecture may include IPC logic circuit (or IPC logic), callee register set (also referred to as the second register set), link register (or link reg), message register set (also referred to as It is the first register set), the IPC engine can be deployed on the CPU core or independently.

As the control center of the IPC engine, the IPC logic circuit can respond to two user mode processor instructions ipccall and ipcret. The ipccall and ipcret are instructions that the process can call in the user mode; control the IPC process and complete the callee Check the various conditions of the caller and so on.

The callee register set includes a set of registers, which is used to record the indication information of the context information of the callee. The register may be a 32-bit or 64-bit register, for example, and the bit width of the register is not limited in this application. Specifically, the callee register set is specifically used to record the entry addresses (callee entry addresses) of multiple callees, and each callee entry address corresponds to the context information of a callee. Therefore, the callee entry address can also be referred to as "indication information of the context information of the callee".

In an embodiment, the callee entry address may indicate the address of the context of a callee process in the global DDR (for example, the DDR memory 13 in FIG. 4B). Exemplarily, the specific content of the callee entry address may be but not limited to: at least one of a page table pointer (page table pointer), an address pointer, a virtual address, or a physical address.

In an embodiment, the callback entry address includes an address pointer of the service function of the callback. The service function may be a callback function (Callback function), that is, the address pointer of the callback points to the callback function (Callback function) registered by the callback. Address, the callback function is used for callee to execute the corresponding service (service). The callback function belongs to a kind of handler, which is a function called through a function pointer, and the call between functions is realized through the callback function. If the pointer (address) of a function is passed as a parameter to another function, when this pointer is used to call the function pointed to by it, the function is called a callback function. The IPC engine can set the Program Counter (PC) in the CPU to the callee entry address, so that the CPU starts to execute the callee process context and run the callee to execute the corresponding service.

A callee entry address can be recorded through the callee register set each time. When the callee entry address of multiple callees is recorded in the callee register set multiple times, these callee entry addresses can form a list. This list can be called a callee list (callee list). list), this list can be stored in memory for indexing. The callee register set can be regarded as the manager of the callee list, which provides functions such as registration, editing (addition, deletion), maintenance, access, or query of the callee list.

As shown in Figure 5A, in a possible implementation, the callee register set further includes a first address register and a counting register. The first address register is used to store the first address of the callee list. Specifically, it can be the first callee in the callee list. entry address. The counting register is used to record the number of callee entry addresses (entry list size). Specifically, each time a list entry (ie, a callee entry address) is added to the callee list, the number of the count register records is increased by 1. In this way, through the callee register set, the entry address (callee entry address) of multiple callees can be recorded to the callee list according to the registration status of multiple callees.

Referring to FIG. 5B, (1) in FIG. 5B shows an example diagram of a scenario of registering a callee to a callee list with an IPC engine. In a specific implementation, each list entry in the callee list can be configured to correspond to an index identification (ID). The index ID may be the process ID of the callee (ie callee ID), or the index ID may be one-to-one mapped with the process ID, and the index ID may be determined after the callee is registered with the IPC engine. In this way, it is convenient for the client process (caller) to perform IPC with one or more callees.

The registration process of the callee to the IPC engine can be completed through a system call. For example, the user interface of the device driver CPU core corresponding to the kernel kernel can be used to save relevant content (such as an address pointer) to the first address register of the IPC engine according to the context information of the callee.

In this way, during the IPC process, the IPC engine can find the callee entry address according to the ID passed in by the caller. As shown in (2) in Figure 5B, the call instruction (ipccall) initiated by the caller to the IPC engine carries the callee ID (callee ID). In this way, the IPC logic circuit can look up the callee list according to the callee ID and index to the callee. The entry address of the callee (callee entry address). The IPC engine can also set the Program Counter (PC) in the CPU to the callee entry address, so that the callee can run and provide corresponding services. The program counter is a register that holds the address (location) of the instruction currently being executed. When each instruction is fetched, the storage address of the program counter is incremented by one. After each instruction is fetched, the program counter points to the next instruction in the sequence. Therefore, the IPC engine can send the callee entry address to the PC for recording, so that the CPU executes the command to run the callee.

In the embodiments of this application, when the IPC engine is deployed on the CPU core, the user interface of the CPU core can provide system calls such as callee entry address addition (add) and removal (remove), and the registration and deregistration of the callee service can also be done through this Interface implementation.

The link register is used to store the entry address of the current caller, and the entry address of the caller corresponds to the context information of the caller. Specifically, the link register may save the call stack address of the current caller to record the call behavior of the current trigger, and the call stack address is associated with the context information of the caller. After the caller initiates the call instruction (ipccall), the IPC logic circuit of the IPC engine queries the status register in the CPU. By querying the latest saved caller status in the status register, you can know which caller initiated the call, so that the call stack address of the caller can be saved To the link register. When the callee completes the execution of the service, the link register can pop up the current caller's record to realize process switching (that is, the CPU switches from the context of the callee to the context of the caller) to restore the process of the caller. The callee register set and link register provided in the embodiments of the present application can implement the context switching process of the process in hardware, thereby freeing up the software execution time of the CPU and reducing the delay of the IPC process.

The message register set includes a set of registers used to record the address of the data (msg) that the caller needs to pass to the callee. The register may be a 32-bit or 64-bit register, for example, and the bit width of the register is not limited in this application. The message register set can be used to establish and save indication information (such as pointers). The indication information indicates the mapping relationship between the virtual address (VA) and the physical address (PA) of the data (msg) that needs to be transferred in the IPC communication process, and the mapping relationship Can be stored in memory.

In a specific embodiment, the message register set is used to record multiple msg entry addresses (msg entry addresses). In a specific implementation, the message register set can record the address of the data passed in by the caller in the call instruction, or the data itself (for example, only a few bytes of small data). Each msg entry address indicates the address of msg in the DDR memory (may be referred to as msg memory address). The msg entry address may contain at least one of the following: the base address of the virtual address (VA base), the base address of the physical address (PA base), address space length (length). It can be seen that the message register set can record the address of the data to be transmitted by one or more callers, so that it is convenient for the caller to perform IPC with one or more callees. It should be understood that the subsequent embodiments take the memory as an example for introduction, but it is not used for limitation, and can be extended to other types of memory.

A caller can pass in one or more msg addresses through a call instruction (ipccall). In an embodiment, the address of the incoming msg may be a virtual address (VA) of the msg. One or more msg entry addresses can be recorded through the message register set each time. When the message register set records msg entry addresses multiple times, these msg entry addresses can form a list, which can be called a msg list (msg list), and this list can be stored in memory for indexing. The message register set can be regarded as the manager of the msg list, providing functions such as editing (adding, deleting), maintaining, accessing, or querying the msg list.

In some embodiments of the present application, in order to avoid copying of the data to be transferred in the IPC process, in the IPC engine, the data itself may not be directly transferred, but the transfer of the data is indirectly realized through the mapping (memory mapping) of the transferred data. , Without the need to copy data. Specifically, a mapping mechanism of msg address space can be added to the IPC engine, and a part of the memory in the DDR global memory can be pre-configured as a shared memory, and the shared memory can be shared and accessed by the caller and the callee. That is to say, the caller and the callee share a section of memory space, which is referred to as shared memory in this article), and the physical address (PA) of the msg to be transferred is the location of the msg in the section of memory space. The shared memory is used to store the data (msg) that needs to be transmitted during the service call, so that the msg is only mapped between the caller and the callee.

Specifically, referring to FIG. 8, in the embodiment of the present application, when the system is initialized (IPC engine initialization), the operating system running on the processor core reserves (or configures) a part of the memory in the physical memory as the shared memory of the caller and the callee. In order to improve data access security, memory access permissions can also be initialized. At the same time, the logic of accessing this part of the shared memory can be unified into the access logic of the existing memory management unit (MMU) to avoid changes to the execution flow of the existing MMU and avoid page faults. That is to say, in the embodiment of the present application, the shared memory is fixedly reserved for allocation when the IPC engine is initialized, and this part of the shared memory is not in the page management page table of the kernel (for example, the kernel). This part of shared memory can be directly accessed by the IPC engine. The shared memory can be used to store data that needs to be transferred between processes during IPC communication. By reserving the shared memory, a dedicated page table (the page table containing the mapping relationship between virtual addresses and physical addresses) can be established to ensure that the data to be transferred always has a corresponding physical page, thereby avoiding page faults.

After the shared memory is allocated, the virtual address (VA) to the physical address (PA) mapping relationship is formed globally in the shared memory. Each msg involved in IPC communication is stored in the shared memory, thus forming a large number of msg virtual addresses ( VA) to a physical address (Physical Address, PA) mapping relationship (for example, a mapping table), and the IPC engine can access such a mapping table. When the caller needs to call the callee service, the operating system allocates memory to the caller based on the shared memory, that is, allocates a part of the memory space in the shared memory to the caller to save the data to be transferred (msg), and the virtual address of the data (VA ) Indicates to the caller so that the caller can initiate the call instruction ipccall.

Later, when the caller initiates a call instruction to the IPC engine, the IPC logic circuit of the IPC engine can implement the maintenance of the msg list by looking up the mapping table.

Referring to FIG. 5C, FIG. 5C shows an example diagram of a scenario where the IPC engine maintains the msg list according to the call instruction (ipccall) of the caller. As shown in Figure 5C, in a possible implementation, the message register set further includes a msg register and a counting register. The msg register may also be an exemplary first address register, which is used to store the first address of the msg list. Specifically, it may be msg The first msg entry address in the list. The counting register is used to record the number of msg entry addresses. Specifically, each time a list entry (that is, an msg entry address) is added to the msg list, the number of the counting register records is increased by 1. In this way, one or more msg entry addresses can be recorded to the callee list through the message register set. Among them, each list entry (that is, a msg entry address) can be specifically expressed as the physical address (PA) of the msg in the shared memory. In specific implementation, the ipccall of the caller can carry msg VA (as shown in the VA1), and the IPC logic circuit of the IPC engine can look up the mapping table corresponding to the shared memory based on the msg VA to determine the PA corresponding to the msg VA (as shown in the figure) PA1), the PA is used as the msg entry address, and the msg entry address to the msg list is recorded through the message register set. It is understandable that when multiple msg VAs are passed into the caller, multiple msg entry addresses can be recorded to the msg list through the message register set.

In a specific implementation, in order to facilitate data search, each list entry (PA) of the msg list can be configured to correspond to a virtual address (VA). That is, the mapping relationship between msg VA and PA is formed. In this way, you only need to transfer msg VA to callee without passing msg itself, avoiding the drawbacks of data replication and improving transmission efficiency.

In some embodiments, during the IPC communication process, Callee can use the VA to query the msg list maintained by the IPC engine to obtain data. The query process includes, for example, the callee uses msg VA to request the corresponding PA from the IPC engine, and the IPC logic circuit of the IPC engine finds the corresponding PA in the VA based on the mapping relationship, and then sends it to the callee.

In still other embodiments, after the shared memory is allocated, when the callee is registered with the IPC engine, the callee can also create the page table of the process and add it to the MMU according to the starting address and size of the shared memory. The table globally defines the mapping between the virtual address (VA) and the physical address (PA) of the shared memory. The callee can access the page table according to the VA to directly obtain the PA corresponding to the VA, that is, the callee can be used The VA directly accesses the data (msg) in the shared memory, thus realizing the unification of the address access logic to the MMU, avoiding changes to the existing MMU process, thereby further improving the feasibility of the solution. In this embodiment, the msg list maintained by the IPC engine can be used to verify the correctness of the data, that is, after the msg list is built, when the caller initiates the service call again, the IPC engine checks the PA corresponding to the VA through the msg list Whether it is in the shared memory (that is, whether the mapping relationship between the VA and the PA in the shared memory is recorded in the msg list).

Further, in order to achieve the security and accuracy of data access, the IPC logic circuit of the IPC engine can control the access authority of the msg by setting the query authority of the callee to the msg list maintained by the IPC engine. For example, when the caller needs to initiate an ipccall to the IPC engine, the operating system allocates memory to the caller based on the shared memory, that is, allocates a part of the memory space in the shared memory to the caller to save the data to be transferred (msg), and virtualize the data The address (VA) is indicated to the caller, and the access permission is set to be readable and writable by the caller, and the other processes/threads are not readable and writable. For the callee corresponding to the callee ID passed in when the caller invokes the service, the IPC engine can enable the search permission in the context information of the callee, that is, the callee corresponding to the callee ID is allowed to use the VA to query the msg list maintained by the IPC engine, and the data The memory is set to be readable by callee, and other processes/threads are not readable and writable, thus achieving access to msg. For other callees, the search permission is closed by default, so other callees cannot query the msg list, which prevents other callees from illegally accessing data and improves the security and accuracy of data access.

In addition, during the execution cycle of the IPC logic circuit, different CPU cores can also be prohibited from simultaneously accessing resources on the IPC engine to resist possible malicious attack programs and improve the security of the IPC process.

It can be seen that data (msg) can be mapped between caller and callee through shared memory. The IPC engine maintains the mapping relationship between msg VA and PA. The IPC engine can set the access rights of msg according to the ipccall initiated by the caller. msg VA can be passed to callee. In this way, the data transfer is indirectly completed without relying on the kernel and no data copy, and the transfer process is not visible to the outside. It can also be understood that, in the embodiment of this application, the current caller's data transfer form may be the transfer of data access rights (rather than the data itself), and the access rights are obtained from the caller's call chain, such as caller->callee, thus It saves transmission resources and improves data transmission efficiency.

It should be noted that in this article, the so-called "context information of the process" can be regarded as various variables, data, and the environment when the process is executed, including the variables and processes of all registers related to the process. Open files, or memory information, etc. When process scheduling occurs, the process switching is the context switching of the process. The context information mentioned above needs to be switched before the newly scheduled process can run. For example, when it is necessary to switch from a client process to a server process, all the states of the client process need to be saved, and at the same time, the state of the server process needs to be loaded. In this way, when the service ends, the state of the interrupted client process can be restored based on the context information of the client process.

It can be seen that the embodiment of the present application designs a dedicated hardware form of the IPC engine, and the IPC engine can be used as a coprocessor or a separate execution unit to run in parallel without the software execution cycle of the CPU. The IPC engine further provides an IPC logic circuit and multiple registers to establish a new IPC mechanism. In order to cooperate with the interaction between the IPC engine and the process in the form of hardware, the embodiment of the application also designs user-mode processor instructions for caller and callee respectively: ipccall and ipcret, so as to call the interface, thereby satisfying the service call of the caller. And the callback of the callee ensures the feasibility of the IPC process. The premise of the execution of the above two instructions is that the IPC engine is initialized. The initialization process can be completed by the kernel mode driver, including the initial configuration of the IPC engine, memory allocation, and so on.

The IPC engine can realize the context information preservation, context switching, or data transfer in the user mode. The kernel of these processes is not aware (that is, the IPC process may not need the kernel to participate), avoiding users in the existing IPC mechanism (such as the binder mechanism) The disadvantage of frequent switching between the kernel state and the kernel state separates the IPC process of the process from the kernel, thereby freeing up a large amount of CPU software execution time, thereby greatly reducing the overall delay of the IPC process.

In addition, the IPC engine in the embodiment of the present application maps the data memory, and only needs to transfer the virtual address of the data to the callee, instead of transferring the data itself, thereby avoiding the copy of the data and reducing the data. Copy delay and improve data transmission efficiency.

In addition, the implementation of the solution of the embodiment of the present application can also realize that after the IPC engine is initialized, the operating system allocates shared memory, and the callee initiates registration and establishes the page table of the process, which is managed by the MMU. When the caller needs to call the service, the operating system allocates a memory segment in the shared memory to the caller to store the generation transfer data (msg). The mapping relationship between the virtual address and the physical address of the msg in the memory segment is recorded in the page table managed by the MMU The mapping relationship is consistent. Therefore, in the subsequent IPC communication, after the msg VA is passed from the caller to the callee through the IPC engine, the callee can access the page table according to the VA to obtain the data, thus achieving the shared memory of the caller and the callee. The purpose is to avoid changes to the existing MMU workflow, avoid page faults, and ensure the stability and security of IPC communication.

It should be understood that the IPC engine in FIG. 5A may be implemented in pure hardware, including a large number of logic circuits, arithmetic circuits or registers, and may also include various interfaces or analog circuits, which are not limited in this embodiment. When the IPC engine is a coprocessor, it can be implemented as pure hardware that does not execute software, or part of it can be implemented as a coprocessor that can run software. At this time, the function of the IPC engine is realized by running the necessary software. At this time, the corresponding components in FIG. 5A can run necessary software modules to implement the technical solution. The IPC engine at this time is still a hardware accelerator independent of the CPU, but it needs necessary software to drive its work, which is not specifically expanded in this embodiment.

For the method embodiments described below, for the sake of convenience, they are all expressed as a combination of a series of action steps. However, those skilled in the art should know that the specific implementation of the technical solution of the present application is not limited to the series of steps described. Restrictions on the order of action steps.

Based on the system architecture and IPC engine described above, the following describes the flow of an inter-process communication (IPC) method provided by an embodiment of the present application. See FIG. 6. This method is described from the perspective of the IPC engine, including but not limited to The following steps:

S100. When the IPC engine hardware is initialized, the operating system running on the processor core configures a part of the memory space in the memory as the shared memory space of the process, and the shared memory space is used to store the to-be-transferred data required for inter-process communication. Wherein, the memory may be memory, such as DDR memory, such as DDR SDRAM (Double Data Rate SDRAM, double rate SDRAM).

In the embodiment of this application, when the system is initialized (IPC engine initialization), the operating system fixedly reserves a part of the memory in the physical memory as the shared memory of the caller and the callee, and the shared memory can be used to store data that needs to be transferred between processes during the IPC communication process. .

In some embodiments, before running the callee process, the callee may establish a page table according to the starting address and size of the shared memory space, the page table is managed by the MMU, and the page table contains the virtual address of the shared memory space The mapping relationship to the physical address is convenient for the callee to look up the page table based on the VA in the subsequent IPC communication to obtain the generation transfer data.

In still other embodiments, indication information (pointer) is stored in the register of the IPC engine, and the indication information indicates the mapping relationship between the virtual address of the data to be transferred and the physical address of the data to be transferred, so that the subsequent callee can be used in the subsequent IPC. In the communication, based on the VA, query the IPC engine to obtain the generation transfer data.

When the caller needs to initiate an ipccall call to the IPC engine, the operating system allocates memory to the caller based on the shared memory, that is, allocates the memory segment in the shared memory to the caller to save the data to be transferred (msg), and the virtual address of the data ( VA) Instruct to the caller. The mapping relationship between the virtual address and the physical address of the msg in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU.

For the related implementation content of the foregoing embodiment, reference may be made to the previous related description, which will not be repeated here.

S101. The IPC engine receives a call instruction from the client process. The call instruction may be the ipccall described herein. The call instruction is used to request the service of the server process. The call instruction includes the identifier of the server process and the data to be transferred. address. The address can be a virtual address.

In the embodiment of this application, the server (Server), as the owner of many services, can register its own service with the IPC engine through the server process (callee) before it can provide services to the client (Client). . In one implementation, after the callee is started, the registration process can be completed with the assistance of a kernel driver, where the kernel may be a macro kernel or a micro kernel, which is not limited in this application.

The server can register one or more services with the IPC engine, and the IPC engine records the callee's ID and the callee entry address according to the callee registration, the callee entry address and the callee context Information correspondence.

Since the information of various services has been pre-registered in the IPC engine, the caller can learn from the IPC engine which services are available for use. The client, as a user of the service, can apply for one or more services to the IPC engine through the client process (caller) when the client needs to use one or more callee services. At this time, the caller of the client can use the call command (ipccall) in the user layer to request the IPC engine service.

Among them, the call request may include information such as the command that needs to call the service, the ID of the callee, and the address of the parameter msg.

S102. The IPC engine activates the server process according to the identifier (ID) of the server process, so that the server process executes the service according to the data to be transferred.

On the one hand, the IPC engine can search the local storage to find the entry address of the server process according to the identifier of the server process; then, the IPC engine can set the program counter (PC) to the callee entry address, Start executing the callee process context, so that the server process runs.

On the other hand, in order to avoid the copy of the data to be transferred in the IPC process, in the IPC engine, it is not necessary to directly transfer the data itself, but indirectly realize the transfer of the data by transferring the mapping (memory mapping) of the data to the callee. No need to copy data. Specifically, the address of the data to be transferred may be msg VA, and the IPC engine can establish a mapping relationship between msg VA and PA according to the shared memory mechanism, grant callee query authority for the mapping relationship, and pass VA to callee. Or the callee can query the page table in the MMU according to the VA to obtain the PA corresponding to the VA, thereby achieving access to the msg. In this way, the subsequent callee can query the IPC engine according to the VA to achieve access to msg, and perform the services required by the client according to the msg.

S103. The IPC engine receives a return instruction (ipcret) from the server process, where the return instruction includes an execution result.

Both ipccall and ipcret in this application belong to the processor instructions in the user mode. Therefore, the caller and callee realize the instruction interaction in the user mode during the IPC process to avoid falling into the kernel mode.

S104. The IPC engine restores the client process according to the return instruction.

In the embodiment of the present application, after the IPC engine receives the ipccall from the caller, it may also record the entry address of the caller. The entry address of the caller corresponds to the context information of the caller. In this way, when the IPC engine receives the ipcret of the callee, it can switch the operation of the callee to the operation of the caller according to the entry address of the caller, that is, realize the process switching. Specifically, after the callee completes the IPC processing, ipcret can be executed. In response to the ipcret, the IPC engine pops up the current caller record, thereby switching to the caller context and restoring the state of the caller.

It can be seen that the implementation of the embodiments of the present application can transfer the context information storage, context switching and restoration, and data transfer in the user state from time and space to a new physical entity (ie, IPC engine). As the medium of IPC, the IPC engine provides corresponding user mode commands ipccall and ipcret, so that the caller and callee can complete the context switch in the user mode without switching to the kernel mode, thereby satisfying the caller's service call and callee's callback. In order to interact with the process at the user mode level, the IPC engine can work in parallel with the kernel software, which greatly reduces the overall delay of the IPC process. In addition, in the embodiments of the present application, the IPC engine can be used to transfer data access rights, and only the virtual address of the data needs to be transferred to the callee, instead of the data itself, thereby avoiding copying of the data, and further Reduce the time delay of data copy, and improve the efficiency of data transmission.

In addition, the implementation of the solution of the embodiment of this application can also realize that after the IPC engine is initialized, the operating system allocates shared memory, and the callee initiates registration and establishes the page table of the process, which is managed by the MMU. When the caller needs to call the service, the operating system is in The shared memory is allocated to the caller to store the memory segment of the generation transfer data (msg). The mapping relationship between the virtual address of msg and the physical address in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU. Therefore, follow-up In IPC communication, after the msg VA is passed from the caller to the callee through the IPC engine, the callee can access the page table to obtain the data according to the VA, thereby achieving the purpose of sharing memory between the caller and the callee, and avoiding the need for existing The change of MMU workflow can avoid page faults, ensure the stability and security of IPC communication, and improve the feasibility of product implementation.

Based on the system architecture and IPC engine described above, the following describes another method of inter-process communication (IPC) provided by the embodiments of this application. The IPC engine can be deployed in the CPU core and communicate with the outside world through the user interface of the CPU core. Interaction, such as interacting with the process. Referring to Figure 7, the method describes the solution in detail from a multi-sided perspective, including but not limited to the following steps:

S200. When the IPC engine hardware is initialized, a part of the memory space in the memory is configured as the shared memory space of the process, and the shared memory space is used to store the to-be-transferred data required for inter-process communication. Wherein, the memory may be memory, such as DDR memory, such as DDR SDRAM (Double Data Rate SDRAM, double rate SDRAM).

For the relevant memory in this step, refer to the description of step S100, which will not be repeated here.

S201.callee is registered to the IPC engine after it is started.

Exemplarily, the callee can be registered to the IPC engine through the kernel. Of course, the callee can also be registered to the IPC engine in other ways. For example, for a system with a microkernel, it can be registered to the IPC engine through a user-mode driver. This application does not impose specific restrictions on the registration method.

In the embodiment of this application, the server (Server), as the owner of many services, has to register itself with the IPC engine through the server process (callee) before it can provide services to the client (Client) through IPC. Service. The server can register one or more services with the IPC engine.

In one implementation, after the callee is started, the registration process can be completed with the assistance of a kernel driver, where the kernel may be a macro kernel or a micro kernel, which is not limited in this application. The kernel can drive the IPC engine to save the information registered by the callee. For example, the registration process can be completed through a system call (such as callee list add instruction). The IPC engine forms a callee entry address through the callee register set according to the callee ID, and records the callee entry address. The ID number of the callee, which is associated with the callee entry address. It is understandable that different processes on the same server or different processes on different clients can be registered in the IPC engine. Each time a callee is registered, a callee entry address is added, and all these callee entry addresses can form a list ( callee list), the list points to the global DDR memory. So a callee entry address can be regarded as an entry in the list. The ID number of the callee can be used as the index of the entry.

Exemplarily, the ID number of the callee may be the process ID (processID, PID) of the callee.

S202. When the caller needs the service of the callee, the caller sends a service call instruction (ipccall) to the IPC engine. The call instruction includes the ID of the callee and the address of the data to be transferred (for example, it is recorded as msg address information). The address can be a virtual address.

In this step, since the information of various services has been pre-registered in the IPC engine, the caller can obtain from the IPC engine which services are available for use. As the user of the service, the client needs to use one or more callee services, it needs to apply to the IPC engine for the one or more services. At this time, the caller of the client can use the call command (ipccall) in the user layer to request the IPC engine service, and pass in the ID and related parameters of the callee corresponding to the service through the ipccall command. The related parameters include the data to be transferred to the callee. Address (referred to as the address of the data to be transferred), for example, the address of the data to be transferred is a virtual address (ie msg VA mentioned above).

It should be noted that the ipccall in this article can support the provision of synchronous or asynchronous invocation methods. The process of this method mainly takes the synchronous invocation method as an example to illustrate the solution.

S203. The IPC engine checks the conditions of the IPC communication between the caller and the callee.

In this step, in response to the ipccall from the caller, the IPC engine can perform various condition checks to verify whether the requirements for IPC communication are met. In a possible embodiment, the subsequent steps are executed only when the condition check passes, and if the condition check fails, the ipccall can be rejected.

1) Check whether caller and callee are at different execution levels.

It should be noted that this step is optional.

S204. The IPC engine records the indication information of the caller context information in the link register (link reg), and centrally records the entry address (msg entry address) of the data to be transferred through the message register.

In this step, the IPC engine can record the caller context information in the call stack pointed to by the link reg for later use when the caller needs to be restored. In addition, the IPC engine can record the msg entry address to the msg list through the message register set according to the msg address (for example, msg CA) passed in by the caller. The msg address passed in by the caller in a call instruction can be one or more. It is understandable that when the caller needs to communicate with one or more callees for IPC, the caller can respectively pass in the msg address information corresponding to different callees.

It should be noted that, in a possible implementation, this step can also be executed before step S203.

S205. The IPC engine finds the callee entry address through the callee register set according to the callee ID.

S206. The IPC engine performs process context switching according to the callee entry address to activate the callee.

In the embodiment of this application, since the callee ID and the callee entry address have a clear correspondence, the IPC engine can find the callee entry address in the callee list according to the ID passed in by the caller. For example, the callee entry address can be It is an address pointer of a callee, the address pointer of the callee points to the address of the callback function registered by the callee, and the callback function is used for the callee to execute the corresponding service. Then, the IPC engine can set the Program Counter (PC) in the CPU to the callee entry address, start executing the callee process context, and at this time the callee is activated to perform the corresponding service.

S207. The IPC engine determines the mapping relationship between the address (virtual address) of the data to be transferred and the memory address.

S208. The IPC engine transfers the address (virtual address) of the data to be transferred to the callee, and transfers the access right of the data to be transferred to the callee.

In some embodiments of the present application, in order to avoid copying of the data to be transferred in the IPC process, in the IPC engine, the data itself may not be directly transferred, but the transfer of the data is indirectly realized through the mapping (memory mapping) of the transferred data. , Without the need to copy data. As shown in Figure 8, a specific implementation scheme is to add a mapping mechanism for msg address space in the IPC engine so that msg data is only mapped between caller and callee. When the IPC engine is initialized, a part of the memory is allocated as shared memory, and a mapping table between the virtual address (VA) and the memory address (physical address) of msg is established, and the IPC engine can access such a mapping table. When the caller initiates an ipccall to the IPC engine, the IPC engine can find the PA by looking up the mapping table according to the incoming msg VA, and record the mapping relationship between the VA and the PA to realize the maintenance of the msg list. In this way, on the one hand, the IPC engine only needs to pass msg and VA to the callee without passing msg itself, avoiding the drawbacks of data replication and improving transmission efficiency. On the other hand, the IPC logic circuit of the IPC engine can control the access authority of msg by setting the query authority of the callee to the msg list maintained by the IPC engine. For example, when the caller needs to initiate an ipccall to the IPC engine, the operating system allocates memory to the caller based on the shared memory, that is, allocates a part of the memory space in the shared memory to the caller to save the data to be transferred (msg), and virtualize the data The address (VA) is indicated to the caller, and the access permission is set to be readable and writable by the caller, and the other processes/threads are not readable and writable. When the ipccall instruction is executed, after the permission check is passed, the IPC engine sets this part of the shared memory to callee readable according to the callee entry information, and other processes/threads cannot read or write. Specifically, for the callee corresponding to the callee ID passed in when the caller invokes the service, the IPC engine can enable the search permission in the context information of the callee, that is, the callee corresponding to the callee ID is allowed to use the VA to query the msg list maintained by the IPC engine. In this way, the access to msg is realized, or the callee can query the page table in the MMU according to the VA to obtain the PA corresponding to the VA, so as to realize the access to the msg. That is to realize the transfer of data access rights from caller to callee. For other callees, the search permission is closed by default, so other callees cannot query the msg list, which prevents other callees from illegally accessing data and improves the security and accuracy of data access.

In still other embodiments of the present application, different transmission modes can be configured for data of different lengths according to the length of the data to be transmitted, so as to improve the flexibility of data transmission.

An exemplary solution may be: configuring small data (the data length is less than a preset threshold, for example, less than 32 bytes) directly through the msg register copy and transfer. Configure large data (data length is greater than or equal to a preset threshold, for example, greater than or equal to 32 bytes) to be transmitted using a memory mapping scheme, and the access right of the data is transmitted to the callee through the IPC engine to complete the transmission process.

Another exemplary solution may be: if the data length is less than 32 bytes, it is directly transmitted through msg register copy during the process context switch; if the data length is greater than or equal to 32 bytes and less than the IPC buffer size (IPC BUF size, the size It can be customized, such as 128 bytes), and can be copied and transmitted through scheduling or interruption; if the data length is greater than the IPC buffer size (such as greater than 128 bytes), the memory mapping scheme is used for transmission, and the access of the data is transmitted through the IPC engine Right to callee to complete the transfer process.

It should be noted that this application does not limit the specific size of the preset threshold, and the above examples are only used to explain the solution of this application and not to limit it.

It should also be noted that there is no inevitable sequence between the above steps S205-S208.

S209. The callee obtains the data to be transferred and executes the services required by the caller.

In this step, the caller can obtain msg according to the access right of the data (for example, use the VA to query the msg list maintained by the IPC engine to achieve access to the msg), and call related functions to complete specific services. The services in the system service layer can be provided to applications in real time through the Manager provided by the application hierarchy framework layer. The service content can be, for example, messaging, communication, camera, or window usage, etc., which is not limited in this application.

S210. callee sends a return instruction (ipcret) to the IPC engine, where the return instruction can carry the execution result of the service.

S211. The IPC engine uses the link register to resume the execution of the caller.

In this step, when the callee completes the IPC processing, ipcret can be executed. In response to the ipcret, the IPC logic circuit of the IPC engine controls the link register (link reg) to pop up the last caller record, thereby switching to the caller context and restoring the state of the caller.

In order to better understand the specific solutions of the embodiments of the present application, the following further uses FIG. 9 as an example for description. In the figure, the instruction interaction between caller and callee is represented by a dotted line. The purpose is to show that caller and callee can implement service calls at the user layer. They are not really directly interacting, but through the IPC engine at the hardware layer as an intermediary. Interaction, so as to realize the IPC communication mode.

The IPC communication process after using the IPC engine is as follows: After the callee of the IPC service process is started, it registers to the IPC engine through the kernel driver, and the caller uses the ipccall instruction in the user layer to request the IPC engine service, and passes the corresponding callee ID and related to the IPC engine. The address of the parameter msg. The context information of the caller is recorded in the call stack pointed to by the link register of the IPC engine, and is used when the caller state needs to be restored. The msg is recorded in the continuous memory pointed to by the msg register. The IPC engine finds the callee entry address according to the ID passed in by the caller, and sets the program counter (PC) in the CPU to the callee entry address, and the CPU starts to switch to the process context of the callee. The IPC engine also passes the access rights of msg to the callee. In this way, callee can execute the corresponding service method. After the callee completes the IPC processing, it sends the ipcret instruction to the IPC engine, and the IPC engine controls the link register to pop up the caller record, thereby restoring the execution of the caller process. In the above IPC process, the event notification of the IPC engine can be reported to the kernel in an interrupt mode. For example, when an IPC engine is abnormal, it can be reported to the kernel by interruption, and for example, when the IPC processing is completed, the event can also be reported to the kernel by interruption.

It should be noted that, for the parts that are not described in detail in the embodiment of the method, please refer to the description of the related content above, such as the embodiments of FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, and FIG. Go into details.

It can be seen that the embodiment of this application transfers the context information preservation, context switching and restoration, data transfer, etc. in the user state from time and space to a new physical entity (ie, IPC engine), and the kernel driver assists in the completion in advance. Collee registration, IPC engine initialization, memory allocation, etc. After the caller actually initiates IPC, the IPC process does not require kernel participation, avoiding the drawbacks of frequent switching between user mode and kernel mode in the existing IPC mechanism (such as binder mechanism), and implement software It does not switch to the kernel mode. The IPC engine and CPU work in parallel on the hardware, thus freeing up a large amount of CPU software execution time. In order to cooperate with the interaction between the hardware form of the IPC engine and the process, it is also provided to the user mode used by the caller and callee. Processor instructions: ipccall and ipcret, to facilitate the call interface, thereby satisfying the service call of the caller and the callback of the callee, realizing the interaction of the process at the user mode level, ensuring the achievability of the IPC process, and greatly reducing the IPC process The overall delay. The implementation of the embodiments of the present application shows that the application test on the android platform can reduce the delay of the IPC process to 20 cycles, which significantly reduces the IPC delay compared to the prior art.

In addition, in the embodiments of the present application, the IPC engine can be used to transfer data (such as small data) or data access rights. Specifically, the IPC engine maps the msg memory of the data to be transferred to realize the transfer of data access rights without the need to transfer the data itself, thereby avoiding copying of data, further reducing the time delay of data copying, and improving data transmission efficient.

In addition, the implementation of the solution of the embodiment of this application can also realize that after the IPC engine is initialized, the operating system allocates shared memory, and the callee initiates registration and establishes the page table of the process, which is managed by the MMU. When the caller needs to call the service, the operating system is in The shared memory is allocated to the caller to store the memory segment of the generation transfer data (msg). The mapping relationship between the virtual address of msg and the physical address in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU. Therefore, follow-up In IPC communication, after the msg VA is passed from the caller to the callee through the IPC engine, the callee can access the page table to obtain the data according to the VA, thereby achieving the purpose of sharing memory between the caller and the callee, and avoiding the need for existing The MMU workflow is changed to avoid page faults and ensure the stability and security of IPC communication.

In the above-mentioned embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in an embodiment, reference may be made to related descriptions of other embodiments.

Claims

A hardware system for inter-process communication IPC, which is characterized by comprising: a processor core, IPC engine hardware and memory, wherein:

The processor core is used to configure a part of the memory space in the memory as the shared memory space of the process when the IPC engine hardware is initialized, and the shared memory space is used to store the to-be-transferred required for inter-process communication Data; a page table is established according to the starting address and length of the shared memory space, the page table contains the mapping relationship between the virtual address of the shared memory space and the physical address;

The processor core is also used to run a client process, and when the client process needs to call the service of the server process, send a first processor instruction to the IPC engine hardware, where the first processor instruction is A call instruction of the client process to the service, where the call instruction includes an identifier of the server process and a virtual address of the data to be transferred; the physical address of the data to be transferred is located in the shared memory space;

The IPC engine hardware is configured to instruct the processor core to run the server process according to the identifier, and send the virtual address of the data to be transferred to the server process;

The processor core is further configured to run the server process, and the server process queries the page table according to the virtual address of the data to be delivered to obtain the data to be delivered to execute the service; and The IPC engine hardware sends a second processor instruction, where the second processor instruction is a return instruction of the server process;

The IPC engine hardware is further configured to, according to the second processor instruction, instruct the processor core to resume running the client process.
The hardware system according to claim 1, wherein the processor core is further configured to allocate a portion of the shared memory space to the shared memory space when the client process needs to call the service of the server process The client process to save the data to be delivered.
The hardware system according to claim 1 or 2, characterized in that:

Before running the client process, the processor core is further configured to send registration information of the server process to the IPC engine hardware, where the registration information includes the identifier;

The IPC engine hardware is further configured to: receive the registration information; in response to the registration information, save the identifier and the entry address of the server process in the IPC engine hardware;

The IPC engine hardware is specifically configured to: find the entry address according to the identifier; set the entry address to a program counter (PC) in the processor core;

The processor core is further configured to run the server process according to the entry address set in the PC.
The hardware system according to any one of claims 1-3, wherein:

The IPC engine hardware is further configured to, after receiving the call instruction, query the status register in the processor core to obtain the call stack address of the client process, and save it in the IPC engine hardware The call stack address of the client process;

The IPC engine hardware is specifically configured to call up the call stack address according to the second processor instruction, and instruct the processor core to resume running the client process according to the call stack address.
The hardware system according to any one of claims 1-4, wherein:

The IPC engine hardware is specifically used to check whether the client process and the server meet the requirements of inter-process communication, and when the client process and the server meet the requirements of inter-process communication, according to the The identifier indicates that the processor core runs the server process.
The hardware system according to any one of claims 1-5, wherein:

The call instruction and the return instruction are both user mode instructions.
A method for inter-process communication IPC, which is characterized in that it includes:

When the IPC engine hardware is initialized, the processor core configures a part of the memory space in the memory as the shared memory space of the process, and the shared memory space is used to store the data to be transferred required for inter-process communication; A starting address and a length establish a page table, the page table containing a mapping relationship from virtual addresses to physical addresses of the shared memory space;

The processor core runs the client process, and when the client process needs to call the service of the server process, it sends a first processor instruction to the IPC engine hardware, and the first processor instruction is a pair of the client process The call instruction of the service, the call instruction includes the identifier of the server process and the virtual address of the data to be transferred; the physical address of the data to be transferred is located in the shared memory space;

The IPC engine hardware instructs the processor core to run the server process according to the identifier, and sends the virtual address of the data to be transferred to the server process;

The processor core runs the server process, and executes the service by querying the page table according to the virtual address of the data to be delivered by the server process to obtain the data to be delivered;

The processor core sends a second processor instruction to the IPC engine hardware, where the second processor instruction is a return instruction of the server process;

The IPC engine hardware instructs the processor core to resume running the client process according to the second processor instruction.
The method according to claim 1, wherein the method further comprises:

When the client process needs to call the service of the server process, the processor core allocates a part of the memory space in the shared memory space to the client process to save the data to be transferred.
The method according to claim 7 or 8, characterized in that, before the processor core runs the client process, the method further comprises:

Sending, by the processor core, registration information of the server process to the IPC engine hardware, where the registration information includes the identifier;

The IPC engine hardware receives the registration information; in response to the registration information, saves the identifier and the entry address of the server process in the IPC engine hardware;

Correspondingly, the IPC engine hardware instructs the processor core to run the server process according to the identifier, including:

The IPC engine finds the entry address according to the identifier; sets the entry address to the program counter (PC) in the processor core;

The processor core runs the server process according to the entry address set in the PC.
The method according to any one of claims 7-9, wherein after the processor core sends the first processor instruction to the IPC engine hardware, the method further comprises:

The IPC engine hardware queries the status register in the processor core to obtain the call stack address of the client process, and saves the call stack address of the client process in the IPC engine hardware;

Correspondingly, the IPC engine hardware instructs the processor core to resume running the client process according to the second processor instruction, including:

The IPC engine hardware calls the call stack address according to the second processor instruction, and instructs the processor core to resume running the client process according to the call stack address.
The method according to any one of claims 7-10, wherein before the IPC engine hardware instructs the processor core to run the server process according to the identifier, the method further comprises:

The IPC engine hardware checks whether the client process and the server meet the requirements of inter-process communication;

Correspondingly, the IPC engine hardware instructing the processor core to run the server process according to the identifier specifically includes:

When the client process and the server meet the requirements of inter-process communication, the IPC engine hardware instructs the processor core to run the server process according to the identifier.
The method according to any one of claims 7-11, wherein:

The call instruction and the return instruction are both user mode instructions.