WO2021196158A1

WO2021196158A1 - Data access circuit and method

Info

Publication number: WO2021196158A1
Application number: PCT/CN2020/083195
Authority: WO
Inventors: 王维伟; 罗飞
Original assignee: 北京希姆计算科技有限公司
Priority date: 2020-04-03
Filing date: 2020-04-03
Publication date: 2021-10-07
Also published as: CN115280272A

Abstract

Disclosed are a data access circuit and method. The data access circuit comprises: a plurality of internal memories; a first data interface circuit for connecting a first internal memory from among the plurality of internal memories to an external processing unit; a second data interface circuit for connecting a second internal memory from among the plurality of internal memories to an external memory; a first control circuit for receiving a first control instruction to control the first data interface circuit and the second data interface circuit; and a second control circuit for receiving a second control instruction to control a data transmission direction of the second data interface circuit. By means of controlling of the interface circuits by the control circuits in the data access circuit, the capacities and access efficiency of the internal memories are all improved, thereby solving the technical problems in the prior art of insufficient capacities of memories, low access efficiency of the memories, and complex circuits.

Description

Data access circuit and method

Technical field

The present disclosure relates to the field of data access, and in particular to a data access circuit and method.

Background technique

With the development of science and technology, human society is rapidly entering the era of intelligence. The important feature of the intelligent age is that people are getting more and more types of data, the amount of data is getting bigger and bigger, and the speed of processing data is getting higher and higher. The chip is the cornerstone of data processing, it is fundamentally determined Improved people’s ability to process data. From the perspective of application fields, there are two main routes for chips: one is a general-purpose chip route, such as the central processing unit (CPU), etc. They can provide great flexibility, but they are effective in processing algorithms in specific areas. The computing power is relatively low; the other is a dedicated chip route, such as Tensor Processing Unit (TPU), etc., which can play a higher effective computing power in some specific fields, but face flexible and changeable comparisons In general fields, they have poor processing capabilities or even can't handle them. Due to the wide variety and huge amount of data in the intelligent era, the chip is required to have extremely high flexibility, capable of processing different fields and rapidly changing algorithms, and extremely strong processing capabilities, which can quickly process extremely large and rapidly increasing data. quantity.

In neural network calculations, multi-core or many-core chips are often used. Here, the processing cores in the multi-core architecture all have a certain degree of independent processing capability, and have a relatively large internal storage space for storing their own programs, data, and weights. The basic computing power of a single processing core determines the ability of the entire chip to calculate neural networks. The performance of the basic computing power of a single processing core is determined by the ideal computing power and storage access efficiency of the computing unit of the single processing core.

Different storage units have different access speeds. Generally speaking, the access speed of the register is the fastest, accessing a few hundred ps (picosecond); followed by Static Random Access Memory (SRAM), the access speed is generally a few hundred ps to a few ns (nanosecond) Within the range of; again is the memory unit, that is, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), and its access speed is generally tens to hundreds of ns; finally, it is passed Other memories accessed by IO (input and output) ports, such as hard disks, have slow access speeds, generally in the ms (millisecond) level.

In the case of neural network processing, the general concern is the access of the processing unit to the memory unit. As we all know, the speed of the processing unit is very fast, and its main frequency is generally several hundred MHz (megahertz) to several GHz (gigahertz), that is, ps to ns level, and the access speed of the memory unit is tens of ns level, both There is a big difference in speed. How to solve the speed difference between the processing unit and the memory access, and effectively utilize the computing power of the processing unit, is a difficult point in modern CPU design.

In order to solve the problem of speed matching between the processing unit and the memory unit, the solution in FIG. 1 is generally used in the prior art. As shown in Figure 1, PU (Processing Unit) is a processing unit, Cache is a high-speed cache, and Memory is a memory. In this solution, a high-speed cache Cache is inserted between the processing unit PU and the memory Memory. The PU accesses the Memory in a hierarchical and indirect manner. It directly accesses the Cache and indirectly accesses the Memory through the Cache. In this scheme, Cache is a mapping of Memory, and its content is a subset of memory content. It is transparent to the program run by the PU, has no functional significance, and has no independent addressing space. Its address is the same as the memory address accessed, that is, the program cannot access the Cache alone.

For the above-mentioned existing solutions, due to the huge amount of parameters and data used in neural network calculations, they usually far exceed the capacity of the Cache. In this way, the measures taken by Cache to reduce the access failure rate based on the temporal and spatial local characteristics of data will not be realized, which greatly reduces the computing power of the processing unit; and because the Cache circuit is complex, the chip design is greatly improved. Difficulty and cost of the chip.

Summary of the invention

The content of the invention is provided in order to introduce concepts in a brief form, and these concepts will be described in detail in the following specific embodiments. The content of the invention is not intended to identify the key features or essential features of the technical solution required to be protected, nor is it intended to be used to limit the scope of the technical solution required to be protected.

In order to solve the technical problems of insufficient capacity of the cache when the amount of data is large and complicated circuits in the prior art, the embodiments of the present disclosure propose the following technical solutions:

In the first aspect, embodiments of the present disclosure provide a data access circuit, including:

Multiple internal memories;

A first data interface circuit, configured to connect a first internal memory of the plurality of internal memories with an external processing unit;

A second data interface circuit for connecting a second internal memory of the plurality of internal memories with an external memory;

The first control circuit is configured to receive a first control instruction to control the first data interface circuit and the second data interface circuit;

The second control circuit is configured to receive a second control instruction to control the data transmission direction of the second data interface circuit.

Further, the addresses of the multiple internal memories are the same.

Further, the first data interface circuit includes:

A first switch circuit, the first switch circuit includes a plurality of connection states, wherein each connection state is used to connect the processing unit with one of the plurality of internal memories.

Further, the second data interface circuit includes:

A second switch circuit, the second switch circuit includes a plurality of connection states, wherein each connection state is used to connect the external memory with one of the plurality of internal memories.

Further, the second data interface circuit further includes:

A storage controller, which is connected between the external storage and the plurality of internal storages, and is used to control the data exchange between the external storage and the plurality of internal storages.

Further, the first control circuit includes:

The switch control circuit is used to receive a first control instruction sent by the external processing unit to generate a first switch control signal and a second switch control signal, wherein the first switch control signal is used to set the first switch circuit The connection state, the second switch control signal is used to set the connection state of the second switch circuit.

Further, the second control circuit includes:

An access control circuit, which is used to receive a second control instruction sent by the external processing unit to generate a control signal, wherein the control signal is used to control the storage controller to fetch the control from the second internal memory The data indicated by the signal is stored in the external memory, or the storage controller is controlled to fetch the data indicated by the control signal from the external memory and store it in the second internal memory.

Further, the multiple internal memories and the external memory are uniformly addressed.

In a second aspect, embodiments of the present disclosure provide a data access method, which is characterized in that it includes:

Receiving a first control instruction to determine a first internal memory connected to the external processing unit and a second internal memory connected to the external memory;

Receiving a second control instruction to determine the data transfer direction between the external memory and the second internal memory;

The external processing unit obtains data from the first internal memory or sends data to the first internal memory;

According to the data transfer direction, the data in the second internal memory is sent to the external memory or the data obtained from the external memory is stored in the second internal memory.

In a third aspect, embodiments of the present disclosure provide a data access device, including:

At least one data access circuit as described in any one of the first aspect.

In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including: a memory, configured to store computer-readable instructions; and one or more processors, configured to execute the computer-readable instructions to cause the processor to run The data access method described in any one of the foregoing second aspects is realized at a time.

In a fifth aspect, embodiments of the present disclosure provide a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to make a computer execute the aforementioned second aspect Any of the data access methods described above.

In a sixth aspect, embodiments of the present disclosure provide a computer program product, wherein the computer program product is characterized by including computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute any of the foregoing second aspects. The data processing method.

In a seventh aspect, an embodiment of the present disclosure provides a chip characterized by comprising at least one data processing device described in the third aspect.

In an eighth aspect, an embodiment of the present disclosure provides a computing device, which is characterized in that it includes at least one chip as described in the seventh aspect.

The embodiment of the present disclosure discloses a data access circuit and method. The data processing circuit includes: a plurality of internal memories; a first data interface circuit for connecting the first internal memory of the plurality of internal memories with a processing unit outside the memory management circuit; and a second data interface A circuit for connecting a second internal memory of the plurality of internal memories with an external memory; a first control circuit for receiving a first control instruction to control the first data interface circuit and the second data Interface circuit; a second control circuit for receiving a second control instruction to control the data transmission direction of the second data interface circuit. By controlling the interface circuit by the control circuit in the data access circuit, the capacity and access efficiency of the internal memory are improved, and the technical problems of insufficient memory capacity, low access efficiency and circuit complexity in the prior art are solved.

The above description is only an overview of the technical solutions of the present disclosure. In order to understand the technical means of the present disclosure more clearly, they can be implemented in accordance with the content of the specification, and to make the above and other objectives, features and advantages of the present disclosure more obvious and understandable. In the following, the preferred embodiments are cited in conjunction with the drawings, and the detailed description is as follows.

Description of the drawings

The above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent in conjunction with the accompanying drawings and with reference to the following specific implementations. Throughout the drawings, the same or similar reference signs indicate the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

Figure 1 is a schematic structural diagram of a processing scheme in the prior art;

2 is a schematic diagram of an application scenario of a data access circuit in an embodiment of the disclosure;

3a is a schematic diagram of the structure of a data access circuit in an embodiment of the disclosure;

3b is a schematic diagram of a specific structure of a data access circuit in an embodiment of the disclosure;

4 is a schematic flowchart of a data access method in an embodiment of the disclosure;

5 is a schematic flowchart of another data access method in an embodiment of the disclosure;

6 is a schematic flowchart of another data access method in an embodiment of the disclosure;

FIG. 7 is a schematic diagram of an actual application scenario of an embodiment of the disclosure;

Fig. 8 is a sequence diagram of neural network calculations using an embodiment of the present disclosure.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided for Have a more thorough and complete understanding of this disclosure. It should be understood that the drawings and embodiments of the present disclosure are only used for exemplary purposes, and are not used to limit the protection scope of the present disclosure.

It should be understood that the various steps recorded in the method embodiments of the present disclosure may be executed in a different order, and/or executed in parallel. In addition, method implementations may include additional steps and/or omit to perform the illustrated steps. The scope of the present disclosure is not limited in this respect.

The term "including" and its variations as used herein are open-ended includes, that is, "including but not limited to". The term "based on" is "based at least in part on." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Related definitions of other terms will be given in the following description.

It should be noted that the concepts of “first” and “second” mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units. Or interdependence.

It should be noted that the modifications of “a” and “a plurality of” mentioned in the present disclosure are illustrative and not restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as “one or Multiple".

The names of messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes, and are not used to limit the scope of these messages or information.

FIG. 2 is a schematic diagram of an application scenario of a data access circuit in an embodiment of the disclosure. Fig. 2 shows a data access device including the data access circuit of the present disclosure. The device includes a processing unit PU, a data access circuit, and an external memory Memory. The data access circuit is located between the PU and the Memory, and is responsible for data transfer between the PU and the Memory.

FIG. 3a is a schematic diagram of the structure of a data access circuit in an embodiment of the disclosure. As shown in FIG. 3, the data access circuit 300 includes: a plurality of internal memories 301; a first data interface circuit 302 for managing the first internal memory and the memory among the plurality of internal memories 301 The processing unit PU outside the circuit is connected; the second data interface circuit 303 is used to connect the second internal memory of the plurality of internal memories 301 with the external memory Memory; the first control circuit 304 is used to receive the first The control instruction is used to control the first data interface circuit 302 and the second data interface circuit 303; the second control circuit 305 is used to receive a second control instruction to control the data transmission direction of the second data interface circuit 303.

Exemplarily, the multiple internal memories are random access memory RAM, which can directly exchange data with the processor. It is understandable that although only two internal memories are shown in FIG. 3, the number of internal memories in practical applications It can be set arbitrarily, so I won't repeat it here.

The first data interface circuit 302, under the control of the first control circuit 304, determines at least one first internal memory from the plurality of internal memories 301 to connect it with the external processing unit, so that the Data transmission can be performed between the first internal memory and the external processing unit PU; the second data interface circuit 303, under the control of the first control circuit 304, determines at least one from the plurality of internal memories 301 The second internal memory is connected to the external memory, so that data transmission can be performed between the second internal memory and the external memory. The first control circuit 304 receives a first control instruction to control the first data interface circuit 302 and the second data interface circuit 303. Optionally, the first control instruction is issued by the external processing unit, so The first control circuit 304, after receiving the first control instruction, undergoes decoding and execution, and configures the first data interface circuit 302 and the second data interface circuit 303 according to the parameters in the first control instruction, The first data interface circuit 302 is made to communicate with the corresponding first internal memory and the external processing unit, and the second data interface circuit 303 is obtained to communicate with the corresponding second internal memory and the external processing unit.

The second data interface circuit 303 determines the data transfer direction of the second data interface circuit under the control of the second control circuit 305, that is, sends data from the second internal memory to the external memory or from the outside. The acquired data in the memory is stored in the second internal memory.

It can be understood that the first internal memory and the second internal memory may be the same memory, that is, the external processing unit and the external memory are connected to the same internal memory.

Optionally, the first data interface circuit 302 includes: a first switch circuit, the first switch circuit includes a plurality of connection states, wherein each connection state is used to connect the processing unit to the plurality of internal memories One of the connections. FIG. 3b is a schematic diagram of a specific structure of a data access circuit in an embodiment of the disclosure. Exemplarily, as shown in FIG. 3b, the first data interface circuit 302 includes a first switch circuit SW_1, wherein the connection state in the first switch circuit SW_1 is the same as the number of internal memories, as shown in the example in FIG. 3b As shown, the internal memory includes two E_RAM and O_RAM, so the first switch circuit SW_1 includes two connection states of 0 and 1, respectively used to connect E_RAM and O_RAM, and the two connection states are both connected to the external processing unit, so that the first The switch circuit SW_1 can only be in one connection state at a time to connect the external processing unit and the internal storage unit.

Optionally, the second data interface circuit 303 includes: a second switch circuit, the second switch circuit includes a plurality of connection states, wherein each connection state is used to connect the external memory to the plurality of internal memories. One of the connections. Exemplarily, as shown in FIG. 3b, the second data interface circuit 303 includes a second switch circuit SW_2, and the connection state in the first switch circuit SW_2 is the same as the number of internal memories, as shown in FIG. 3b As shown in the example, the internal memory includes two E_RAM and O_RAM, so the first switch circuit SW_2 includes two connection states of 0 and 1, respectively used to connect E_RAM and O_RAM, and the two connection states are both connected to the external memory, so that the first The switch circuit SW_2 can only be in one connection state at a time to connect the external memory and the internal memory unit.

Optionally, the second data interface circuit 303 further includes a storage controller connected between the external storage and the multiple internal storages, and configured to control the external storage and the internal storages. The data exchange between multiple internal memories. Exemplarily, as shown in FIG. 3b, the second data interface circuit 303 further includes a memory controller DMAC, which is located between the external memory and the plurality of internal memories, specifically, connected to the second switch circuit SW_1 and Between external memories, used to control the data exchange between the external memory and the multiple internal memories, that is, control data from the external memory to the multiple internal memories or control data from the multiple internal memories To the external storage.

Optionally, the first control circuit 304 includes: a switch control circuit for receiving a first control instruction sent by the external processing unit to generate a first switch control signal and a second switch control signal, wherein the first switch control signal A switch control signal is used to set the connection state of the first switch circuit, and the second switch control signal is used to set the connection state of the second switch circuit. Exemplarily, as shown in FIG. 3b, the first control circuit 304 includes a switch control circuit SW_ctrl, which receives the first control command ISW_dis sent by the external processing unit PU, and after receiving the first control command Isw_dis, It is decoded and executed to generate a first switch control signal C_SW1 and a second switch control signal C_SW2, wherein the first control instruction includes parameters for controlling the first switch and the second switch to indicate the current moment of the first switch and In which connection state the second switch should be, the first switch control signal C_SW1 and the second switch control signal C_SW2 can be generated to respectively set the connection state of the first switch SW_1 and the second switch SW_2, so that the external processing unit can be determined separately The internal storage unit connected to the PU at this time and the internal storage unit connected to the external memory are as shown in the example of FIG. 3b. At this time, the external processing unit PU is connected to E_RAM, and the external memory Memory is connected to O_RAM.

Optionally, the second control circuit 305 includes: an access control circuit, which is configured to receive a second control instruction sent by the external processing unit to generate a control signal, wherein the control signal is used to control the storage control The device fetches the data indicated by the control signal from the second internal memory and stores it in the external memory, or controls the storage controller to fetch the data indicated by the control signal from the external memory and store it in the external memory. The second internal memory. Exemplarily, as shown in FIG. 3b, the second control circuit 305 includes an access control circuit LS_mem_ctrl, which receives the second control command Ils_dis sent by the external processing unit PU, and after receiving the second control command Ils_dis , It is decoded and executed to generate the control signal C_DMAC, wherein the second control instruction Ils_dis includes the fetch instruction ld_mem instruction that fetches the data from the external memory Memory and stores it in the internal memory RAM and stores the data in the internal memory RAM St_mem instruction to the external memory Memory; the control signal C_DMAC is used to configure and start the memory controller DMAC according to the parameters in the second control instruction to control the memory controller DMAC to fetch from the internal memory O_RAM The data indicated by the control signal C_DMAC is stored in the external memory Memory, or the memory controller DMAC is controlled to fetch the data indicated by the control signal C_DMAC from the external memory Memory and store it in the internal memory O_RAM.

In the above embodiment, the first switch circuit and the second switch circuit are two independent circuits, and the connection state of the switch control circuit is controlled, so that the external processing unit PU accesses the internal memory RAM through the first switch circuit, so that the storage controller The DMAC accesses the internal memory RAM through the second switch circuit, and the two can run independently and in parallel.

In the embodiment of the present disclosure, the addresses of the multiple internal memories are the same, so that every time the PU accesses an internal memory, its addressing space is unchanged; and the internal memory can be addressed uniformly with the external memory, for example The address range of the low address is allocated to the internal memory RAM, and the address range of the high address is allocated to the external memory Memory. For the external processing unit PU, it only needs to access the address of the internal memory RAM, so its access address range is limited to the internal memory RAM; and for the memory controller DMAC, it needs to access both the internal memory RAM and the external Memory, so its access address range is the full address range of the internal memory and external memory unified addressing. In this way, when the external memory PU reads and writes to the internal memory, it uses the same address. From the perspective of the external processor PU, it always uses the same internal memory RAM, which does not distinguish which internal memory RAM. ; Similarly, for the memory controller DMAC, it also uses an address (such as the low address range of uniform addressing), so it does not need to distinguish which specific internal memory, so there is no need to consider calculation and storage For the parallel execution of the program, the traditional serial program can be written when the program is written, which can greatly reduce the complexity of the program.

FIG. 4 is a schematic flowchart of a data access method in an embodiment of the disclosure. As shown in Figure 4, the data access method includes:

Step S401, receiving a first control instruction to determine a first internal memory connected to an external processing unit from a plurality of internal memories;

Step S402: The external processing unit obtains data from the first internal memory or sends data to the first internal memory.

In step S401, after receiving the first control instruction sent by the external processing unit PU to the data access circuit 300, the switch control circuit of the data access circuit decodes it and executes the control signal to generate the first switch to The connection state of the first switch circuit is controlled so that the external processing unit is connected to the first internal memory of the plurality of internal memories; after that, in step S402, the external processing unit performs its arithmetic operation, from the The first temporal memory acquires data or sends data to the internal memory.

FIG. 5 is a schematic flowchart of another data access method in an embodiment of the disclosure. As shown in FIG. 5, the data access method includes:

Step S501, receiving a first control instruction to determine a second internal memory connected to an external memory from a plurality of internal memories;

Step S502, receiving a second control instruction to determine the data transfer direction between the external memory and the second internal memory;

Step S503: According to the data transfer direction, the data in the second internal memory is sent to the external memory or the data obtained from the external memory is stored in the second internal memory.

In the step S501, after receiving the first control instruction sent by the external processing unit PU to the data access circuit 300, the switch control circuit of the data access circuit decodes it and executes the control signal to generate the second switch, In order to control the connection state of the second switch circuit, the external processing unit is connected to the second internal memory of the plurality of internal memories; then, in step S502, the access control circuit of the data access circuit is receiving After the external processing unit PU sends the first control instruction to the data access circuit 300, it is decoded and executed to generate a control signal for controlling the storage controller to determine the data transfer between the external memory and the second internal memory Direction; then in step S503, the storage controller sends the data indicated in the second control instruction from the second internal storage to the external storage or from the external storage according to the data transfer direction The data indicated in the second control instruction is acquired from the external memory and stored in the internal memory.

The above two data access methods are methods independently executed by the circuits at both ends of the data access circuit, which can be executed independently and in parallel, and the two methods can also be put together to complete more complex data access tasks.

Therefore, the embodiments of the present disclosure also provide a data access method, including:

Step S601, receiving a first control instruction to determine a first internal memory connected to the external processing unit and a second internal memory connected to the external memory;

Step S602, receiving a second control instruction to determine the data transfer direction between the external memory and the second internal memory;

Step S603: The external processing unit obtains data from the first internal memory or sends data to the first internal memory;

Step S604: According to the data transfer direction, the data in the second internal memory is sent to the external memory or the data obtained from the external memory is stored in the second internal memory.

An example of the above method is as follows: as shown in FIG. 3b, the external processor PU sends a first control instruction Isw_dis to the data access circuit 300, and the switch control circuit of the data access circuit receives the instruction and generates a first switch control signal SW_1 and the second switch control signal SW_2, where SW_1 controls the connection state of the first switch to 0, so that the external processing unit is connected to E_RAM, and SW_2 controls the connection state of the second switch to 1, so that DAMC is connected to O_RAM. After that, the external processing unit PU sends a second control command Ils_dis to the data access circuit 300, where Ils_dis is the fetch command ld_mem. After the access control circuit of the data access circuit 300 receives the command ld_mem, it performs Decode and execute the control signal C_DMAC of the memory controller DMAC to configure the read address, write address, and data size of the DMAC to transfer the data block determined by the instruction ld_mem from the external memory Memory The storage area of the read address is read out and written into the storage area of the write address of O_RAM, where both the read address and the write address may be the first address. At the same time, the external processing unit PU can execute its own instruction, the operand of the instruction is read from E_RAM, or the execution result data of the instruction is stored in E_RAM.

FIG. 7 is a schematic diagram of an actual application scenario of an embodiment of the disclosure. The data access circuit in the embodiment of the present disclosure is used to make the external processing unit PU execute the calculation of the neural network. Figure 7 shows a schematic diagram of the neural network. The neural network has two layers. The parameters and data used by the neural network of each layer are smaller than the capacity of a single block of RAM, that is, E_RAM and O_RAM can accommodate one The parameters and data calculated by the layered neural network. Among them, E_RAM corresponds to the first layer of neural network layer1, and O_RAM corresponds to the second layer of neural network layer2, so the external processing unit PU can switch between E_RAM and O_RAM at different times to execute the two-layer neural network program.

Fig. 8 is a sequence diagram of neural network calculations using an embodiment of the present disclosure. As shown in Figure 8, at time t0, the first switch circuit selects E_RAM to connect with PU, and the second switch circuit selects O_RAM to connect with DMAC. At this time, PU obtains and calculates the operand of layer1 through E_RAM and performs the calculation of layer1, or calculates The result of layer1 is stored in E_RAM. DMAC updates the data in O_RAM according to the second control instruction of the PU, such as storing the data in Memory in O_RAM; at t1, the PU issues the first control instruction, and the control switch controls the first The switch control signal and the second switch control signal are used to control the first switch circuit to select O_RAM and the second switch circuit to select E_RAM. At this time, the PU obtains and calculates the operand of layer2 through O_RAM and executes the calculation of layer2, or saves the result of calculation of layer2 To O_RAM, the DMAC updates the data in E_RAM according to the second control instruction of the PU, such as storing the data in Memory in E_RAM; at t2, the PU sends out the first control instruction, and controls the switch to generate the first switch control signal and The second switch control signal controls the first switch circuit to select E_RAM and the second switch circuit to select O_RAM. At this time, the PU obtains and calculates the operand of layer1 through E_RAM and executes the calculation of layer1, or saves the result of calculating layer1 in E_RAM, DMAC updates the data in O_RAM according to the second control instruction of the PU, such as storing the data in Memory in O_RAM. This cycle alternates until the calculation task of the neural network is completed.

It can be seen from Figure 8 that when E_RAM is occupied by the calculation of the PU, O_RAM is simultaneously updating the parameters and data of the next calculation; in the same way, when O_RAM is occupied by the calculation of the PU, E_RAM is also performing the next calculation of the parameters. And data update. In this way, calculations and parameter/data updates are performed in parallel, which can maximize computing power.

It is understandable that in the above calculation process, the RAM may not be switched, so that the calculation and the parameter/data update are performed on the same block of RAM, so that the calculation and storage will be performed serially on the same block of RAM.

An embodiment of the present disclosure also provides a data access device, which is characterized by comprising: at least one data access circuit as described in any of the above embodiments.

The data access device is, for example, a processing core.

An embodiment of the present disclosure also provides a chip, which is characterized by including at least one data access circuit as described in any of the above embodiments.

The embodiments of the present disclosure provide a computer program product, which is characterized in that it includes computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute any of the data accesses in the foregoing embodiments. method.

The embodiments of the present disclosure provide a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to make a computer execute any of the foregoing third aspects. The data access method.

An embodiment of the present disclosure provides a computing device, which is characterized by comprising at least one chip described in any one of the foregoing embodiments.

The flowcharts and block diagrams in the drawings of the present disclosure illustrate the possible implementation architecture, functions, and operations of the system, method, and computer program product according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram can represent a module, program segment, or part of code, and the module, program segment, or part of code contains one or more for realizing the specified logic function. Executable instructions. It should also be noted that, in some alternative implementations, the functions marked in the block may also occur in a different order from the order marked in the drawings. For example, two blocks shown one after another can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and/or flowchart, and the combination of the blocks in the block diagram and/or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations Or it can be realized by a combination of dedicated hardware and computer instructions.

The units involved in the embodiments described in the present disclosure can be implemented in software or hardware. Among them, the name of the unit does not constitute a limitation on the unit itself under certain circumstances.

The functions described above in this document may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), Application Specific Standard Product (ASSP), System on Chip (SOC), Complex Programmable Logical device (CPLD) and so on.

In the context of the present disclosure, a machine-readable medium may be a tangible medium, which may contain or store a program for use by the instruction execution system, apparatus, or device or in combination with the instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the foregoing.

Claims

A data access circuit, characterized in that it comprises:

Multiple internal memories;

A first data interface circuit, configured to connect a first internal memory of the plurality of internal memories with an external processing unit;

A second data interface circuit for connecting a second internal memory of the plurality of internal memories with an external memory;

The first control circuit is configured to receive a first control instruction to control the first data interface circuit and the second data interface circuit;

The second control circuit is configured to receive a second control instruction to control the data transmission direction of the second data interface circuit.
The data access circuit according to claim 1, wherein the addresses of the plurality of internal memories are the same.
3. The data access circuit according to claim 1 or 2, wherein the first data interface circuit comprises:

A first switch circuit, the first switch circuit includes a plurality of connection states, wherein each connection state is used to connect the processing unit with one of the plurality of internal memories.
3. The data access circuit according to any one of claims 1-3, wherein the second data interface circuit comprises:

A second switch circuit, the second switch circuit includes a plurality of connection states, wherein each connection state is used to connect the external memory with one of the plurality of internal memories.
5. The data access circuit of claim 4, wherein the second data interface circuit further comprises:

A storage controller, which is connected between the external storage and the plurality of internal storages, and is used to control the data exchange between the external storage and the plurality of internal storages.
5. The data access circuit according to any one of claims 1 to 4, wherein the first control circuit comprises:

The switch control circuit is used to receive a first control instruction sent by the external processing unit to generate a first switch control signal and a second switch control signal, wherein the first switch control signal is used to set the first switch circuit The connection state, the second switch control signal is used to set the connection state of the second switch circuit.
5. The data access circuit according to any one of claims 1 to 6, wherein the second control circuit comprises:

An access control circuit, which is used to receive a second control instruction sent by the external processing unit to generate a control signal, wherein the control signal is used to control the storage controller to fetch the control from the second internal memory The data indicated by the signal is stored in the external memory, or the storage controller is controlled to fetch the data indicated by the control signal from the external memory and store it in the second internal memory.
3. The data access circuit according to claim 1, wherein the plurality of internal memories and the external memory are uniformly addressed.
A data access method, characterized in that it comprises:

Receiving a first control instruction to determine a first internal memory connected to the external processing unit and a second internal memory connected to the external memory;

Receiving a second control instruction to determine the data transfer direction between the external memory and the second internal memory;

The external processing unit obtains data from the first internal memory or sends data to the first internal memory;

According to the data transfer direction, the data in the second internal memory is sent to the external memory or the data obtained from the external memory is stored in the second internal memory.
A chip comprising at least one data access circuit according to any one of claims 1-8.