WO2021149836A1

WO2021149836A1 - Semiconductor apparatus, and inspection device for same

Info

Publication number: WO2021149836A1
Application number: PCT/JP2021/002927
Authority: WO
Inventors: 軍生木本
Original assignee: 軍生木本
Priority date: 2020-01-21
Filing date: 2021-01-20
Publication date: 2021-07-29
Also published as: JP2021118341A

Abstract

Provided is a high-density IC package with which wiring without discontinuity is possible from narrow-pitch IC chip terminals to a device PCB, and which lowers the cost of manufacturing and inspection. The present invention has a means comprising at least one wiring pattern sheet formed from a plurality of conductive patterns fixed to a first insulation film, in which: the wiring pattern sheet is positioned vertically; the parts of the plurality of conductive patterns that are at the terminals thereof serving as the opening terminal in the wiring pattern sheet are positioned in a row in the X direction; the center-to-center distance, in the X direction, of the conductive pattern opening terminals is the same as the center-to-center distance, in the X direction, of terminals arranged in the X direction in a given row in the semiconductor device; and the center-to-center distance, in the Y direction, of the conductive pattern opening terminals in a plurality of the vertically positioned wiring pattern sheets is the same as the center-to-center distance, in the Y direction, of terminals arranged in the Y direction in the semiconductor device.

Description

Semiconductor equipment and its inspection equipment

The present invention relates to a semiconductor device having a plurality of semiconductor chips and wiring patterns, and an inspection device thereof.

With the advent of IoT, AI, and 5G societies, semiconductors that should be applied to these are required to have multiple functions, higher functions, smaller sizes, and lower prices. In order to meet such demands, various semiconductor device mounting forms have been introduced. Vertical wiring by Through-Silicon Via (TSV), which is called three-dimensional (3D) lamination, is mainly used for connection between ICs of the same type such as DRAM. On the other hand, as a connection technology between different types of ICs, a method called 2.5-dimensional (2.5D) stacking is common, and a plurality of different types of ICs are mounted on the same package surface and systematized to form a single device chip. This is called System IN a Package (SiP: system in package).
As a packaging technology that realizes further high density and miniaturization of SiP, the upper and lower parts can be made conductive by TSV technology, and an interposer based on silicon with fine wiring is connected to the fine terminals on the IC chip side. As a wiring means, a method of connecting to the device PCB side with a build-up wiring board or the like made of an organic base material is often adopted (Patent Document 1). FIG. 8A shows a typical structure thereof. As a means for mounting an IC chip 50 equipped with a multi-pin narrow pitch terminal and connecting wiring, a silicon interposer 101 in which a fine wiring 103 is produced by a wafer process is used as a primary wiring board, and the fine wiring 103 is wired to the back surface of the silicon interposer. The TSV 104 is installed as a means and is connected to the organic substrate 102 which is a secondary wiring means. The organic substrate 102 is further expanded and distributed by an expansion wiring 105, a through hole 106, or the like, and is connected to an external device by a solder ball 107 or the like.
Furthermore, high-density wiring technology using silicon substrates is applied only to high-density signal connections between multiple ICs called silicon bridges, those silicon substrates are embedded in organic material substrates, and power supply / device interface signals are organic. A method of wiring in a substrate and the like (Patent Document 2) have been put into practical use. As shown in FIG. 8B, a partially manufactured silicon substrate 101 to which only the fine wiring portion 103 is applied is built in the organic substrate 102.
As described above, as means for realizing high density and miniaturization of SiP, a thin film process as a means for realizing fine terminal connection and fine rewiring on the IC chip side, and TSV technology as a means for transmitting upper and lower silicon substrates. , The mainstream is the selection and combination of build-up organic substrate technology and the like as a means for widening the wiring pitch and connecting to the PCB terminal of the device.
On the other hand, the author has so far formed a conductive pattern on an insulating film by electrocasting technology or the like, and arranged one end as a probe for connecting to an IC terminal and the other end as a terminal for connecting to a PCB side. We have devised a probe unit and a probe card that are manufactured as parts and have a direct wiring from the high-density terminal on the IC side to the PCB terminal on the device side, along with the probing technology of an IC having an area array type multi-pin narrow pitch terminal (Patent Document). 3). We thought that this technology would be effective not only for inspection technology but also for packaging technology.

Japanese Unexamined Patent Publication No. 2009-110983 Japanese Unexamined Patent Publication No. 2014-179613 JP-A-2019-194554

However, the features and problems of the conventional methods represented by Patent Document 1 or Patent Document 2 are as shown below.
It is based on pattern wiring on the same plane as the IC terminal arrangement plane and their multi-layer board configuration. Therefore, as the number of ICs to be mounted increases or the number of input / output (I / O) terminals increases and the density increases, the number of wires between the terminals must be increased or the number of layers must be increased. This leads to an increase in manufacturing cost.
Further, in order to increase the number of wirings between terminals, it is necessary to miniaturize the wirings (for example, a wiring width of 2 μm class), and for that purpose, a manufacturing process by a wafer process must be used, and a table on a silicon substrate is used. TSV technology is indispensable as a connection means on the back surface, which leads to an increase in manufacturing cost and a decrease in yield.
In addition, by combining a wiring board based on wafer process or TSV technology with a board based on organic substrate technology, it leads to deterioration of characteristics, increase in manufacturing cost, and longer delivery time of development and manufacturing due to the mixture of different manufacturing processes. There is.
Further, since the inspection system and the manufacturing system are independent for inspection before and after IC stacking, there is a problem of an increase in disposal cost due to the occurrence of defects after IC stacking.
The present invention solves the above-mentioned problems by a completely new method, and as a method thereof, by wiring on a substrate arranged in a direction perpendicular to the IC terminal arrangement plane, via via connection in a multilayer wiring board or the like. Wiring without discontinuity is possible from the IC chip to the terminal on the device side.
In addition, since the wiring board is manufactured by a manufacturing method that does not use the wafer process and TSV technology, it is possible to collectively manufacture all wiring with a single manufacturing technology, reducing manufacturing costs and stabilizing characteristics. Can be realized.
Furthermore, a wiring method without discontinuities from high-density wiring to device-side wiring has already been implemented with a probe card using the same manufacturing technology, and the probe and IC package for inspection during IC stacking are manufactured with the same parts. Therefore, it is possible to detect and dispose of the defective IC in advance before fixing the package, reduce the disposal cost, and manufacture a low-cost product.
By these methods, a high-density IC package that realizes cost reduction in both manufacturing and inspection is provided.

In the present invention, for any one common X-direction array terminal group in any one or a plurality of semiconductor devices, one wiring board arranged on an XZ plane is electrically connected between the plurality of the semiconductor devices. One or a plurality of the semiconductor devices on one or a plurality of wiring boards arranged on an XY plane, a wiring circuit for electrically connecting an arbitrary semiconductor device and an external device terminal, and one or a plurality of the semiconductor devices. Since it has a wiring circuit that electrically connects the terminals, in an IC package that mounts and connects multiple ICs with multi-pin narrow pitch terminals, high-density wiring between ICs and high-density wiring near the ICs. Since the extended wiring from the to the vicinity of the PCB can be formed by the same wiring pattern sheet, a low-cost package can be realized.
Further, the present invention includes a first wiring pattern sheet composed of a plurality of conductive patterns fixed on at least one or a plurality of first insulating films, and a second wiring pattern sheet installed parallel to the XY coordinate plane. The semiconductor comprises one or a plurality of positioning sheets provided with positioning holes in the insulating film of No. 1 and a connection sheet having a connection terminal portion in a third insulating film installed on the upper portion of the positioning sheet parallel to the XY coordinate plane. A device mounting terminal array forming means, a semiconductor device mounting fixing means, a wiring circuit forming means for electrically connecting the semiconductor device terminals, and an arbitrary semiconductor device and an external device terminal are electrically connected. Since it has a wiring circuit forming means, in an IC package in which a plurality of ICs having multi-pin narrow pitch terminals are mounted and connected by wiring, high-density wiring between ICs and expansion from high-density wiring near ICs to near PCBs. Since the wiring can be formed by the same wiring pattern sheet, a low-cost package can be realized.
Further, the present invention is made on a first wiring pattern sheet composed of a plurality of conductive patterns fixed on one or a plurality of first insulating films and on one or a plurality of fourth insulating films. Since it is composed of a plurality of fixed conductive patterns and has a second wiring pattern sheet installed under the first wiring pattern sheet in parallel with the XY coordinate plane, the semiconductor device terminals are spaced between the plurality of semiconductor device terminals. It can be electrically connected on the XY plane.
Further, in the present invention, a part of one or more of the first wiring pattern sheets is installed in the vertical direction (XZ plane), and one end of the first wiring pattern sheet installed in the vertical direction is an open end. A part of the plurality of conductive patterns is arranged in parallel in the X direction, and a part or all of the conductive pattern open end center in any one of the first wiring pattern sheets installed in the vertical direction. The X-direction distance of the position is the same as the X-direction distance of any one row of terminal arrangement center positions in the X direction in the semiconductor device, and the conductivity in the plurality of first wiring pattern sheets installed in the vertical direction. The distance in the Y direction of the center position of the open end of the pattern is the same as the distance in the Y direction of the center position of a part or all of the terminal arrangement in the Y direction in the semiconductor device, and the center position of the open end of the conductive pattern is in the XY coordinate plane. Since the relative coordinates have the same means as the relative coordinates in the XY coordinate plane of the terminal arrangement center position of the semiconductor device, it is possible to mount a plurality of ICs having multi-pin narrow pitch terminals with high accuracy and low cost. ..
Further, according to the present invention, in the second insulating film, a first opening hole into which the conductive pattern open end can be inserted at the same position as the XY coordinates of a part or all of the conductive pattern open end center. A second opening hole of any shape opened at a position in the Y direction on the XY coordinate plane near the first opening hole with an opening area larger than that of the first opening hole. A first positioning sheet is installed in which the first opening hole and the second opening hole are continuous opening holes by a tapered opening hole, and further, a second opening hole of the first positioning sheet is installed. And, at a position opposite to the center coordinates of the first opening hole (in the −Y direction), a third opening hole having an arbitrary shape opened at least with an opening area larger than that of the first opening hole is provided. A second positioning sheet in which the first opening hole and the third opening hole are continuous opening holes by a tapered opening hole is installed so as to overlap with the first positioning sheet, and the conductive pattern is opened. Since the means for penetrating the ends through the first opening holes of both the first and second positioning sheets, the open ends of the conductive pattern can be easily arranged with high accuracy.
Further, according to the present invention, in the third insulating film of the connection sheet, at least one of the upper surfaces of the conductive pattern open end is located at the same position as the XY coordinates of a part or all of the conductive pattern open end center. Since an opening hole having a part or the entire area is provided and a means for matching the upper surface of the conductive pattern open end with the lower surface of the opening hole is provided, bumps or the like are independently formed on the conductive pattern open end. It is possible to form terminals, and it is possible to fix them firmly with high accuracy.
Further, the present invention provides a part or all terminals of an arbitrary X-direction terminal arrangement in the first semiconductor device and a part or all terminals of an arbitrary X-direction terminal arrangement in the second semiconductor device. In an IC package in which a plurality of ICs having a multi-pin narrow pitch terminal are mounted and connected by wiring, the vicinity of the IC is provided because the means for connecting the plurality of conductive patterns in one wiring pattern sheet installed in the vertical direction is provided. A low-cost IC package because the pattern wiring width and wiring interval can be sufficiently secured even in the high-density wiring of the above, and the high-density wiring between ICs can be directly wired without passing through vias in the multilayer wiring layer. Can be realized.
Further, in the present invention, a part or all of the terminals of an arbitrary X-direction terminal arrangement in any of the semiconductor devices and a part or all of the terminals of an arbitrary row in the external device terminals are installed in the vertical direction. In an IC package in which a plurality of ICs having multi-pin narrow pitch terminals are mounted and connected by wiring, since the means for connecting with the plurality of conductive patterns in one said first wiring pattern sheet is provided, high-density wiring in the vicinity of the IC is provided. Since the extended wiring from to the vicinity of the PCB can be directly wired without passing through vias or the like in the multilayer wiring layer, a low-cost IC package can be realized.
Further, in the present invention, since the first insulating film of the plurality of wiring pattern sheets installed in the vertical direction has a means for forming with one continuous insulating film, a plurality of ICs having a multi-pin narrow pitch terminal. In an IC package that is equipped with and connects wiring, high-density wiring between ICs and extended wiring from high-density wiring near the IC to the vicinity of the PCB can be integrated in all wiring patterns without the need for expensive manufacturing processes and skill. Since it can be manufactured, a low-cost IC package can be realized.
Further, in the present invention, since a part of the open end of the conductive pattern in the first wiring pattern sheet has a spring property, it can be used as an inspection probe of an mounted IC and fixes a defective IC. It is possible to reduce the product cost by discarding the IC before.
Further, the present invention includes a part or all of the conductive patterns installed on the XY plane in the second wiring pattern sheet, and a part or all of the conductive patterns in the plurality of first wiring pattern sheets. Since it has a means for electrically connecting the above terminals, complicated terminal-to-terminal connections or common connections are possible.

According to the semiconductor device of the present invention, wiring is performed on a substrate arranged in the direction perpendicular to the IC terminal arrangement plane, so that the IC chip is discontinuous from the device side terminal without via via connection in the multilayer wiring board. Wiring without points is possible.
In addition, since the wiring board is manufactured by a manufacturing method that does not use the wafer process and TSV technology, it is possible to collectively manufacture all wiring with a single manufacturing technology, reducing manufacturing costs and stabilizing characteristics. Can be realized.
Furthermore, a wiring method without discontinuities from high-density wiring to device-side wiring has already been implemented with a probe card using the same manufacturing technology, and the probe and package for inspection during IC stacking are manufactured with the same parts. Therefore, it is possible to detect and dispose of the defective IC in advance before fixing the package, reduce the disposal cost, and manufacture a low-cost product.
By these methods, a high-density IC package that realizes cost reduction in both manufacturing and inspection is provided.

FIG. 1 is a diagram showing a comparison between a basic mounting method of a semiconductor device according to the present invention and a conventional semiconductor device.
FIG. 2 is a diagram showing a basic structure of a semiconductor device according to the first embodiment of the present invention. FIG. 3 is an exploded perspective view showing a configuration of the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a plan view illustrating the operation of the terminal positioning method according to the first embodiment of the present invention.
FIG. 5 is a perspective view showing a semiconductor device fixing method according to the first embodiment of the present invention.
FIG. 6 is a partial view showing the configuration of the semiconductor device according to the second embodiment of the present invention.
FIG. 7 is a diagram showing a basic structure of a semiconductor device according to a third embodiment of the present invention.
FIG. 8 is a diagram showing the structure of a conventional semiconductor device.

Next, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing a comparison between a basic mounting method of a semiconductor device according to the present invention and a conventional semiconductor device. FIG. 1A is a configuration of the semiconductor device 1 according to the present invention, and FIG. 1B is a conventional semiconductor device. It is a summary of 100 typical configurations.
As summarized in FIG. 1B, the conventional semiconductor device described with reference to FIGS. 8A and 8B has an interposer 101 and an organic substrate 102 installed in parallel in the XY plane direction, and the silicon interposer 101 has a plurality of semiconductor devices. It has a wiring circuit that electrically connects the semiconductor device 50 and the terminal 61 of the external device 60 by the fine wiring 103 for signal connection between them and the expansion wiring 105 in the organic substrate 102.
On the other hand, in the semiconductor device 1 according to the present invention, as shown in FIG. 1A, a first wiring pattern sheet 10 arranged on an XZ plane with respect to an array terminal group common to any one X direction in a plurality of semiconductor devices. It also has a wiring circuit 111 that electrically connects a plurality of the semiconductor devices to each other, and a wiring circuit 112 that electrically connects an arbitrary semiconductor device and an external device terminal 61. Further, one or a plurality of second wiring pattern sheets 40 arranged on an XY plane are provided with a wiring circuit 113 for electrically connecting one or a plurality of the semiconductor device terminals. Details will be described with reference to FIGS. 2 and 2.
FIG. 2 is a diagram showing a basic structure of a semiconductor device according to the first embodiment of the present invention, showing a front view and a side view showing a semiconductor device configuration, and a plan view of a typical semiconductor device. ..
In FIG. 2, the semiconductor device 1 is for mounting and wiring one or a plurality of semiconductor devices 50 having terminals 51 at arbitrary coordinates on the XY coordinate plane, and a plurality of semiconductor devices 1 fixed on the first insulating film 11. It is composed of a wiring pattern sheet 10 composed of a conductive pattern 12, a positioning sheet 20 installed parallel to the XY coordinate plane, and a connection sheet 30 installed above the positioning sheet also parallel to the XY coordinate plane. ..
In the wiring pattern sheet 10, a plurality of wiring pattern sheets 10-1 to 10-12 installed in the vertical direction (XZ plane) are arranged in parallel in the Y direction, and a part of the conductive pattern 12 has a vertical portion 121. It is configured and arranged in parallel in the X direction on the first insulating film 11 to form a terminal arrangement in which one end is an open end 122.
The X-direction center distance of the conductive pattern open end 122 in any one vertically installed wiring pattern sheet 10-1, for example, Ppx, is the X-direction center in any X-direction terminal arrangement 511 in the semiconductor device. The Y-direction center distance of the conductive pattern open end 122 in all the wiring pattern sheets 10-1 to 10-12 arranged so as to be the same as the distance Ptx and installed in the vertical direction, for example, Ppy, is the semiconductor device 50. By being installed so as to be the same as the Y-direction center distance Pty in the Y-direction terminal arrangement 521, the relative coordinates of all the conductive pattern open end center positions in the XY coordinate plane are the terminal arrangement center positions of the semiconductor device. It becomes the same as the relative coordinates in the XY coordinate plane. In the wiring pattern sheet 10, a part of the X-direction terminal arrangement in the first semiconductor device 501, for example 512, and a part of the X-direction terminal arrangement in the second semiconductor device 502, for example 513, are combined into one. The wiring pattern sheet 10 was connected by the conductive pattern group 123.
On the other hand, in the wiring pattern sheet 10, a part of the X-direction terminal arrangement in the first semiconductor device 501, for example, 514, and the external connection terminal group 141 connected to the external device 60 are further added to the second semiconductor. A part of the X-direction terminal arrangement in the device 502, for example, 515, and the external connection terminal group 142 connected to the external device 60 are connected by a plurality of

conductive pattern groups

124 and 125 in one wiring pattern sheet 10, respectively. ..
The conductive pattern 12 can be manufactured with high accuracy by etching, electroforming, laser processing, or the like. According to the wiring pattern sheet according to the present invention, the fine terminal connection portion and the fine wiring portion 13 in the vicinity of the semiconductor device and the external device terminal connection portion 14 such as a PCB can be manufactured with the same wiring pattern sheet, that is, the same component. Become. Electroplating technology is widely used for microfabricated parts such as MEMS (MicroElectro, Mechanical, System), and both the wiring width and the wiring interval can be 10 μm or less.
Further, according to the method of the present invention, in the fine terminal connection portion near the semiconductor device, all the wiring is installed in the vertical direction (XZ plane), so that the pin-to-pin wiring as in the XY coordinate plane wiring is unnecessary. Therefore, unlike a wiring board in a wafer process, fine wiring having a wiring width and a wiring interval of 2 μm is not required. When the semiconductor device is, for example, a CPU and a DRAM device, according to the present invention, even if the terminal pitch for signal transmission between the CPU and the DRAM is 40 to 50 μm, it is fine without passing through an interlayer via hole or the like. It is possible to wire a short distance with the wiring connection, and it is possible to provide a wiring pattern sheet with little signal delay. Further, in the wiring of the interface signal wiring or the power supply with the external device, the wiring interval or the wiring width is continuously expanded in the same wiring pattern sheet, so that it is possible to realize an inexpensive interposer function. Become.
All the wiring pattern sheets 10-1 to 10-12 installed in the vertical direction may be manufactured as independent parts, but as shown in the side view of FIG. 1, one continuous first. By forming all the conductive patterns on the insulating film 11 and bending the semiconductor device to satisfy the Y-direction center distance Ppy, the semiconductor device can be manufactured at a low manufacturing cost.
FIG. 3 is an exploded perspective view showing the configuration of the semiconductor device according to the first embodiment of the present invention. Reference numeral 201 denotes a first positioning sheet, which is formed on the second insulating film 21 in the same arrangement as the center coordinates of the conductive pattern open end 122 in the XY coordinates, and has substantially the same shape as the outer shape of the conductive pattern open end 122. The first opening hole 221 has a size that allows the conductive pattern open end 122 and the vertical portion 121 to penetrate, and the first opening hole 221 is located in the vicinity of the first opening hole 221 in the Y direction on the XY coordinate plane. It has a second opening hole 222 of an arbitrary shape opened with an opening area larger than that of the opening hole 221 of the above, and the first opening hole 221 and the second opening hole 222 are continuously connected by a tapered opening hole 223. The opening hole 22 is formed.
Reference numeral 202 denotes a second positioning sheet, which is arranged on the second insulating film 21 in the same arrangement as the center coordinates in the XY coordinates of the open end 122 of the conductive pattern, similarly to the first positioning sheet 201. The first positioning sheet 201 has a first opening hole 231 having substantially the same shape as the outer shape of the conductive pattern open end 122 and having a size capable of penetrating the conductive pattern open end 122 and the vertical portion 121. At a position opposite to the center coordinates of the second opening hole 222 and the first opening hole 231 (in the −Y direction), a second having an arbitrary shape opened with an opening area larger than that of the first opening hole 231. It has 3 opening holes 232, and the first opening hole 231 and the third opening hole 232 are formed into a continuous opening hole 23 by a tapered opening hole 233. The second positioning sheet 202 is installed so as to overlap the first positioning sheet 201, and the conductive pattern open end 122 and the vertical portion 121 are placed on both of the first and

second positioning sheets

201 and 202. It is made to penetrate through the first opening holes 221 and 231.
FIG. 4 is a plan view illustrating the operation of the first and

second positioning sheets

201 and 202. FIG. 4A shows a plan view of the stage where the opening holes 22 and 23 of the first and

second positioning sheets

201 and 202 are substantially aligned and the conductive pattern open end 122 and the vertical portion 121 are inserted. Is. Since the second and third opening holes 222 and 232 are opened in an area relatively larger than the area of the conductive pattern open end 122, the conductive pattern open end 122 and the vertical portion 121 are inserted. easy.
Next, as shown in FIG. 4B, the first positioning sheet 201 is moved in the + Y direction, and the second positioning sheet 202 is moved in the −Y direction. At this time, even if the position of the conductive pattern open end 122 in the XY coordinates is slightly deviated from the desired position by the tapered opening holes 223 and 233 provided in the opening holes 22 and 23, the said The conductive pattern vertical portion 121 is guided to the wall surface of the tapered

opening hole

223 or 233 and is housed in the first opening holes 221 and 231 commonly installed at desired positions. By this operation, the position of the conductive pattern open end 122 in the XY coordinates is determined with high accuracy.
FIG. 5 is a perspective view showing a method of fixing a semiconductor device in a semiconductor device according to the first embodiment of the present invention. In FIG. 5, the connection sheet 30 is placed on the third insulating film 31 at the same position as the center coordinate of the conductive pattern open end 122 in the XY coordinates, which is substantially the same as the outer shape of the conductive pattern open end 122. After having the opening holes 33 and passing the first and

second positioning sheets

201 and 202 through the conductive pattern open end 122 and the vertical portion 121, the upper surface of the conductive pattern open end 122 and the connection sheet 30 is installed at a position substantially coincident with the lower surface of the third insulating film 31. As a result, the connection terminal portion 32 is formed by installing recesses each electrically insulated on the upper surface of all the conductive pattern open ends 122, and bumps are formed by filling with a conductive adhesive or the like. Can be fixed.
FIG. 6 is a partial view showing a configuration according to a second embodiment of the present invention. In FIG. 6, reference numeral 126 denotes a spring deformed portion installed in the vertical portion 121 at the open end 122 of the conductive pattern 12, and the vertical portion 121 is passed through the opening holes 22 and 23 in the positioning sheet 20 to be opened. A state in which the center positions of the ends 122 are aligned is shown. By providing the spring deforming portion 126 in the vertical portion 121, the open end 122 can function as a probe. Therefore, in the state of this figure, it is possible to bring the open end 122 into contact with the semiconductor device terminal 51 to carry out an electrical inspection of the semiconductor device 50, and to determine the quality of the semiconductor device 50 in advance. Therefore, the yield of the semiconductor device including the semiconductor device can be improved.
FIG. 7 is a diagram showing a basic structure of a semiconductor device according to a third embodiment of the present invention. The main difference from FIG. 1 in FIG. 7 is that a second wiring pattern sheet 40 is added, and the second wiring pattern sheet 40 is a plurality of conductive films fixed on a fourth insulating film 41. It is composed of the sex pattern 42 and is installed in the lower part of the first wiring pattern sheet 10 in parallel with the XY coordinate plane.
A part of the electrode pads 42 installed on the XY plane in the second wiring pattern sheet 40 and a part of the conductive patterns 12 in the plurality of first wiring pattern sheets 10 are electrically connected by soldering or the like. Is connected to. The connection method may be bump connection.
Since the electrode pad 42 in the second wiring pattern sheet 40 is installed on the XY coordinate plane, it is connected in the Y direction, that is, between the wiring pattern sheets (for example, between 10-1 and 10-2). Can also be connected. Therefore, the wiring between the plurality of

semiconductor device terminals

501 and 502 is not limited to the wiring by the conductive pattern 12 of the first wiring pattern sheet 10, but also the conductive pattern of the second wiring pattern sheet 40. Since wiring by 43 is also possible, it is possible to make complicated wiring between terminals and common wiring such as a power supply.
As described above, according to the present invention, the wiring on the substrate arranged in the direction perpendicular to the IC terminal arrangement plane allows the terminal on the device side from the IC chip without via the via connection in the multilayer wiring board. Wiring without discontinuities is possible.
In addition, since the wiring board is manufactured by a manufacturing method that does not use the wafer process and TSV technology, it is possible to collectively manufacture all wiring with a single manufacturing technology, reducing manufacturing costs and stabilizing characteristics. Can be realized.
Furthermore, a wiring method without discontinuities from high-density wiring to device-side wiring has already been implemented with a probe card using the same manufacturing technology, and the probe and package for inspection during IC stacking are manufactured with the same parts. Therefore, it is possible to find and dispose of the defective IC in advance before fixing the package.
By these methods, a high-density IC package that realizes cost reduction in both manufacturing and inspection is provided.

It can be used for semiconductor devices and inspection devices that have multiple semiconductor chips and wiring patterns.

1 Semiconductor device 10 First wiring pattern sheet 11 First insulating film 12 Conductive pattern 121 Vertical portion 122

Open end

123, 124, 125 Conductive pattern group 126 Spring deformation portion 13 Fine terminal connection portion 14 External device terminal connection portion 141,142 External connection terminal group 100 Semiconductor device 101 Silicon interposer 102 Organic substrate 103 Fine wiring 104 TSV
105 Expansion wiring 106 Through hole 107

Solder ball

111, 112, 113 Wiring circuit 20 Positioning sheet 201 First positioning sheet 202 Second positioning sheet 21 Second insulating film 22 Opening hole 221 First opening hole 222 Second opening hole 222

Opening holes

223, 233 Tapered opening holes 23 Opening holes 231 First opening holes 232 Third opening holes 30 Connection sheet 31 Third insulating film 32 Connection terminal 33 Opening holes 40 Second wiring pattern sheet 41 Fourth Insulating film 42 Electrode pad 43 Conductive pattern 50 Semiconductor device 501 First semiconductor device 502 Second semiconductor device 51 Semiconductor device terminals 511 to 515 X-direction terminal arrangement 521 Y-direction terminal arrangement 53 Bump 60 External device Ptx X-direction center Distance Pty Y-direction center distance Ppx X-direction center distance Ppy Y-direction center distance

Claims

A semiconductor device equipped with one or more semiconductor devices having terminals at arbitrary coordinates in the XY coordinate plane, for any one common X-direction array terminal group in any one or more semiconductor devices. , A wiring circuit that electrically connects a plurality of the semiconductor devices to each other on one wiring board arranged on an XZ plane, and a wiring circuit that electrically connects an arbitrary semiconductor device and an external device terminal. A semiconductor device comprising one or a plurality of wiring boards arranged on an XY plane with a wiring circuit for electrically connecting one or a plurality of the semiconductor device terminals.
The semiconductor device according to claim 1, which is parallel to a first wiring pattern sheet composed of a plurality of conductive patterns fixed on at least one or a plurality of first insulating films and parallel to an XY coordinate plane. A connection sheet having one or more positioning sheets provided with positioning holes in the second insulating film installed in the above, and a connection terminal portion in the third insulating film installed above the positioning sheet parallel to the XY coordinate plane. The semiconductor device mounting terminal array forming means, the semiconductor device mounting fixing means, the wiring circuit forming means for electrically connecting the semiconductor device terminals, and any of the semiconductor device and the external device terminal are provided. A semiconductor device characterized by having a wiring circuit forming means for electrically connecting.
The semiconductor device according to claim 1, which is installed parallel to the XY coordinate plane with a first wiring pattern sheet composed of a plurality of conductive patterns fixed on one or a plurality of first insulating films. One or a plurality of positioning sheets provided with positioning holes in the second insulating film, and a connection sheet having a connection terminal portion in the third insulating film installed above the positioning sheet in parallel with the XY coordinate plane. It is composed of a plurality of conductive patterns fixed on one or a plurality of fourth insulating films, and is composed of a second wiring pattern sheet installed under the first wiring pattern sheet in parallel with the XY coordinate plane. , The semiconductor device mounting terminal array forming means, the semiconductor device mounting fixing means, a wiring circuit forming means for electrically connecting a plurality of the semiconductor device terminals, and any of the semiconductor devices and external device terminals. A semiconductor device characterized by having a wiring circuit forming means for electrically connecting.
The terminal array forming means for mounting a semiconductor device according to claim 2 or 3, wherein a part of one or a plurality of the first wiring pattern sheets is installed in the vertical direction (XZ plane) and installed in the vertical direction. A part of the plurality of conductive patterns having one end as an open end in the first wiring pattern sheet is arranged in parallel in the X direction, and any one of the first wiring patterns installed in the vertical direction. The X-direction distance of a part or all of the conductive pattern open end center position in the sheet is the same as the X-direction distance of any one row of terminal arrangement center positions in the X direction in the semiconductor device, and is installed in the vertical direction. The Y-direction distance at the center position of the open end of the conductive pattern in the plurality of first wiring pattern sheets is the same as the Y-direction distance at the center position of a part or all of the terminal arrangement in the Y direction in the semiconductor device. Any of claims 1 to 3, wherein the relative coordinates of the center position of the open end arrangement of the conductive pattern in the XY coordinate plane are the same as the relative coordinates of the center position of the terminal arrangement of the semiconductor device in the XY coordinate plane. The semiconductor device described.
The terminal array forming means for mounting a semiconductor device according to claim 2 or 3, wherein a part or all of the conductive pattern open end center is located at the same position as the XY coordinates in the second insulating film. It has a first opening hole into which the open end of the conductive pattern can be inserted, and opens at a position in the Y direction on the XY coordinate plane near the first opening hole with an opening area larger than that of the first opening hole. A first positioning sheet having a second opening hole of an arbitrary shape and having the first opening hole and the second opening hole continuous with a tapered opening hole is installed. The semiconductor device according to any one of claims 1 to 4, wherein the open end of the conductive pattern is passed through at least the first opening hole.
The second insulating film has a first opening hole into which the open end of the conductive pattern can be inserted at the same position on the XY coordinate plane as the first positioning sheet, and is in the vicinity of the first opening hole. On the opposite side (-Y direction) of the second opening hole of the first positioning sheet and the center coordinates of the first opening hole in the XY coordinate plane of the above, at least an opening area larger than that of the first opening hole. A second positioning sheet having a third opening hole of an arbitrary shape opened in 1 and having the first opening hole and the third opening hole continuous with a tapered opening hole. 5. The fifth aspect of the present invention is that the open end of the conductive pattern is installed so as to be overlapped with the first positioning sheet, and the open end of the conductive pattern is passed through the first opening hole of both the first and second positioning sheets. The described semiconductor device.
The semiconductor device mounting fixing means according to claim 2 or 3, at the same position as the XY coordinates of a part or all of the conductive pattern open end center in the third insulating film in the connection sheet. Claim 1 is characterized in that an opening hole having at least a part or the entire area of the upper surface of the open end of the conductive pattern is provided so that the upper surface of the open end of the conductive pattern and the lower surface of the opening hole are made to coincide with each other. 6. The semiconductor device according to any one of 6.
A wiring circuit forming means for electrically connecting a plurality of the semiconductor devices according to claim 2 or 3, wherein a part or all terminals of an arbitrary X-direction terminal arrangement in the first semiconductor device are used. A feature of the second semiconductor device is that a part or all of the terminals of an arbitrary X-direction terminal arrangement are connected by a plurality of the conductive patterns in one wiring pattern sheet installed in the vertical direction. The semiconductor device according to any one of claims 1 to 7.
A wiring circuit forming means for electrically connecting any of the semiconductor devices according to claim 2 or 3 to external device terminals, which is a part or all of terminals of an arbitrary X-direction terminal arrangement in any of the semiconductor devices. And a part or all of the terminals in an arbitrary row of the terminals of the external device are connected by a plurality of the conductive patterns in the one first wiring pattern sheet installed in the vertical direction. Item 6. The semiconductor device according to any one of Items 1 to 8.
The semiconductor device according to any one of claims 1 to 9, wherein the first insulating film of the plurality of wiring pattern sheets installed in the vertical direction is formed of one continuous insulating film.
The semiconductor device according to any one of claims 1 to 10, wherein a part of the open end of the conductive pattern in the first wiring pattern sheet has a spring property.
A wiring circuit forming means for electrically connecting a plurality of the semiconductor device terminals according to claim 3, wherein a part or all of a conductive pattern installed on an XY plane in the second wiring pattern sheet is used. The semiconductor device according to any one of claims 1 or 3 to 11, wherein a part or all of the conductive patterns in the plurality of first wiring pattern sheets are electrically connected.