WO2021073193A1 - Composite crystalline metal oxide thin film transistor having vertical structure and manufacturing method therefor - Google Patents

Composite crystalline metal oxide thin film transistor having vertical structure and manufacturing method therefor Download PDF

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WO2021073193A1
WO2021073193A1 PCT/CN2020/104576 CN2020104576W WO2021073193A1 WO 2021073193 A1 WO2021073193 A1 WO 2021073193A1 CN 2020104576 W CN2020104576 W CN 2020104576W WO 2021073193 A1 WO2021073193 A1 WO 2021073193A1
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layer
metal oxide
gate
electrode
gate dielectric
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PCT/CN2020/104576
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French (fr)
Chinese (zh)
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陈荣盛
尹雪梅
李国元
邓孙斌
郭海成
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华南理工大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a composite crystal type metal oxide thin film transistor with a vertical structure and a manufacturing method thereof.
  • TFTs thin film transistors
  • the channel length must be reduced.
  • the channel length is difficult to shrink to the sub-micron level.
  • V-TFT The vertical channel structure TFT
  • the vertical channel structure TFT is an alternative structure that realizes the sub-micron-scale channel length. It can easily control the channel length by adjusting the thickness of the deposited film, thereby achieving the requirement of downsizing. At the same time, due to the shortening of the channel length, the operating speed of the device can be increased, and a larger operating current can be obtained under low voltage.
  • the V-TFT prepared by the ALD deposition method exhibits a higher off-state current and a larger gate leakage current.
  • Back-channel effect the spacer layer between the source and drain is etched to form vertical sidewalls, and the active layer is deposited on the sidewalls, thereby A device structure that forms a vertical channel.
  • the back channel is in the vertical sidewall position. Due to the existence of a large number of interface states and nearby oxygen vacancies, a large off-state current may be generated in the short-channel V-TFT, and this current will not be caused by the reduction of the electric field in the gate coverage area. Reduce; 2.
  • the gate leakage current is significantly higher: In order to achieve an effective vertical structure, during the preparation process, the thickness of the channel active layer and the gate dielectric layer must be reduced as much as possible, because the gate dielectric layer is very thin and the vertical channel surface Roughness easily forms a leakage path for tunneling current. Therefore, both before and after the oxygen plasma treatment, the gate leakage current is obviously higher.
  • the purpose of the embodiments of the present invention is to provide a composite crystal type metal oxide thin film transistor with a vertical structure and a manufacturing method thereof.
  • the composite crystal metal oxide thin film transistor of the vertical structure has lower off-state current and gate leakage current.
  • embodiments of the present invention provide a composite crystal metal oxide thin film transistor with a vertical structure, including a substrate, a source electrode, a spacer layer, a drain electrode, an active layer, a double-layer gate dielectric layer, a gate electrode, and Test electrode; wherein the source electrode is disposed on the surface of the substrate; a part of the spacer layer is disposed on the surface of the source electrode, and another part of the spacer layer is disposed on the surface of the substrate; the drain Is disposed on the surface of the spacer layer; a part of the active layer is disposed on the surface of the drain, and another part of the active layer is disposed on the surface of the source; a part of the double-layer gate dielectric layer is disposed on the surface of the drain.
  • a part of the double-layered gate dielectric layer is disposed on the surface of the active layer, and another part of the double-layered gate dielectric layer is disposed on the surface of the source; the gate is disposed on the surface of the active layer;
  • the surface of the double-layer gate dielectric layer, and the projection range of the gate on the substrate is smaller than the projection range of the active layer on the substrate;
  • the first part of the test electrode is arranged on the source electrode
  • the second part of the test electrode is arranged on the surface of the drain and is in contact with the double-layer gate dielectric layer; the gate and the source are in contact with the double-layer gate dielectric layer.
  • Both the electrode and the drain overlap in the projection range of the active layer;
  • the active layer is an inorganic metal oxide with a composite crystal type.
  • the substrate includes one of a silicon wafer, glass or a flexible material whose surface is covered with a buffer layer.
  • the buffer layer includes one of silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride.
  • the source electrode, the drain electrode, the gate electrode and the test electrode all comprise one of metal, conductive metal oxide or organic conductive material.
  • the thickness of the source electrode and the drain electrode are both in the range of 30-60 nm.
  • the thickness of the gate electrode and the test electrode are both in the range of 100-300 nm.
  • the spacer layer includes one of silicon dioxide, silicon nitride, aluminum oxide, PI, PET or photoresist.
  • the thickness of the spacer layer ranges from 300 nm to 500 nm.
  • an embodiment of the present invention provides a method for manufacturing a composite crystal metal oxide thin film transistor with a vertical structure, which includes the following steps:
  • the spacer layer is etched by a dry etching process to form vertical sidewalls
  • a third conductive film is deposited, and the third conductive film is patterned to form a gate and a test electrode.
  • the manufacturing method further includes the steps:
  • the manufactured vertical structure composite crystal type metal oxide thin film transistor is annealed.
  • the active layer adopts inorganic non-metal oxides with composite crystals, which has fewer defect states and higher carrier mobility, thereby obtaining a lower off state.
  • Current Double-layer gate dielectric layer is used to improve the insulation of the gate dielectric layer, thereby reducing gate leakage current.
  • FIG. 1 is a schematic cross-sectional view of a composite crystal type metal oxide thin film transistor with a vertical structure according to an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of a substrate with a buffer layer provided by an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view after forming a source pattern according to an embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view after forming a spacer layer and a drain pattern according to an embodiment of the present invention
  • FIG. 5 is a schematic cross-sectional view after forming a spacer layer and a drain pattern with vertical sidewalls according to an embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional view after forming an active layer pattern according to an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view after forming a first gate dielectric layer according to an embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional view after forming a second gate dielectric layer according to an embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view after forming a contact hole according to an embodiment of the present invention.
  • FIG. 10 is a graph showing the transfer characteristics of a composite crystal metal oxide thin film transistor with a vertical structure according to an embodiment of the present invention.
  • FIG. 11 is a graph showing the transfer characteristics of another composite crystal metal oxide thin film transistor with a vertical structure according to an embodiment of the present invention.
  • an embodiment of the present invention provides a composite crystal metal oxide thin film transistor with a vertical structure, which includes a substrate 101, a source electrode 103, a spacer layer 104, a drain electrode 105, an active layer 106, and a double layer.
  • the gate dielectric layer, the gate electrode 109 and the test electrode 110, the substrate 101 includes a buffer layer 102, and the double-layer gate dielectric layer includes a first layer of gate dielectric layer 107 and a second layer of gate dielectric layer 108; wherein, the source electrode 103 is provided On the substrate surface buffer layer 102; a part of the spacer layer 104 is disposed on the surface of the source electrode 103, and another part of the spacer layer 104 is disposed on the substrate surface buffer layer 102; the drain The electrode 105 is arranged on the surface of the spacer layer 104; a part of the active layer 106 is arranged on the surface of the drain electrode, and another part of the active layer 106 is arranged on the surface of the source electrode 103; the double-layer gate A part of the dielectric layer is disposed on the surface of the drain electrode 105, a part of the double-layer gate dielectric layer is disposed on the surface of the active layer 106, and another part of the double-layer gate dielectric layer is disposed on
  • the material in the active layer has a composite crystal structure, that is, crystalline and amorphous components exist at the same time; among them, the size of the crystal grains is between 0.5 nm and 10 nm, and is surrounded by an amorphous frame. The degree of order is between amorphous and polycrystalline materials.
  • the thickness of the active layer is 50 nm to 100 nm.
  • the active layer is obtained by direct magnetron sputtering or evaporation of an inorganic metal oxide source material with a complex crystal form, or simultaneous magnetron sputtering or evaporation of two or more inorganic metal oxide source materials.
  • the source material At least one of them has a crystal structure, for example: In 2 O 3 and ZnO combination, ITO and ZnO combination, FTO and ZnO combination, etc.
  • the first gate dielectric layer and the second gate dielectric layer are both silicon dioxide, but the preparation processes of the first gate dielectric layer and the second gate dielectric layer are different.
  • the first gate dielectric layer uses plasma-enhanced chemical vapor deposition to deposit silicon dioxide, and the reaction precursor is alkoxysilane such as ethyl orthosilicate (TEOS) or tetramethyl silicate (TMOS), plus oxygen, Oxidizing gases such as ozone or nitrous oxide, the deposition temperature is 23°C ⁇ 400°C, the first gate dielectric layer directly contacting the active layer is silicon dioxide prepared by this method, and its thickness is 80nm ⁇ 120nm;
  • the reaction precursor is silicon hydride (SiH 4 ), plus oxidizing gases such as nitrogen, ozone or nitrous oxide, and the deposition temperature It is 23°C ⁇ 400°C, and its thickness is 40nm ⁇ 80nm.
  • the active layer adopts inorganic non-metal oxides with composite crystals, which has fewer defect states and higher carrier mobility, thereby obtaining a lower off state.
  • Current Double-layer gate dielectric layer is used to improve the insulation of the gate dielectric layer, thereby reducing gate leakage current.
  • the substrate includes one of a silicon wafer, glass or a flexible material whose surface is covered with a buffer layer.
  • the buffer layer includes one of silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride.
  • the temperature at which the buffer layer is deposited on the substrate is 23°C to 400°C.
  • the source electrode, the drain electrode, the gate electrode and the test electrode all comprise one of metal, conductive metal oxide or organic conductive material.
  • the thickness of the source electrode and the drain electrode are both in the range of 30-60 nm.
  • the thickness of the gate electrode and the test electrode are both in the range of 100-300 nm.
  • metals include aluminum, titanium, molybdenum, etc.
  • conductive metal oxides include ITO (In 2 O 3 :Sn) and FTO (SnO 2 :F)
  • organic conductive materials include PEDOT: PSS.
  • the spacer layer includes one of silicon dioxide, silicon nitride, aluminum oxide, PI, PET or photoresist.
  • the spacer layer can be either organic material or inorganic material.
  • the thickness of the spacer layer ranges from 300 nm to 500 nm.
  • an embodiment of the present invention provides a method for manufacturing a composite crystal metal oxide thin film transistor with a vertical structure, which includes the following steps:
  • a buffer layer 102 on the surface of the substrate 101 material. As shown in FIG. 2, in this embodiment, first, a silicon dioxide buffer layer 102 is deposited on a 4-inch substrate 101 by using a plasma enhanced chemical vapor deposition method.
  • a first conductive film on the surface of the buffer layer 102 of the substrate 101, and patterning the first conductive film to form the source electrode 103.
  • a conductive 50nm thick indium tin oxide film that is, the first conductive film, is deposited on the buffer layer 102 using a DC magnetron sputtering method, and the indium tin oxide is patterned through photolithography and etching processes.
  • a square source 103 is formed.
  • a spacer layer 104 and a second conductive film sequentially on the surface of the patterned substrate 101, and performing a patterning process on the second conductive film to form a drain 105.
  • a 300nm thick SiO 2 spacer layer 104 is deposited under a SiH 4 atmosphere by plasma enhanced chemical vapor deposition; and a conductive 50nm thick indium tin oxide film is deposited on top of it using a DC magnetron sputtering method. That is, the second conductive film is patterned with indium tin oxide through photolithography and etching processes to form a square drain 105.
  • the spacer layer 104 is etched by a dry etching process to form vertical sidewalls.
  • the square indium tin oxide film drain 105 is used as a mask, and the SiO 2 spacer layer 104 is etched by a dry etching process to form vertical sidewalls.
  • S6 Depositing the first gate dielectric layer 107 and the second gate dielectric layer 108 separately by chemical vapor deposition.
  • a plasma enhanced chemical vapor deposition method is used above the active layer 106.
  • the gas source is TEOS supported by argon gas, plus nitrous oxide and oxygen, and the deposition temperature is At 300° C., the power was 30 W, the pressure was 220 mTorr, and then 100 nm silicon dioxide was deposited as the first gate dielectric layer 107.
  • plasma enhanced chemical vapor deposition of silicon dioxide is also used.
  • the gas source is silane, plus nitrous oxide and nitrogen, and the deposition temperature is 300°C.
  • the power is 60W
  • the pressure is 900mTorr
  • the second gate dielectric layer 108 of 50nm is deposited.
  • the indium tin oxide film is deposited by the DC magnetron sputtering method, and the indium tin oxide is patterned through photolithography and etching processes to facilitate testing, and the gate 109 and the test electrode 110 as shown in FIG. 1 are formed.
  • the manufacturing method further includes the steps:
  • the manufactured vertical structure composite crystal type metal oxide thin film transistor is annealed. Specifically, the above-mentioned vertical thin film transistor was annealed in an oven at 300° C. in an air atmosphere for 10 hours.
  • the vertical structure thin film transistor based on the composite crystal type indium tin zinc oxide active layer manufactured by the above method in this embodiment was tested.
  • the transfer characteristic curve of the vertical structure thin film transistor is shown in Fig. 10 and Fig. 11, and its electrical characteristics can be found. Superior performance.
  • the device has a low off-state current, as shown in Fig. 10; the device has a low gate leakage current, as shown in Fig. 11, the values are all in the range of 10-13 to 10-14.
  • the low off-state current indicates that the composite crystalline indium tin zinc oxide film has fewer defect states, and the vertical side of the spacer layer etched by the dry etching process has fewer interface states.
  • the low gate leakage current shows that the composite crystal indium tin zinc oxide film and the silicon dioxide layer based on organic source plasma-enhanced chemical vapor deposition such as TEOS have an extremely high-quality interface and exhibit excellent insulation properties.

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Abstract

Disclosed are a composite crystalline metal oxide thin film transistor having a vertical structure and a manufacturing method therefor. The transistor comprises a substrate, a source, a spacer layer, a drain, an active layer, a double-layer gate dielectric layer, a gate, and a test electrode. The source is disposed on a surface of the substrate. The spacer layer is disposed on a surface of the source and the surface of the substrate. The drain is disposed on a surface of the spacer layer. The active layer is disposed on a surface of the drain and the surface of the the source. The double-layer gate dielectric layer is disposed on the surface of the drain, a surface of the active layer, and the surface of the source. The gate is disposed on a surface of the double-layer gate dielectric layer, and a projection range of the gate on the substrate is smaller than that of the active layer on the substrate. The test electrode is disposed on the surface of the source and the surface of the drain, and is in contact with both layers of the double-layer gate dielectric layer. Projection ranges of the gate, the source, and the drain on the active layer overlap. The active layer is an inorganic metal oxide having a composite crystalline form. The transistor has low off-state currents and low gate leakage currents. The present invention is widely applicable in the technical field of semiconductors.

Description

垂直结构的复合晶型金属氧化物薄膜晶体管及其制造方法Vertical structure composite crystal type metal oxide thin film transistor and manufacturing method thereof 技术领域Technical field
本发明涉及半导体技术领域，尤其涉及垂直结构的复合晶型金属氧化物薄膜晶体管及其制造方法。The present invention relates to the field of semiconductor technology, in particular to a composite crystal type metal oxide thin film transistor with a vertical structure and a manufacturing method thereof.
背景技术Background technique
下一代有源矩阵平板显示技术正朝着大尺寸、超高清、高帧率及外围电路全集成等方向发展。薄膜晶体管(TFT)作为显示面板的构成要素，要求其必须往小型化方向发展，并能向显示器件提供足够的电学驱动能力。对于传统横向沟道结构的TFT器件，要缩小尺寸，必需减小沟道长度。然而，由于平板显示制作工艺中光刻工具的局限性，沟道长度很难缩小到亚微米级。The next-generation active matrix flat panel display technology is developing in the direction of large size, ultra-high definition, high frame rate, and full integration of peripheral circuits. As a constituent element of a display panel, thin film transistors (TFTs) are required to develop in the direction of miniaturization and provide sufficient electrical driving capabilities for display devices. For TFT devices with a traditional lateral channel structure, to reduce the size, the channel length must be reduced. However, due to the limitations of photolithography tools in the flat panel display manufacturing process, the channel length is difficult to shrink to the sub-micron level.
垂直沟道结构的TFT(V-TFT)是一种实现亚微米尺度沟道长度的可替换结构，它可通过调节沉积薄膜的厚度来轻松控制沟道长度，从而达到缩小尺寸的要求。同时，因沟道长度的缩短，可以提高器件的工作速度，并可在低压下获得较大的工作电流。但是，采用ALD沉积方法制备的V-TFT，表现出较高的关态电流及较大的栅泄漏电流。The vertical channel structure TFT (V-TFT) is an alternative structure that realizes the sub-micron-scale channel length. It can easily control the channel length by adjusting the thickness of the deposited film, thereby achieving the requirement of downsizing. At the same time, due to the shortening of the channel length, the operating speed of the device can be increased, and a larger operating current can be obtained under low voltage. However, the V-TFT prepared by the ALD deposition method exhibits a higher off-state current and a larger gate leakage current.
由于V-TFT器件因工艺结构的特殊性，普遍存在两大问题：一、背沟道效应：源漏之间的间隔层经刻蚀形成垂直侧壁，在侧壁上沉积有源层，从而形成垂直沟道的器件结构。背沟道处于垂直侧壁位置，因存在大量界面态以及附近的氧空位，可能会导致短沟道V-TFT中产生大关态电流，而此电流不会因为栅覆盖区域的电场减小而减小；二、栅漏电流明显偏高：为实现有效垂直结构，在制备过程中，需尽量减小沟道有源层及栅介质层厚度，由于栅介质层很薄，以及垂直沟道表面粗糙容易形成隧穿电流的泄漏通道。故不论是经氧等离子体处理前还是处理后，栅泄漏电流都明显偏高。Due to the particularity of the process structure of V-TFT devices, there are generally two major problems: 1. Back-channel effect: the spacer layer between the source and drain is etched to form vertical sidewalls, and the active layer is deposited on the sidewalls, thereby A device structure that forms a vertical channel. The back channel is in the vertical sidewall position. Due to the existence of a large number of interface states and nearby oxygen vacancies, a large off-state current may be generated in the short-channel V-TFT, and this current will not be caused by the reduction of the electric field in the gate coverage area. Reduce; 2. The gate leakage current is significantly higher: In order to achieve an effective vertical structure, during the preparation process, the thickness of the channel active layer and the gate dielectric layer must be reduced as much as possible, because the gate dielectric layer is very thin and the vertical channel surface Roughness easily forms a leakage path for tunneling current. Therefore, both before and after the oxygen plasma treatment, the gate leakage current is obviously higher.
发明内容Summary of the invention
有鉴于此，本发明实施例的目的是提供一种垂直结构的复合晶型金属氧化物薄膜晶体管及其制造方法。该垂直结构的复合晶型金属氧化物薄膜晶体管具有较低的关态电流及栅泄漏电流。In view of this, the purpose of the embodiments of the present invention is to provide a composite crystal type metal oxide thin film transistor with a vertical structure and a manufacturing method thereof. The composite crystal metal oxide thin film transistor of the vertical structure has lower off-state current and gate leakage current.
第一方面，本发明实施例提供了一种垂直结构的复合晶型金属氧化物薄膜晶体管，包括衬底、源极、间隔层、漏极、有源层、双层栅介质层、栅极及测试电极；其中，所述源极设置于所述衬底表面；所述间隔层的一部分设置于所述源极表面，所述间隔层的另一部分设置 于所述衬底表面；所述漏极设置于所述间隔层表面；所述有源层的一部分设置于所述漏极表面，所述有源层的另一部分设置于所述源极表面；所述双层栅介质层的一部分设置于所述漏极表面，所述双层栅介质层的一部分设置于所述有源层表面，所述双层栅介质层的另一部分设置于所述源极表面；所述栅极设置于所述双层栅介质层表面，且所述栅极在所述衬底上的投影范围小于所述有源层在所述衬底上的投影范围；所述测试电极的第一部分设置于所述源极表面且与所述双层栅介质层均有接触，所述测试电极的第二部分设置于所述漏极表面且与所述双层栅介质层均有接触；所述栅极、所述源极及所述漏极在所述有源层的投影范围均有交叠；所述有源层是具有复合晶型的无机金属氧化物。In the first aspect, embodiments of the present invention provide a composite crystal metal oxide thin film transistor with a vertical structure, including a substrate, a source electrode, a spacer layer, a drain electrode, an active layer, a double-layer gate dielectric layer, a gate electrode, and Test electrode; wherein the source electrode is disposed on the surface of the substrate; a part of the spacer layer is disposed on the surface of the source electrode, and another part of the spacer layer is disposed on the surface of the substrate; the drain Is disposed on the surface of the spacer layer; a part of the active layer is disposed on the surface of the drain, and another part of the active layer is disposed on the surface of the source; a part of the double-layer gate dielectric layer is disposed on the surface of the drain. On the surface of the drain, a part of the double-layered gate dielectric layer is disposed on the surface of the active layer, and another part of the double-layered gate dielectric layer is disposed on the surface of the source; the gate is disposed on the surface of the active layer; The surface of the double-layer gate dielectric layer, and the projection range of the gate on the substrate is smaller than the projection range of the active layer on the substrate; the first part of the test electrode is arranged on the source electrode The second part of the test electrode is arranged on the surface of the drain and is in contact with the double-layer gate dielectric layer; the gate and the source are in contact with the double-layer gate dielectric layer. Both the electrode and the drain overlap in the projection range of the active layer; the active layer is an inorganic metal oxide with a composite crystal type.
优选地，所述衬底包括表面覆有缓冲层的硅片、玻璃或柔性材料中的一种。Preferably, the substrate includes one of a silicon wafer, glass or a flexible material whose surface is covered with a buffer layer.
优选地，所述缓冲层包括二氧化硅、氮化硅或二氧化硅与氮化硅组合物中的一种。Preferably, the buffer layer includes one of silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride.
优选地，所述源极、所述漏极、所述栅极及所述测试电极均包括金属、导电金属氧化物或有机导电材料中的一种。Preferably, the source electrode, the drain electrode, the gate electrode and the test electrode all comprise one of metal, conductive metal oxide or organic conductive material.
优选地，所述源极及所述漏极的厚度范围均为30～60nm。Preferably, the thickness of the source electrode and the drain electrode are both in the range of 30-60 nm.
优选地，所述栅极及所述测试电极的厚度范围均为100～300nm。Preferably, the thickness of the gate electrode and the test electrode are both in the range of 100-300 nm.
优选地，所述间隔层包括二氧化硅、氮化硅、氧化铝、PI、PET或光刻胶中的一种。Preferably, the spacer layer includes one of silicon dioxide, silicon nitride, aluminum oxide, PI, PET or photoresist.
优选地，所述间隔层的厚度范围为300～500nm。Preferably, the thickness of the spacer layer ranges from 300 nm to 500 nm.
第二方面，本发明实施例提供了一种垂直结构的复合晶型金属氧化物薄膜晶体管的制造方法，包括以下步骤：In the second aspect, an embodiment of the present invention provides a method for manufacturing a composite crystal metal oxide thin film transistor with a vertical structure, which includes the following steps:
在衬底材料表面沉积缓冲层；Deposit a buffer layer on the surface of the substrate material;
在所述衬底的缓冲层表面沉积第一导电薄膜，并对第一导电薄膜进行图形化处理，形成源极；Depositing a first conductive film on the surface of the buffer layer of the substrate, and patterning the first conductive film to form a source;
在所述图形化处理后的衬底表面依次沉积间隔层及第二导电薄膜，并对第二导电薄膜进行图形化处理，形成漏极；Depositing a spacer layer and a second conductive film sequentially on the surface of the patterned substrate, and patterning the second conductive film to form a drain electrode;
以所述漏极为掩膜，采用干法蚀刻工艺刻蚀间隔层，形成垂直侧壁；Using the drain electrode as a mask, the spacer layer is etched by a dry etching process to form vertical sidewalls;
沉积具有复合晶型的氧化物薄膜，并对所述氧化物薄膜进行图形化处理，形成有源层；Depositing an oxide film with a composite crystal type, and performing patterning treatment on the oxide film to form an active layer;
采用化学气相沉积方式分别沉积第一栅介质层和第二栅介质层；Depositing the first gate dielectric layer and the second gate dielectric layer separately by chemical vapor deposition;
采用干法蚀刻工艺刻蚀所述第一栅介质层及所述第二栅介质层，形成所述源极及所述漏极的接触孔；Etch the first gate dielectric layer and the second gate dielectric layer by using a dry etching process to form contact holes for the source electrode and the drain electrode;
沉积第三导电薄膜，并对所述第三导电薄膜进行图形化处理，形成栅极和测试电极。A third conductive film is deposited, and the third conductive film is patterned to form a gate and a test electrode.
优选地，所述制造方法，还包括步骤：Preferably, the manufacturing method further includes the steps:
将制造的垂直结构的复合晶型金属氧化物薄膜晶体管进行退火处理。The manufactured vertical structure composite crystal type metal oxide thin film transistor is annealed.
实施本发明实施例具有如下有益效果：本发明实施例中有源层采用具有复合晶型的无机非金属氧化物，缺陷态更少、载流子迁移率更高，从而获得较低的关态电流；采用双层栅介质层，使栅介质层的绝缘性提高，从而减小栅泄漏电流。The implementation of the embodiments of the present invention has the following beneficial effects: In the embodiments of the present invention, the active layer adopts inorganic non-metal oxides with composite crystals, which has fewer defect states and higher carrier mobility, thereby obtaining a lower off state. Current; Double-layer gate dielectric layer is used to improve the insulation of the gate dielectric layer, thereby reducing gate leakage current.
附图说明Description of the drawings
图1是本发明实施例提供的一种垂直结构的复合晶型金属氧化物薄膜晶体管的横截面示意图；1 is a schematic cross-sectional view of a composite crystal type metal oxide thin film transistor with a vertical structure according to an embodiment of the present invention;
图2是本发明实施例提供的一种具有缓冲层衬底的横截面示意图；2 is a schematic cross-sectional view of a substrate with a buffer layer provided by an embodiment of the present invention;
图3是本发明实施例提供的一种形成源极图案后的横截面示意图；3 is a schematic cross-sectional view after forming a source pattern according to an embodiment of the present invention;
图4是本发明实施例提供的一种形成间隔层和漏极图案后的横截面示意图；4 is a schematic cross-sectional view after forming a spacer layer and a drain pattern according to an embodiment of the present invention;
图5是本发明实施例提供的一种形成垂直侧壁的间隔层和漏极图案后的横截面示意图；5 is a schematic cross-sectional view after forming a spacer layer and a drain pattern with vertical sidewalls according to an embodiment of the present invention;
图6是本发明实施例提供的一种形成有源层图案后的横截面示意图；6 is a schematic cross-sectional view after forming an active layer pattern according to an embodiment of the present invention;
图7是本发明实施例提供的一种形成第一栅介质层后的横截面示意图；FIG. 7 is a schematic cross-sectional view after forming a first gate dielectric layer according to an embodiment of the present invention; FIG.
图8是本发明实施例提供的一种形成第二栅介质层后的横截面示意图；8 is a schematic cross-sectional view after forming a second gate dielectric layer according to an embodiment of the present invention;
图9是本发明实施例提供的一种形成接触孔后的横截面示意图；FIG. 9 is a schematic cross-sectional view after forming a contact hole according to an embodiment of the present invention;
图10是本发明实施例提供的一种垂直结构的复合晶型金属氧化物薄膜晶体管的转移特性曲线图；10 is a graph showing the transfer characteristics of a composite crystal metal oxide thin film transistor with a vertical structure according to an embodiment of the present invention;
图11是本发明实施例提供的另一种垂直结构的复合晶型金属氧化物薄膜晶体管的转移特性曲线图。FIG. 11 is a graph showing the transfer characteristics of another composite crystal metal oxide thin film transistor with a vertical structure according to an embodiment of the present invention.
具体实施方式Detailed ways
下面结合附图和具体实施例对本发明做进一步的详细说明。对于以下实施例中的步骤编号，其仅为了便于阐述说明而设置，对步骤之间的顺序不做任何限定，实施例中的各步骤的执行顺序均可根据本领域技术人员的理解来进行适应性调整。The present invention will be further described in detail below in conjunction with the drawings and specific embodiments. For the step numbers in the following embodiments, they are set only for ease of elaboration, and there is no limitation on the order between the steps. The execution order of the steps in the embodiments can be adapted according to the understanding of those skilled in the art. Sexual adjustment.
如图1所示，本发明实施例提供了一种垂直结构的复合晶型金属氧化物薄膜晶体管，包括衬底101、源极103、间隔层104、漏极105、有源层106、双层栅介质层、栅极109及测试电极110，衬底101包括缓冲层102，双层栅介质层包括第一层栅介质层107及第二层栅介质层108；其中，所述源极103设置于所述衬底表面缓冲层102上；所述间隔层104的一部分设置于所述源极103表面，所述间隔层104的另一部分设置于所述衬底表面缓冲层102上；所述漏极105设置于所述间隔层104表面；所述有源层106的一部分设置于所述漏极表面，所述有源层106的另一部分设置于所述源极103表面；所述双层栅介质层的一部分设置于所 述漏极105表面，所述双层栅介质层的一部分设置于所述有源层106表面，所述双层栅介质层的另一部分设置于所述源极103表面；所述栅极109设置于所述双层栅介质层表面，且所述栅极109在所述衬底101上的投影范围小于所述有源层106在所述衬底101上的投影范围；所述测试电极110的第一部分设置于所述源极103表面且与所述双层栅介质层均有接触，所述测试电极110的第二部分设置于所述漏极105表面且与所述双层栅介质层均有接触；所述栅极109、所述源极103及所述漏极105在所述有源层106的投影范围均有交叠；所述有源层106是具有复合晶型的无机金属氧化物。As shown in FIG. 1, an embodiment of the present invention provides a composite crystal metal oxide thin film transistor with a vertical structure, which includes a substrate 101, a source electrode 103, a spacer layer 104, a drain electrode 105, an active layer 106, and a double layer. The gate dielectric layer, the gate electrode 109 and the test electrode 110, the substrate 101 includes a buffer layer 102, and the double-layer gate dielectric layer includes a first layer of gate dielectric layer 107 and a second layer of gate dielectric layer 108; wherein, the source electrode 103 is provided On the substrate surface buffer layer 102; a part of the spacer layer 104 is disposed on the surface of the source electrode 103, and another part of the spacer layer 104 is disposed on the substrate surface buffer layer 102; the drain The electrode 105 is arranged on the surface of the spacer layer 104; a part of the active layer 106 is arranged on the surface of the drain electrode, and another part of the active layer 106 is arranged on the surface of the source electrode 103; the double-layer gate A part of the dielectric layer is disposed on the surface of the drain electrode 105, a part of the double-layer gate dielectric layer is disposed on the surface of the active layer 106, and another part of the double-layer gate dielectric layer is disposed on the surface of the source electrode 103 The gate 109 is arranged on the surface of the double-layer gate dielectric layer, and the projection range of the gate 109 on the substrate 101 is smaller than the projection range of the active layer 106 on the substrate 101 The first part of the test electrode 110 is arranged on the surface of the source electrode 103 and is in contact with the double-layer gate dielectric layer, and the second part of the test electrode 110 is arranged on the surface of the drain electrode 105 and is in contact with the The double-layer gate dielectric layer has contacts; the gate 109, the source 103 and the drain 105 overlap in the projection range of the active layer 106; the active layer 106 has Complex crystal type inorganic metal oxide.
具体地，有源层中的材料是具有复合晶型的微观结构，即同时存在结晶和非晶成分；其中，晶粒的尺寸在0.5nm～10nm之间，并被非晶型框架包围，原子有序度介于非晶和多晶材料之间。有源层厚度为50nm～100nm。有源层是通过直接磁控溅射或蒸发一种具有复合晶型的无机金属氧化物源材料，或同时磁控溅射或蒸发两种或以上无机金属氧化物源材料而获得的，源材料中至少有一种具有晶体结构，例如：In 2O 3和ZnO组合，ITO和ZnO组合，FTO和ZnO组合等。 Specifically, the material in the active layer has a composite crystal structure, that is, crystalline and amorphous components exist at the same time; among them, the size of the crystal grains is between 0.5 nm and 10 nm, and is surrounded by an amorphous frame. The degree of order is between amorphous and polycrystalline materials. The thickness of the active layer is 50 nm to 100 nm. The active layer is obtained by direct magnetron sputtering or evaporation of an inorganic metal oxide source material with a complex crystal form, or simultaneous magnetron sputtering or evaporation of two or more inorganic metal oxide source materials. The source material At least one of them has a crystal structure, for example: In 2 O 3 and ZnO combination, ITO and ZnO combination, FTO and ZnO combination, etc.
具体地，第一层栅介质层及第二层栅介质层均为二氧化硅，但是第一层栅介质层及第二层栅介质层的制备工艺不同。第一层栅介质层使用等离子体增强化学气相沉积法沉积二氧化硅，反应前驱物为正硅酸乙酯(TEOS)或硅酸四甲酯(TMOS)等烷氧基硅烷，加上氧气、臭氧或一氧化二氮等氧化性气体，沉积温度为23℃～400℃，直接与有源层接触的第一层栅介质层是利用此方法制备的二氧化硅，其厚度为80nm～120nm；接着，使用等离子体增强化学气相沉积法沉积第二层栅介质层的二氧化硅，反应前驱物为氢化硅(SiH 4)，加上氮气、臭氧或一氧化二氮等氧化性气体，沉积温度为23℃～400℃，其厚度为40nm～80nm。 Specifically, the first gate dielectric layer and the second gate dielectric layer are both silicon dioxide, but the preparation processes of the first gate dielectric layer and the second gate dielectric layer are different. The first gate dielectric layer uses plasma-enhanced chemical vapor deposition to deposit silicon dioxide, and the reaction precursor is alkoxysilane such as ethyl orthosilicate (TEOS) or tetramethyl silicate (TMOS), plus oxygen, Oxidizing gases such as ozone or nitrous oxide, the deposition temperature is 23℃～400℃, the first gate dielectric layer directly contacting the active layer is silicon dioxide prepared by this method, and its thickness is 80nm～120nm; Next, use plasma enhanced chemical vapor deposition to deposit the silicon dioxide of the second gate dielectric layer, the reaction precursor is silicon hydride (SiH 4 ), plus oxidizing gases such as nitrogen, ozone or nitrous oxide, and the deposition temperature It is 23℃～400℃, and its thickness is 40nm～80nm.
实施本发明实施例具有如下有益效果：本发明实施例中有源层采用具有复合晶型的无机非金属氧化物，缺陷态更少、载流子迁移率更高，从而获得较低的关态电流；采用双层栅介质层，使栅介质层的绝缘性提高，从而减小栅泄漏电流。The implementation of the embodiments of the present invention has the following beneficial effects: In the embodiments of the present invention, the active layer adopts inorganic non-metal oxides with composite crystals, which has fewer defect states and higher carrier mobility, thereby obtaining a lower off state. Current; Double-layer gate dielectric layer is used to improve the insulation of the gate dielectric layer, thereby reducing gate leakage current.
优选地，所述衬底包括表面覆有缓冲层的硅片、玻璃或柔性材料中的一种。Preferably, the substrate includes one of a silicon wafer, glass or a flexible material whose surface is covered with a buffer layer.
优选地，所述缓冲层包括二氧化硅、氮化硅或二氧化硅与氮化硅组合物中的一种。Preferably, the buffer layer includes one of silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride.
具体地，将上述缓冲层沉积到衬底基片上的温度为23℃～400℃。Specifically, the temperature at which the buffer layer is deposited on the substrate is 23°C to 400°C.
优选地，所述源极、所述漏极、所述栅极及所述测试电极均包括金属、导电金属氧化物或有机导电材料中的一种。Preferably, the source electrode, the drain electrode, the gate electrode and the test electrode all comprise one of metal, conductive metal oxide or organic conductive material.
优选地，所述源极及所述漏极的厚度范围均为30～60nm。Preferably, the thickness of the source electrode and the drain electrode are both in the range of 30-60 nm.
优选地，所述栅极及所述测试电极的厚度范围均为100～300nm。Preferably, the thickness of the gate electrode and the test electrode are both in the range of 100-300 nm.
具体地，金属包括铝、钛及钼等，导电金属氧化物包括ITO(In 2O 3:Sn)及FTO(SnO 2:F)等，有机导电材料包括PEDOT:PSS等。 Specifically, metals include aluminum, titanium, molybdenum, etc., conductive metal oxides include ITO (In 2 O 3 :Sn) and FTO (SnO 2 :F), and organic conductive materials include PEDOT: PSS.
优选地，所述间隔层包括二氧化硅、氮化硅、氧化铝、PI、PET或光刻胶中的一种。间隔层即可以选择有机材料，也可以选择无机材料。Preferably, the spacer layer includes one of silicon dioxide, silicon nitride, aluminum oxide, PI, PET or photoresist. The spacer layer can be either organic material or inorganic material.
优选地，所述间隔层的厚度范围为300～500nm。Preferably, the thickness of the spacer layer ranges from 300 nm to 500 nm.
参见图2至图9，本发明实施例提供了一种垂直结构的复合晶型金属氧化物薄膜晶体管的制造方法，包括以下步骤：2-9, an embodiment of the present invention provides a method for manufacturing a composite crystal metal oxide thin film transistor with a vertical structure, which includes the following steps:
S1、在衬底101材料表面沉积缓冲层102。如图2所示，本实施例中，首先在4英寸衬底101上，采用等离子体增强化学气相沉积法沉积二氧化硅缓冲层102。S1. Depositing a buffer layer 102 on the surface of the substrate 101 material. As shown in FIG. 2, in this embodiment, first, a silicon dioxide buffer layer 102 is deposited on a 4-inch substrate 101 by using a plasma enhanced chemical vapor deposition method.
S2、在所述衬底101的缓冲层102表面沉积第一导电薄膜，并对第一导电薄膜进行图形化处理，形成源极103。如图3所示，在缓冲层102上方使用直流磁控溅射法沉积导电的50nm厚氧化铟锡薄膜，即第一导电薄膜，并通过光刻和刻蚀工艺，使氧化铟锡图形化，形成方形源极103。S2. Depositing a first conductive film on the surface of the buffer layer 102 of the substrate 101, and patterning the first conductive film to form the source electrode 103. As shown in FIG. 3, a conductive 50nm thick indium tin oxide film, that is, the first conductive film, is deposited on the buffer layer 102 using a DC magnetron sputtering method, and the indium tin oxide is patterned through photolithography and etching processes. A square source 103 is formed.
S3、在所述图形化处理后的衬底101表面依次沉积间隔层104及第二导电薄膜，并对第二导电薄膜进行图形化处理，形成漏极105。如图4所示，采用等离子体增强化学气相沉积法在SiH 4气氛下沉积300nm厚的SiO 2间隔层104；并在其上方使用直流磁控溅射法沉积导电的50nm厚氧化铟锡薄膜，即第二导电薄膜，并通过光刻和刻蚀工艺，使氧化铟锡图形化，形成方形漏极105。 S3, depositing a spacer layer 104 and a second conductive film sequentially on the surface of the patterned substrate 101, and performing a patterning process on the second conductive film to form a drain 105. As shown in Figure 4, a 300nm thick SiO 2 spacer layer 104 is deposited under a SiH 4 atmosphere by plasma enhanced chemical vapor deposition; and a conductive 50nm thick indium tin oxide film is deposited on top of it using a DC magnetron sputtering method. That is, the second conductive film is patterned with indium tin oxide through photolithography and etching processes to form a square drain 105.
S4、以所述漏极105为掩膜，采用干法蚀刻工艺刻蚀间隔层104，形成垂直侧壁。如图5所示，以方形氧化铟锡薄膜漏极105为掩膜，采用干法蚀刻工艺刻蚀SiO 2间隔层104，形成垂直侧壁。 S4. Using the drain 105 as a mask, the spacer layer 104 is etched by a dry etching process to form vertical sidewalls. As shown in FIG. 5, the square indium tin oxide film drain 105 is used as a mask, and the SiO 2 spacer layer 104 is etched by a dry etching process to form vertical sidewalls.
S5、沉积具有复合晶型的氧化物薄膜，并对所述氧化物薄膜进行图形化处理，形成有源层106。如图6所示，通过同时使用直流电源磁控溅射多晶氧化铟锡靶材(In 2O 3:SnO 2＝90:10wt％)(功率密度约为5.4W/cm 2)和射频电源磁控溅射多晶氧化锌靶材(功率密度约为7.4W/cm 2)的方式，并在溅射过程中采用40％的高氧分压，沉积80nm具有复合晶型的铟锡锌氧化物薄膜，在光刻和刻蚀后，使铟锡锌氧化物薄膜图形化，形成有源层106。 S5, depositing an oxide film with a composite crystal type, and performing patterning treatment on the oxide film to form the active layer 106. As shown in Figure 6, by using DC power supply magnetron sputtering polycrystalline indium tin oxide target material (In 2 O 3 :SnO 2 =90:10wt%) (power density is about 5.4W/cm 2 ) and radio frequency power supply Magnetron sputtering polycrystalline zinc oxide target material (power density is about 7.4W/cm 2 ), and uses 40% high oxygen partial pressure during the sputtering process, and deposits 80nm indium tin zinc oxide with composite crystal form After photolithography and etching, the indium tin zinc oxide film is patterned to form the active layer 106.
S6、采用化学气相沉积方式分别沉积第一栅介质层107和第二栅介质层108。如图7所示，在有源层106上方，使用等离子体增强化学气相沉积方法，气源为氩气承载的正硅酸乙酯(TEOS)，加上一氧化二氮和氧气，沉积温度为300℃，功率为30W，气压为220mTorr，接着沉积100nm二氧化硅，作为第一栅介质层107。如图8所示，在第一栅介质层107上方， 同样使用等离子体增强化学气相沉积的二氧化硅，此时的气源为硅烷，加上一氧化二氮和氮气，沉积温度为300℃，功率为60W，气压为900mTorr，再沉积50nm第二栅介质层108。S6: Depositing the first gate dielectric layer 107 and the second gate dielectric layer 108 separately by chemical vapor deposition. As shown in FIG. 7, above the active layer 106, a plasma enhanced chemical vapor deposition method is used. The gas source is TEOS supported by argon gas, plus nitrous oxide and oxygen, and the deposition temperature is At 300° C., the power was 30 W, the pressure was 220 mTorr, and then 100 nm silicon dioxide was deposited as the first gate dielectric layer 107. As shown in Figure 8, above the first gate dielectric layer 107, plasma enhanced chemical vapor deposition of silicon dioxide is also used. At this time, the gas source is silane, plus nitrous oxide and nitrogen, and the deposition temperature is 300°C. , The power is 60W, the pressure is 900mTorr, and the second gate dielectric layer 108 of 50nm is deposited.
S7、采用干法蚀刻工艺刻蚀所述第一栅介质层107及所述第二栅介质层108，形成所述源极及所述漏极的接触孔。如图9所示，采用干法蚀刻工艺刻蚀SiO 2第一栅介质层107及SiO 2第二栅介质层108，形成源极103及漏极105的接触孔。 S7. Use a dry etching process to etch the first gate dielectric layer 107 and the second gate dielectric layer 108 to form contact holes for the source electrode and the drain electrode. As shown in FIG. 9, the first gate dielectric layer 107 of SiO 2 and the second gate dielectric layer 108 of SiO 2 are etched by a dry etching process to form contact holes for the source 103 and the drain 105.
S8、沉积第三导电薄膜，并对所述第三导电薄膜进行图形化处理，形成栅极109和测试电极110。采用直流磁控溅射法沉积氧化铟锡薄膜，并通过光刻和刻蚀工艺，使氧化铟锡图形化，方便测试，形成如图1所示的栅极109和测试电极110。S8, depositing a third conductive film, and patterning the third conductive film to form a gate 109 and a test electrode 110. The indium tin oxide film is deposited by the DC magnetron sputtering method, and the indium tin oxide is patterned through photolithography and etching processes to facilitate testing, and the gate 109 and the test electrode 110 as shown in FIG. 1 are formed.
优选地，所述制造方法，还包括步骤：Preferably, the manufacturing method further includes the steps:
将制造的垂直结构的复合晶型金属氧化物薄膜晶体管进行退火处理。具体地，将上述垂直型薄膜晶体管放在300℃空气气氛的烘箱中退火10小时。The manufactured vertical structure composite crystal type metal oxide thin film transistor is annealed. Specifically, the above-mentioned vertical thin film transistor was annealed in an oven at 300° C. in an air atmosphere for 10 hours.
将本实施例中采用上述方法制造的基于复合晶型铟锡锌氧化物有源层的垂直结构薄膜晶体管进行测试，垂直结构薄膜晶体管转移特性曲线如图10及图11所示，可发现其电学性能优越。特别是，器件具有低的关态电流，如图10所示；器件具有低的栅泄漏电流，图11所示，数值均在10 -13至10 -14范围内。低关态电流说明复合晶型铟锡锌氧化物薄膜的缺陷态较少，以及通过干法刻蚀工艺刻蚀的间隔层垂直侧面具有较少的界面态。而低栅泄漏电流说明复合晶型铟锡锌氧化物薄膜与基于TEOS等有机源等离子体增强化学气相沉积的二氧化硅层之间具有极高质量的界面，表现出优异的绝缘性能。 The vertical structure thin film transistor based on the composite crystal type indium tin zinc oxide active layer manufactured by the above method in this embodiment was tested. The transfer characteristic curve of the vertical structure thin film transistor is shown in Fig. 10 and Fig. 11, and its electrical characteristics can be found. Superior performance. In particular, the device has a low off-state current, as shown in Fig. 10; the device has a low gate leakage current, as shown in Fig. 11, the values are all in the range of 10-13 to 10-14. The low off-state current indicates that the composite crystalline indium tin zinc oxide film has fewer defect states, and the vertical side of the spacer layer etched by the dry etching process has fewer interface states. The low gate leakage current shows that the composite crystal indium tin zinc oxide film and the silicon dioxide layer based on organic source plasma-enhanced chemical vapor deposition such as TEOS have an extremely high-quality interface and exhibit excellent insulation properties.
以上是对本发明的较佳实施进行了具体说明，但本发明创造并不限于所述实施例，熟悉本领域的技术人员在不违背本发明精神的前提下还可做作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。The above is a detailed description of the preferred implementation of the present invention, but the invention is not limited to the described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. These equivalent modifications or replacements are all included in the scope defined by the claims of this application.

Claims (10)

  1. 垂直结构的复合晶型金属氧化物薄膜晶体管，其特征在于，包括衬底、源极、间隔层、漏极、有源层、双层栅介质层、栅极及测试电极；其中，所述源极设置于所述衬底表面；所述间隔层的一部分设置于所述源极表面，所述间隔层的另一部分设置于所述衬底表面；所述漏极设置于所述间隔层表面；所述有源层的一部分设置于所述漏极表面，所述有源层的另一部分设置于所述源极表面；所述双层栅介质层的一部分设置于所述漏极表面，所述双层栅介质层的一部分设置于所述有源层表面，所述双层栅介质层的另一部分设置于所述源极表面；所述栅极设置于所述双层栅介质层表面，且所述栅极在所述衬底上的投影范围小于所述有源层在所述衬底上的投影范围；所述测试电极的第一部分设置于所述源极表面且与所述双层栅介质层均有接触，所述测试电极的第二部分设置于所述漏极表面且与所述双层栅介质层均有接触；所述栅极、所述源极及所述漏极在所述有源层的投影范围均有交叠；所述有源层是具有复合晶型的无机金属氧化物。The composite crystal metal oxide thin film transistor with a vertical structure is characterized by comprising a substrate, a source electrode, a spacer layer, a drain electrode, an active layer, a double-layer gate dielectric layer, a gate electrode and a test electrode; wherein, the source The electrode is arranged on the surface of the substrate; a part of the spacer layer is arranged on the surface of the source electrode, and another part of the spacer layer is arranged on the surface of the substrate; the drain electrode is arranged on the surface of the spacer layer; A part of the active layer is disposed on the surface of the drain, and another part of the active layer is disposed on the surface of the source; a part of the double-layer gate dielectric layer is disposed on the surface of the drain, and the A part of the double-layer gate dielectric layer is disposed on the surface of the active layer, another part of the double-layer gate dielectric layer is disposed on the surface of the source electrode; the gate is disposed on the surface of the double-layer gate dielectric layer, and The projection range of the gate on the substrate is smaller than the projection range of the active layer on the substrate; the first part of the test electrode is arranged on the surface of the source and is connected to the double-layer gate The dielectric layer is in contact, the second part of the test electrode is arranged on the surface of the drain and is in contact with the double-layer gate dielectric layer; the gate, the source and the drain are in contact with each other The projection ranges of the active layer overlap; the active layer is an inorganic metal oxide with a composite crystal type.
  2. 根据权利要求1所述的垂直结构的复合晶型金属氧化物薄膜晶体管，其特征在于，所述衬底包括表面覆有缓冲层的硅片、玻璃或柔性材料中的一种。The composite crystal metal oxide thin film transistor with a vertical structure according to claim 1, wherein the substrate comprises one of a silicon wafer, glass or a flexible material covered with a buffer layer on the surface.
  3. 根据权利要求2所述的垂直结构的复合晶型金属氧化物薄膜晶体管，其特征在于，所述缓冲层包括二氧化硅、氮化硅或二氧化硅与氮化硅组合物中的一种。The composite crystal metal oxide thin film transistor with a vertical structure according to claim 2, wherein the buffer layer comprises one of silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride.
  4. 根据权利要求1所述的垂直结构的复合晶型金属氧化物薄膜晶体管，其特征在于，所述源极、所述漏极、所述栅极及所述测试电极均包括金属、导电金属氧化物或有机导电材料中的一种。The composite crystal metal oxide thin film transistor with a vertical structure according to claim 1, wherein the source electrode, the drain electrode, the gate electrode and the test electrode all comprise metal, conductive metal oxide Or one of organic conductive materials.
  5. 根据权利要求4所述的垂直结构的复合晶型金属氧化物薄膜晶体管，其特征在于，所述源极及所述漏极的厚度范围均为30～60nm。4. The composite crystal metal oxide thin film transistor with a vertical structure according to claim 4, wherein the thickness of the source electrode and the drain electrode are both in the range of 30-60 nm.
  6. 根据权利要求5所述的垂直结构的复合晶型金属氧化物薄膜晶体管，其特征在于，所述栅极及所述测试电极的厚度范围均为100～300nm。The composite crystal metal oxide thin film transistor with a vertical structure according to claim 5, wherein the thickness of the gate and the test electrode are both in the range of 100-300 nm.
  7. 根据权利要求1所述的垂直结构的复合晶型金属氧化物薄膜晶体管，其特征在于，所述间隔层包括二氧化硅、氮化硅、氧化铝、PI、PET或光刻胶中的一种。The composite crystal metal oxide thin film transistor with a vertical structure according to claim 1, wherein the spacer layer comprises one of silicon dioxide, silicon nitride, aluminum oxide, PI, PET or photoresist .
  8. 根据权利要求7所述的垂直结构的复合晶型金属氧化物薄膜晶体管，其特征在于，所述间隔层的厚度范围为300～500nm。8. The composite crystal metal oxide thin film transistor with a vertical structure according to claim 7, wherein the thickness of the spacer layer is in the range of 300 to 500 nm.
  9. 垂直结构的复合晶型金属氧化物薄膜晶体管的制造方法，其特征在于，包括以下步骤：The method for manufacturing a composite crystal metal oxide thin film transistor with a vertical structure is characterized in that it comprises the following steps:
    在衬底材料表面沉积缓冲层；Deposit a buffer layer on the surface of the substrate material;
    在所述衬底的缓冲层表面沉积第一导电薄膜，并对第一导电薄膜进行图形化处理，形成源极；Depositing a first conductive film on the surface of the buffer layer of the substrate, and patterning the first conductive film to form a source;
    在所述图形化处理后的衬底表面依次沉积间隔层及第二导电薄膜，并对第二导电薄膜进行图形化处理，形成漏极；Depositing a spacer layer and a second conductive film sequentially on the surface of the patterned substrate, and patterning the second conductive film to form a drain electrode;
    以所述漏极为掩膜，采用干法蚀刻工艺刻蚀间隔层，形成垂直侧壁；Using the drain electrode as a mask, the spacer layer is etched by a dry etching process to form vertical sidewalls;
    沉积具有复合晶型的氧化物薄膜，并对所述氧化物薄膜进行图形化处理，形成有源层；Depositing an oxide film with a composite crystal type, and performing patterning treatment on the oxide film to form an active layer;
    采用化学气相沉积方式分别沉积第一栅介质层和第二栅介质层；Depositing the first gate dielectric layer and the second gate dielectric layer separately by chemical vapor deposition;
    采用干法蚀刻工艺刻蚀所述第一栅介质层及所述第二栅介质层，形成所述源极及所述漏极的接触孔；Etch the first gate dielectric layer and the second gate dielectric layer by using a dry etching process to form contact holes for the source electrode and the drain electrode;
    沉积第三导电薄膜，并对所述第三导电薄膜进行图形化处理，形成栅极和测试电极。A third conductive film is deposited, and the third conductive film is patterned to form a gate and a test electrode.
  10. 根据权利要求9所述的垂直结构的复合晶型金属氧化物薄膜晶体管的制造方法，其特征在于，所述制造方法，还包括步骤：9. The method for manufacturing a composite crystal metal oxide thin film transistor with a vertical structure according to claim 9, wherein the manufacturing method further comprises the step of:
    将制造的垂直结构的复合晶型金属氧化物薄膜晶体管进行退火处理。The manufactured vertical structure composite crystal type metal oxide thin film transistor is annealed.
PCT/CN2020/104576 2019-10-15 2020-07-24 Composite crystalline metal oxide thin film transistor having vertical structure and manufacturing method therefor WO2021073193A1 (en)

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